SystemC/SystemC-Components-Test
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Added clang format

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This commit is contained in:
Eyck Jentzsch 2017-09-25 22:00:46 +02:00
parent 363d03ebad
commit a29bfe6bae
24 changed files with 468 additions and 842 deletions
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4
.clang-format
View File

@ -36,13 +36,13 @@ BraceWrapping:
BreakBeforeBinaryOperators: None
BreakBeforeBraces: Attach
BreakBeforeTernaryOperators: true
BreakConstructorInitializersBeforeComma: false
BreakConstructorInitializersBeforeComma: true
BreakAfterJavaFieldAnnotations: false
BreakStringLiterals: true
ColumnLimit: 120
CommentPragmas: '^ IWYU pragma:'
ConstructorInitializerAllOnOneLineOrOnePerLine: false
ConstructorInitializerIndentWidth: 4
ConstructorInitializerIndentWidth: 0
ContinuationIndentWidth: 4
Cpp11BracedListStyle: true
DerivePointerAlignment: false

14
.cproject
View File

@ -21,7 +21,6 @@
<configuration artifactName="${ProjName}" buildArtefactType="org.eclipse.cdt.build.core.buildArtefactType.exe" buildProperties="org.eclipse.cdt.build.core.buildArtefactType=org.eclipse.cdt.build.core.buildArtefactType.exe,org.eclipse.cdt.build.core.buildType=org.eclipse.cdt.build.core.buildType.debug" cleanCommand="rm -rf" description="" id="cdt.managedbuild.config.gnu.macosx.exe.debug.133691581" name="Debug" parent="cdt.managedbuild.config.gnu.macosx.exe.debug">
<folderInfo id="cdt.managedbuild.config.gnu.macosx.exe.debug.133691581." name="/" resourcePath="">
<toolChain id="cdt.managedbuild.toolchain.gnu.macosx.exe.debug.500082514" name="MacOSX GCC" superClass="cdt.managedbuild.toolchain.gnu.macosx.exe.debug">
<targetPlatform binaryParser="org.eclipse.cdt.core.ELF" id="cdt.managedbuild.target.gnu.platform.macosx.exe.debug.493103663" name="Debug Platform" superClass="cdt.managedbuild.target.gnu.platform.macosx.exe.debug"/>
<targetPlatform binaryParser="org.eclipse.cdt.core.ELF;org.eclipse.cdt.core.GNU_ELF" id="cdt.managedbuild.target.gnu.platform.macosx.exe.debug.493103663" name="Debug Platform" superClass="cdt.managedbuild.target.gnu.platform.macosx.exe.debug"/>
<builder buildPath="${workspace_loc:/sc-components-test/build}" id="cdt.managedbuild.target.gnu.builder.base.214255941" keepEnvironmentInBuildfile="true" managedBuildOn="false" name="Gnu Make Builder" superClass="cdt.managedbuild.target.gnu.builder.base"/>
<tool id="cdt.managedbuild.tool.macosx.c.linker.macosx.exe.debug.1022976995" name="MacOS X C Linker" superClass="cdt.managedbuild.tool.macosx.c.linker.macosx.exe.debug"/>
@ -172,10 +171,12 @@
<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
</scannerConfigBuildInfo>
</storageModule>
<storageModule moduleId="org.eclipse.cdt.internal.ui.text.commentOwnerProjectMappings"/>
<storageModule moduleId="org.eclipse.cdt.make.core.buildtargets">
<buildTargets>
<target name="all" path="build" targetID="org.eclipse.cdt.build.MakeTargetBuilder">
<buildCommand>make</buildCommand>
<buildArguments/>
<buildTarget>all</buildTarget>
<stopOnError>true</stopOnError>
<useDefaultCommand>true</useDefaultCommand>
@ -183,6 +184,7 @@
</target>
<target name="all VERBOSE=1" path="build" targetID="org.eclipse.cdt.build.MakeTargetBuilder">
<buildCommand>make</buildCommand>
<buildArguments/>
<buildTarget>all VERBOSE=1</buildTarget>
<stopOnError>true</stopOnError>
<useDefaultCommand>true</useDefaultCommand>
@ -190,13 +192,19 @@
</target>
<target name="clean" path="build" targetID="org.eclipse.cdt.build.MakeTargetBuilder">
<buildCommand>make</buildCommand>
<buildArguments/>
<buildTarget>clean</buildTarget>
<stopOnError>true</stopOnError>
<useDefaultCommand>true</useDefaultCommand>
<runAllBuilders>true</runAllBuilders>
</target>
<target name="clangformat" path="build" targetID="org.eclipse.cdt.build.MakeTargetBuilder">
<buildCommand>make</buildCommand>
<buildArguments/>
<buildTarget>clangformat</buildTarget>
<stopOnError>true</stopOnError>
<useDefaultCommand>true</useDefaultCommand>
<runAllBuilders>true</runAllBuilders>
</target>
</buildTargets>
</storageModule>
<storageModule moduleId="org.eclipse.cdt.internal.ui.text.commentOwnerProjectMappings"/>
</cproject>

2
CMakeLists.txt
View File

@ -42,6 +42,8 @@ if(SCV_FOUND)
link_directories(${SCV_LIBRARY_DIRS})
endif(SCV_FOUND)
set(PROJECT_3PARTY_DIRS external sr_report sr_signal)
include(sc-components/cmake/clang-format.cmake)
add_subdirectory(sc-components)
add_subdirectory(examples)

3
examples/simple_system/gen/e300_plat_t.h
View File

@ -15,7 +15,8 @@
******************************************************************************/
#ifndef _E300_PLAT_MAP_H_
#define _E300_PLAT_MAP_H_
// need double braces, see https://stackoverflow.com/questions/6893700/how-to-construct-stdarray-object-with-initializer-list#6894191
// need double braces, see
// https://stackoverflow.com/questions/6893700/how-to-construct-stdarray-object-with-initializer-list#6894191
const std::array<sysc::target_memory_map_entry<32>, 4> e300_plat_map = {{
{&i_plic, 0x0c000000, 0x200008},
{&i_gpio, 0x10012000, 0x1000},

19
examples/simple_system/gen/gpio_regs.h
View File

@ -36,17 +36,14 @@
#ifndef _GPIO_REGS_H_
#define _GPIO_REGS_H_
#include <sysc/utilities.h>
#include <util/bit_field.h>
#include <sysc/register.h>
#include <sysc/tlm_target.h>
#include <sysc/utilities.h>
#include <util/bit_field.h>
namespace sysc {
class gpio_regs :
public sc_core::sc_module,
public sysc::resetable
{
class gpio_regs : public sc_core::sc_module, public sysc::resetable {
protected:
// storage declarations
uint32_t r_value;
@ -105,8 +102,7 @@ protected:
public:
gpio_regs(sc_core::sc_module_name nm);
template<unsigned BUSWIDTH=32>
void registerResources(sysc::tlm_target<BUSWIDTH>& target);
template <unsigned BUSWIDTH = 32> void registerResources(sysc::tlm_target<BUSWIDTH> &target);
};
}
//////////////////////////////////////////////////////////////////////////////
@ -131,12 +127,9 @@ inline sysc::gpio_regs::gpio_regs(sc_core::sc_module_name nm)
, NAMED(low_ip, r_low_ip, 0, *this)
, NAMED(iof_en, r_iof_en, 0, *this)
, NAMED(iof_sel, r_iof_sel, 0, *this)
, NAMED(out_xor, r_out_xor, 0, *this)
{
}
, NAMED(out_xor, r_out_xor, 0, *this) {}
template<unsigned BUSWIDTH>
inline void sysc::gpio_regs::registerResources(sysc::tlm_target<BUSWIDTH>& target) {
template <unsigned BUSWIDTH> inline void sysc::gpio_regs::registerResources(sysc::tlm_target<BUSWIDTH> &target) {
target.addResource(value, 0x0UL);
target.addResource(input_en, 0x4UL);
target.addResource(output_en, 0x8UL);

21
examples/simple_system/gen/plic_regs.h
View File

@ -36,22 +36,19 @@
#ifndef _PLIC_REGS_H_
#define _PLIC_REGS_H_
#include <sysc/utilities.h>
#include <util/bit_field.h>
#include <sysc/register.h>
#include <sysc/tlm_target.h>
#include <sysc/utilities.h>
#include <util/bit_field.h>
namespace sysc {
class plic_regs :
public sc_core::sc_module,
public sysc::resetable
{
class plic_regs : public sc_core::sc_module, public sysc::resetable {
public:
// storage declarations
BEGIN_BF_DECL(priority_t, uint32_t);
BF_FIELD(priority, 0, 3);
END_BF_DECL() ;
END_BF_DECL();
std::array<priority_t, 255> r_priority;
uint32_t r_pending;
@ -73,8 +70,7 @@ public:
plic_regs(sc_core::sc_module_name nm);
template<unsigned BUSWIDTH=32>
void registerResources(sysc::tlm_target<BUSWIDTH>& target);
template <unsigned BUSWIDTH = 32> void registerResources(sysc::tlm_target<BUSWIDTH> &target);
};
}
//////////////////////////////////////////////////////////////////////////////
@ -87,12 +83,9 @@ inline sysc::plic_regs::plic_regs(sc_core::sc_module_name nm)
, NAMED(pending, r_pending, 0, *this)
, NAMED(enabled, r_enabled, 0, *this)
, NAMED(threshold, r_threshold, 0, *this)
, NAMED(claim_complete, r_claim_complete, 0, *this)
{
}
, NAMED(claim_complete, r_claim_complete, 0, *this) {}
template<unsigned BUSWIDTH>
inline void sysc::plic_regs::registerResources(sysc::tlm_target<BUSWIDTH>& target) {
template <unsigned BUSWIDTH> inline void sysc::plic_regs::registerResources(sysc::tlm_target<BUSWIDTH> &target) {
target.addResource(priority, 0x4UL);
target.addResource(pending, 0x1000UL);
target.addResource(enabled, 0x2000UL);

19
examples/simple_system/gen/spi_regs.h
View File

@ -36,17 +36,14 @@
#ifndef _SPI_REGS_H_
#define _SPI_REGS_H_
#include <sysc/utilities.h>
#include <util/bit_field.h>
#include <sysc/register.h>
#include <sysc/tlm_target.h>
#include <sysc/utilities.h>
#include <util/bit_field.h>
namespace sysc {
class spi_regs :
public sc_core::sc_module,
public sysc::resetable
{
class spi_regs : public sc_core::sc_module, public sysc::resetable {
protected:
// storage declarations
BEGIN_BF_DECL(sckdiv_t, uint32_t);
@ -147,8 +144,7 @@ protected:
public:
spi_regs(sc_core::sc_module_name nm);
template<unsigned BUSWIDTH=32>
void registerResources(sysc::tlm_target<BUSWIDTH>& target);
template <unsigned BUSWIDTH = 32> void registerResources(sysc::tlm_target<BUSWIDTH> &target);
};
}
//////////////////////////////////////////////////////////////////////////////
@ -172,12 +168,9 @@ inline sysc::spi_regs::spi_regs(sc_core::sc_module_name nm)
, NAMED(fctrl, r_fctrl, 0, *this)
, NAMED(ffmt, r_ffmt, 0, *this)
, NAMED(ie, r_ie, 0, *this)
, NAMED(ip, r_ip, 0, *this)
{
}
, NAMED(ip, r_ip, 0, *this) {}
template<unsigned BUSWIDTH>
inline void sysc::spi_regs::registerResources(sysc::tlm_target<BUSWIDTH>& target) {
template <unsigned BUSWIDTH> inline void sysc::spi_regs::registerResources(sysc::tlm_target<BUSWIDTH> &target) {
target.addResource(sckdiv, 0x0UL);
target.addResource(sckmode, 0x4UL);
target.addResource(csid, 0x10UL);

19
examples/simple_system/gen/uart_regs.h
View File

@ -36,17 +36,14 @@
#ifndef _UART_REGS_H_
#define _UART_REGS_H_
#include <sysc/utilities.h>
#include <util/bit_field.h>
#include <sysc/register.h>
#include <sysc/tlm_target.h>
#include <sysc/utilities.h>
#include <util/bit_field.h>
namespace sysc {
class uart_regs :
public sc_core::sc_module,
public sysc::resetable
{
class uart_regs : public sc_core::sc_module, public sysc::resetable {
protected:
// storage declarations
BEGIN_BF_DECL(txdata_t, uint32_t);
@ -98,8 +95,7 @@ protected:
public:
uart_regs(sc_core::sc_module_name nm);
template<unsigned BUSWIDTH=32>
void registerResources(sysc::tlm_target<BUSWIDTH>& target);
template <unsigned BUSWIDTH = 32> void registerResources(sysc::tlm_target<BUSWIDTH> &target);
};
}
//////////////////////////////////////////////////////////////////////////////
@ -114,12 +110,9 @@ inline sysc::uart_regs::uart_regs(sc_core::sc_module_name nm)
, NAMED(rxctrl, r_rxctrl, 0, *this)
, NAMED(ie, r_ie, 0, *this)
, NAMED(ip, r_ip, 0, *this)
, NAMED(div, r_div, 0, *this)
{
}
, NAMED(div, r_div, 0, *this) {}
template<unsigned BUSWIDTH>
inline void sysc::uart_regs::registerResources(sysc::tlm_target<BUSWIDTH>& target) {
template <unsigned BUSWIDTH> inline void sysc::uart_regs::registerResources(sysc::tlm_target<BUSWIDTH> &target) {
target.addResource(txdata, 0x0UL);
target.addResource(rxdata, 0x4UL);
target.addResource(txctrl, 0x8UL);

15
examples/simple_system/gpio.cpp
View File

@ -25,23 +25,20 @@ gpio::gpio(sc_core::sc_module_name nm)
, tlm_target<>(clk)
, NAMED(clk_i)
, NAMED(rst_i)
, NAMEDD(gpio_regs, regs)
{
, NAMEDD(gpio_regs, regs) {
regs->registerResources(*this);
SC_METHOD(clock_cb);
sensitive<<clk_i;
sensitive << clk_i;
SC_METHOD(reset_cb);
sensitive<<rst_i;
sensitive << rst_i;
}
gpio::~gpio() {
}
gpio::~gpio() {}
void gpio::clock_cb() {
}
void gpio::clock_cb() {}
void gpio::reset_cb() {
if(rst_i.read())
if (rst_i.read())
regs->reset_start();
else
regs->reset_stop();

3
examples/simple_system/gpio.h
View File

@ -23,13 +23,14 @@ namespace sysc {
class gpio_regs;
class gpio: public sc_core::sc_module, public tlm_target<> {
class gpio : public sc_core::sc_module, public tlm_target<> {
public:
SC_HAS_PROCESS(gpio);
sc_core::sc_in<sc_core::sc_time> clk_i;
sc_core::sc_in<bool> rst_i;
gpio(sc_core::sc_module_name nm);
virtual ~gpio();
protected:
void clock_cb();
void reset_cb();

69
examples/simple_system/plic.cpp
View File

@ -60,25 +60,22 @@ plic::plic(sc_core::sc_module_name nm)
// port callbacks
SC_METHOD(global_int_port_cb);
for(uint8_t i = 0; i<255; i++) {
for (uint8_t i = 0; i < 255; i++) {
sensitive << global_interrupts_i[i].pos();
}
dont_initialize();
// register event callbacks
SC_METHOD(clock_cb);
sensitive<<clk_i;
sensitive << clk_i;
SC_METHOD(reset_cb);
sensitive<<rst_i;
sensitive << rst_i;
}
plic::~plic() {
}
plic::~plic() {}
void plic::init_callbacks()
{
m_claim_complete_write_cb = [=](sysc::sc_register<uint32_t> reg, uint32_t v)->bool {
void plic::init_callbacks() {
m_claim_complete_write_cb = [=](sysc::sc_register<uint32_t> reg, uint32_t v) -> bool {
reg.put(v);
reset_pending_int(v);
// std::cout << "Value of register: 0x" << std::hex << reg << std::endl;
@ -87,15 +84,10 @@ void plic::init_callbacks()
};
}
void plic::clock_cb() { this->clk = clk_i.read(); }
void plic::clock_cb()
{
this->clk=clk_i.read();
}
void plic::reset_cb()
{
if(rst_i.read())
void plic::reset_cb() {
if (rst_i.read())
regs->reset_start();
else
regs->reset_stop();
@ -117,28 +109,25 @@ void plic::reset_cb()
// - called by:
// - complete-reg write register content
void plic::global_int_port_cb()
{
void plic::global_int_port_cb() {
// set related pending bit if enable is set for incoming global_interrupt
// todo: extend up to 255 bits (limited to 32 right now)
for(uint32_t i = 1; i<32; i++) {
for (uint32_t i = 1; i < 32; i++) {
uint32_t enable_bits = regs->r_enabled;
bool enable = enable_bits & (0x1 << i); // read enable bit
if ( enable && global_interrupts_i[i].read() == 1 ) {
regs->r_pending = regs->r_pending | ( 0x1 << i);
LOG(logging::INFO) << "pending interrupt identified: " << i;
if (enable && global_interrupts_i[i].read() == 1) {
regs->r_pending = regs->r_pending | (0x1 << i);
LOG(INFO) << "pending interrupt identified: " << i;
}
}
handle_pending_int();
}
void plic::handle_pending_int()
{
void plic::handle_pending_int() {
// identify high-prio pending interrupt and raise a core-interrupt
uint32_t claim_int = 0; // claim interrupt
uint32_t claim_prio = 0; // related priority (highest prio interrupt wins the race)
@ -146,41 +135,38 @@ void plic::handle_pending_int()
uint32_t thold = regs->r_threshold.threshold; // threshold value
// todo: extend up to 255 bits (limited to 32 right now)
for(uint32_t i = 1; i<32; i++) {
for (uint32_t i = 1; i < 32; i++) {
uint32_t pending_bits = regs->r_pending;
bool pending = (pending_bits & (0x1 << i)) ? true : false;
uint32_t prio = regs->r_priority[i-1].priority; // read priority value
uint32_t prio = regs->r_priority[i - 1].priority; // read priority value
if ( pending && thold < prio )
{
regs->r_pending = regs->r_pending | ( 0x1 << i);
// below condition ensures implicitly that lowest id is selected in case of multiple identical priority-interrupts
if ( prio > claim_prio ) {
if (pending && thold < prio) {
regs->r_pending = regs->r_pending | (0x1 << i);
// below condition ensures implicitly that lowest id is selected in case of multiple identical
// priority-interrupts
if (prio > claim_prio) {
claim_prio = prio;
claim_int = i;
raise_int = 1;
LOG(logging::INFO) << "pending interrupt activated: " << i;
LOG(INFO) << "pending interrupt activated: " << i;
}
}
}
if ( raise_int ) {
if (raise_int) {
regs->r_claim_complete = claim_int;
core_interrupt_o.write(1);
// todo: evluate clock period
} else {
regs->r_claim_complete = 0;
LOG(logging::INFO) << "no further pending interrupt.";
LOG(INFO) << "no further pending interrupt.";
}
}
void plic::reset_pending_int(uint32_t irq)
{
void plic::reset_pending_int(uint32_t irq) {
// todo: evaluate enable register (see spec)
// todo: make sure that pending is set, otherwise don't reset irq ... read spec.
LOG(logging::INFO) << "reset pending interrupt: " << irq;
LOG(INFO) << "reset pending interrupt: " << irq;
// reset related pending bit
regs->r_pending &= ~(0x1 << irq);
core_interrupt_o.write(0);
@ -189,5 +175,4 @@ void plic::reset_pending_int(uint32_t irq)
handle_pending_int();
}
} /* namespace sysc */

7
examples/simple_system/plic.h
View File

@ -17,14 +17,14 @@
#ifndef _PLIC_H_
#define _PLIC_H_
#include <sysc/tlm_target.h>
#include <sysc/register.h>
#include <sysc/tlm_target.h>
namespace sysc {
class plic_regs;
class plic: public sc_core::sc_module, public tlm_target<> {
class plic : public sc_core::sc_module, public tlm_target<> {
public:
SC_HAS_PROCESS(plic);
sc_core::sc_in<sc_core::sc_time> clk_i;
@ -35,6 +35,7 @@ public:
sc_core::sc_event clear_int_ev;
plic(sc_core::sc_module_name nm);
virtual ~plic();
protected:
void clock_cb();
void reset_cb();
@ -48,7 +49,7 @@ protected:
void clear_core_interrupt();
sc_core::sc_time clk;
std::unique_ptr<plic_regs> regs;
std::function<bool(sc_register<uint32_t>,uint32_t)> m_claim_complete_write_cb;
std::function<bool(sc_register<uint32_t>, uint32_t)> m_claim_complete_write_cb;
};
} /* namespace sysc */

34
examples/simple_system/sc_main.cpp
View File

@ -21,12 +21,11 @@
*/
#include "simple_system.h"
#include <sysc/tracer.h>
#include <sysc/scv_tr_db.h>
#include <sysc/report.h>
#include <boost/program_options.hpp>
#include <sysc/report.h>
#include <sstream>
#include <sysc/report.h>
#include <sysc/scv_tr_db.h>
#include <sysc/tracer.h>
using namespace sysc;
namespace po = boost::program_options;
@ -37,34 +36,32 @@ const size_t SUCCESS = 0;
const size_t ERROR_UNHANDLED_EXCEPTION = 2;
} // namespace
int sc_main(int argc, char* argv[]){
int sc_main(int argc, char *argv[]) {
// Environment adaptations
putenv(const_cast<char*>("SC_SIGNAL_WRITE_CHECK=DISABLE"));
putenv(const_cast<char *>("SC_SIGNAL_WRITE_CHECK=DISABLE"));
// sc_report_handler::set_handler(my_report_handler);
sysc::Logger::reporting_level()=log::DEBUG;
// sc_report_handler::set_handler(my_report_handler);
sysc::Logger::reporting_level() = log::DEBUG;
// todo: add module-name to log-file
///////////////////////////////////////////////////////////////////////////
// CLI argument parsing
///////////////////////////////////////////////////////////////////////////
po::options_description desc("Options");\
desc.add_options()\
("help,h", "Print help message")\
("debug,d", po::value<int>(), "set debug level")\
("trace,t", "trace SystemC signals");
po::options_description desc("Options");
desc.add_options()("help,h", "Print help message")("debug,d", po::value<int>(),
"set debug level")("trace,t", "trace SystemC signals");
po::variables_map vm;
try {
po::store(po::parse_command_line(argc, argv, desc), vm); // can throw
// --help option
if ( vm.count("help") ){
if (vm.count("help")) {
std::cout << "JIT-ISS simulator for AVR" << std::endl << desc << std::endl;
return SUCCESS;
}
po::notify(vm); // throws on error, so do after help in case
// there are any problems
} catch(po::error& e){
} catch (po::error &e) {
std::cerr << "ERROR: " << e.what() << std::endl << std::endl;
std::cerr << desc << std::endl;
return ERROR_IN_COMMAND_LINE;
@ -79,7 +76,7 @@ int sc_main(int argc, char* argv[]){
// instantiate top level
///////////////////////////////////////////////////////////////////////////
simple_system i_simple_system("i_simple_system");
//sr_report_handler::add_sc_object_to_filter(&i_simple_system.i_master, sc_core::SC_WARNING, sc_core::SC_MEDIUM);
// sr_report_handler::add_sc_object_to_filter(&i_simple_system.i_master, sc_core::SC_WARNING, sc_core::SC_MEDIUM);
///////////////////////////////////////////////////////////////////////////
// run simulation
@ -87,10 +84,9 @@ int sc_main(int argc, char* argv[]){
sc_start(sc_core::sc_time(1, sc_core::SC_MS));
// todo: provide end-of-simulation macros
if(!sc_core::sc_end_of_simulation_invoked()) {
LOG(logging::ERROR) << "simulation timed out";
if (!sc_core::sc_end_of_simulation_invoked()) {
LOG(ERROR) << "simulation timed out";
sc_core::sc_stop();
}
return 0;
}

11
examples/simple_system/simple_system.cpp
View File

@ -35,14 +35,13 @@ simple_system::simple_system(sc_core::sc_module_name nm)
, NAMED(s_clk)
, NAMED(s_rst)
, NAMED(s_global_interrupts, 256)
, NAMED(s_core_interrupt)
{
, NAMED(s_core_interrupt) {
// todo: discuss naming conventions (s_<signal> vs. <port>_i/_o) --> covnert into _s
// bus connections
i_master.intor(i_router.target[0]);
size_t i=0;
for(const auto& e: e300_plat_map){
size_t i = 0;
for (const auto &e : e300_plat_map) {
i_router.initiator[i](e.target->socket);
i_router.add_target_range(i, e.start, e.size);
i++;
@ -71,9 +70,9 @@ simple_system::simple_system(sc_core::sc_module_name nm)
}
void simple_system::gen_reset() {
s_rst=true;
s_rst = true;
wait(10_ns);
s_rst=false;
s_rst = false;
}
} /* namespace sysc */

12
examples/simple_system/simple_system.h
View File

@ -23,20 +23,19 @@
#ifndef SIMPLESYSTEM_H_
#define SIMPLESYSTEM_H_
#include "uart.h"
#include "spi.h"
#include "gpio.h"
#include "plic.h"
#include "spi.h"
#include "uart.h"
#include "test_initiator.h"
#include <sysc/router.h>
#include <sysc/kernel/sc_module.h>
#include <array>
#include <sysc/kernel/sc_module.h>
#include <sysc/router.h>
namespace sysc {
class simple_system: public sc_core::sc_module {
class simple_system : public sc_core::sc_module {
public:
SC_HAS_PROCESS(simple_system);
@ -52,6 +51,7 @@ public:
sc_core::sc_signal<bool> s_core_interrupt;
simple_system(sc_core::sc_module_name nm);
protected:
void gen_reset();

16
examples/simple_system/spi.cpp
View File

@ -25,24 +25,20 @@ spi::spi(sc_core::sc_module_name nm)
, tlm_target<>(clk)
, NAMED(clk_i)
, NAMED(rst_i)
, NAMEDD(spi_regs, regs)
{
, NAMEDD(spi_regs, regs) {
regs->registerResources(*this);
SC_METHOD(clock_cb);
sensitive<<clk_i;
sensitive << clk_i;
SC_METHOD(reset_cb);
sensitive<<rst_i;
sensitive << rst_i;
}
spi::~spi() {
}
spi::~spi() {}
void spi::clock_cb() {
this->clk=clk_i.read();
}
void spi::clock_cb() { this->clk = clk_i.read(); }
void spi::reset_cb() {
if(rst_i.read())
if (rst_i.read())
regs->reset_start();
else
regs->reset_stop();

3
examples/simple_system/spi.h
View File

@ -23,13 +23,14 @@ namespace sysc {
class spi_regs;
class spi: public sc_core::sc_module, public tlm_target<> {
class spi : public sc_core::sc_module, public tlm_target<> {
public:
SC_HAS_PROCESS(spi);
sc_core::sc_in<sc_core::sc_time> clk_i;
sc_core::sc_in<bool> rst_i;
spi(sc_core::sc_module_name nm);
virtual ~spi();
protected:
void clock_cb();
void reset_cb();

66
examples/simple_system/test_initiator.cpp
View File

@ -21,9 +21,9 @@
*/
#include "test_initiator.h"
#include <array>
#include <sysc/report.h>
#include <sysc/utilities.h>
#include <array>
// todo: move into gen folder somewhere (adapt code-generator)
#define PLIC_PRIO1_REG 0x0C000004
@ -41,8 +41,7 @@ test_initiator::test_initiator(sc_core::sc_module_name nm)
, NAMED(intor)
, NAMED(rst_i)
, NAMED(global_interrupts_o, 256)
, NAMED(core_interrupt_i)
{
, NAMED(core_interrupt_i) {
SC_THREAD(run);
SC_METHOD(core_irq_handler);
@ -50,10 +49,9 @@ test_initiator::test_initiator(sc_core::sc_module_name nm)
dont_initialize();
}
void test_initiator::run()
{
void test_initiator::run() {
// wait for reset
if(rst_i.read()==false) wait(rst_i.posedge_event());
if (rst_i.read() == false) wait(rst_i.posedge_event());
wait(rst_i.negedge_event());
wait(10_ns);
@ -66,8 +64,7 @@ void test_initiator::run()
// todo: review irq sequences from FW point of view ... expected ???
}
void test_initiator::test_unique_irq()
{
void test_initiator::test_unique_irq() {
//// enable reg is not set
// -> irq to be ignored
@ -125,16 +122,11 @@ void test_initiator::test_unique_irq()
// todo: evaluate error messages ... provide correct pass/fail verdict
wait(100_ns);
}
void test_initiator::test_frequent_irq()
{
void test_initiator::test_frequent_irq() {}
}
void test_initiator::test_parallel_irq()
{
void test_initiator::test_parallel_irq() {
//// create three parallel global_int requests
// -> read and clear bits one after the other
@ -142,7 +134,6 @@ void test_initiator::test_parallel_irq()
// -> correct priority handing expected
// -> three core interrupts expected in total
// reverse order priority configuration
write_bus(PLIC_PRIO1_REG, 0x3);
wait(10_ns);
@ -204,29 +195,23 @@ void test_initiator::test_parallel_irq()
reg_check(PLIC_CLAIM_COMPLETE_REG, 0x0);
wait(10_ns);
// todo: advance upon register-write access ... remove above 10_ns waits
// todo: evaluate error messages ... provide correct pass/fail verdict
wait(100_ns);
}
void test_initiator::test_irq_stress()
{
void test_initiator::test_irq_stress() {}
}
void test_initiator::write_bus(std::uint32_t adr, std::uint32_t dat)
{
void test_initiator::write_bus(std::uint32_t adr, std::uint32_t dat) {
tlm::tlm_generic_payload gp;
std::array<uint8_t, 4> data;
data[3] = 0xff & dat>>24;
data[2] = 0xff & dat>>16;
data[1] = 0xff & dat>>8;
data[3] = 0xff & dat >> 24;
data[2] = 0xff & dat >> 16;
data[1] = 0xff & dat >> 8;
data[0] = 0xff & dat;
LOG(logging::INFO) << "write_bus(0x" << std::hex << adr << ") : " << dat;
LOG(INFO) << "write_bus(0x" << std::hex << adr << ") : " << dat;
gp.set_command(tlm::TLM_WRITE_COMMAND);
gp.set_address(adr);
@ -236,13 +221,12 @@ void test_initiator::write_bus(std::uint32_t adr, std::uint32_t dat)
sc_core::sc_time delay;
intor->b_transport(gp, delay);
if ( gp.get_response_status() != tlm::TLM_OK_RESPONSE ) {
if (gp.get_response_status() != tlm::TLM_OK_RESPONSE) {
throw std::exception();
}
}
std::uint32_t test_initiator::read_bus(std::uint32_t adr)
{
std::uint32_t test_initiator::read_bus(std::uint32_t adr) {
tlm::tlm_generic_payload gp;
std::array<uint8_t, 4> data;
@ -255,32 +239,30 @@ std::uint32_t test_initiator::read_bus(std::uint32_t adr)
sc_core::sc_time delay;
intor->b_transport(gp, delay);
if ( gp.get_response_status() != tlm::TLM_OK_RESPONSE ) {
if (gp.get_response_status() != tlm::TLM_OK_RESPONSE) {
// todo: improve output in case of exception, define own exception class to carry transaction-infos
// ... i.e. out-of-range report with info about legal mem boundaries
throw std::exception();
}
// todo: use reinterpret_cast instead
std::uint32_t rdat = data[3]<<24 | data[2]<<16 | data[1]<<8 | data[0];
std::uint32_t rdat = data[3] << 24 | data[2] << 16 | data[1] << 8 | data[0];
LOG(logging::INFO) << "read_bus(0x" << std::hex << adr << ") -> " << rdat;
LOG(INFO) << "read_bus(0x" << std::hex << adr << ") -> " << rdat;
return rdat;
}
void test_initiator::reg_check(std::uint32_t adr, std::uint32_t exp)
{
void test_initiator::reg_check(std::uint32_t adr, std::uint32_t exp) {
uint32_t dat = read_bus(adr);
if ( dat != exp ) {
LOG(logging::ERROR) << "register check failed for address 0x" << std::hex << adr << ": " << dat << " != " << exp;
if (dat != exp) {
LOG(ERROR) << "register check failed for address 0x" << std::hex << adr << ": " << dat << " != " << exp;
} else {
LOG(logging::INFO) << "register check passed for address 0x" << std::hex << adr << ": " << dat;
LOG(INFO) << "register check passed for address 0x" << std::hex << adr << ": " << dat;
}
}
void test_initiator::core_irq_handler()
{
LOG(logging::INFO) << "core_interrupt_i edge detected -> " << core_interrupt_i.read();
void test_initiator::core_irq_handler() {
LOG(INFO) << "core_interrupt_i edge detected -> " << core_interrupt_i.read();
}
} /* namespace sysc */

3
examples/simple_system/test_initiator.h
View File

@ -28,7 +28,7 @@
namespace sysc {
class test_initiator: public sc_core::sc_module {
class test_initiator : public sc_core::sc_module {
public:
SC_HAS_PROCESS(test_initiator);
tlm_utils::simple_initiator_socket<test_initiator, 32> intor;
@ -36,6 +36,7 @@ public:
sc_core::sc_in<bool> core_interrupt_i;
sc_core::sc_in<bool> rst_i;
test_initiator(sc_core::sc_module_name nm);
protected:
void run();
void test_unique_irq();

16
examples/simple_system/uart.cpp
View File

@ -25,24 +25,20 @@ uart::uart(sc_core::sc_module_name nm)
, tlm_target<>(clk)
, NAMED(clk_i)
, NAMED(rst_i)
, NAMEDD(uart_regs, regs)
{
, NAMEDD(uart_regs, regs) {
regs->registerResources(*this);
SC_METHOD(clock_cb);
sensitive<<clk_i;
sensitive << clk_i;
SC_METHOD(reset_cb);
sensitive<<rst_i;
sensitive << rst_i;
}
uart::~uart() {
}
uart::~uart() {}
void uart::clock_cb() {
this->clk=clk_i.read();
}
void uart::clock_cb() { this->clk = clk_i.read(); }
void uart::reset_cb() {
if(rst_i.read())
if (rst_i.read())
regs->reset_start();
else
regs->reset_stop();

3
examples/simple_system/uart.h
View File

@ -23,13 +23,14 @@ namespace sysc {
class uart_regs;
class uart: public sc_core::sc_module, public tlm_target<> {
class uart : public sc_core::sc_module, public tlm_target<> {
public:
SC_HAS_PROCESS(uart);
sc_core::sc_in<sc_core::sc_time> clk_i;
sc_core::sc_in<bool> rst_i;
uart(sc_core::sc_module_name nm);
virtual ~uart();
protected:
void clock_cb();
void reset_cb();

111
examples/transaction_recording/scv_tr_recording_example.cpp
View File

@ -22,7 +22,7 @@
const unsigned ram_size = 256;
class rw_task_if: virtual public sc_interface {
class rw_task_if : virtual public sc_interface {
public:
typedef sc_uint<8> addr_t;
typedef sc_uint<8> data_t;
@ -31,38 +31,42 @@ public:
data_t data;
};
virtual data_t read(const addr_t*) = 0;
virtual void write(const write_t*) = 0;
virtual data_t read(const addr_t *) = 0;
virtual void write(const write_t *) = 0;
};
SCV_EXTENSIONS(rw_task_if::write_t){
SCV_EXTENSIONS(rw_task_if::write_t) {
public:
scv_extensions<rw_task_if::addr_t> addr;
scv_extensions<rw_task_if::data_t> data;
SCV_EXTENSIONS_CTOR(rw_task_if::write_t) {
scv_extensions<rw_task_if::addr_t> addr;
scv_extensions<rw_task_if::data_t> data;
SCV_EXTENSIONS_CTOR(rw_task_if::write_t) {
SCV_FIELD(addr);
SCV_FIELD(data);
}
}
};
class pipelined_bus_ports: public sc_module {
class pipelined_bus_ports : public sc_module {
public:
sc_in<bool> clk;
sc_inout<bool> rw;
sc_inout<bool> addr_req;
sc_inout<bool> addr_ack;
sc_inout<sc_uint<8> > bus_addr;
sc_inout<sc_uint<8>> bus_addr;
sc_inout<bool> data_rdy;
sc_inout<sc_uint<8> > bus_data;
sc_inout<sc_uint<8>> bus_data;
SC_CTOR(pipelined_bus_ports) :
clk("clk"), rw("rw"), addr_req("addr_req"), addr_ack("addr_ack"), bus_addr("bus_addr"), data_rdy("data_rdy"), bus_data(
"bus_data") {
}
virtual void trace( sc_trace_file* tf ) const;
SC_CTOR(pipelined_bus_ports)
: clk("clk")
, rw("rw")
, addr_req("addr_req")
, addr_ack("addr_ack")
, bus_addr("bus_addr")
, data_rdy("data_rdy")
, bus_data("bus_data") {}
virtual void trace(sc_trace_file *tf) const;
};
void pipelined_bus_ports::trace( sc_trace_file* tf ) const {
void pipelined_bus_ports::trace(sc_trace_file *tf) const {
sc_trace(tf, clk, clk.name());
sc_trace(tf, rw, rw.name());
sc_trace(tf, addr_req, addr_req.name());
@ -72,46 +76,45 @@ void pipelined_bus_ports::trace( sc_trace_file* tf ) const {
sc_trace(tf, bus_data, bus_data.name());
}
class rw_pipelined_transactor: public rw_task_if, public pipelined_bus_ports {
class rw_pipelined_transactor : public rw_task_if, public pipelined_bus_ports {
fifo_mutex addr_phase;fifo_mutex data_phase;
fifo_mutex addr_phase;
fifo_mutex data_phase;
scv_tr_stream pipelined_stream;
scv_tr_stream addr_stream;
scv_tr_stream data_stream;
scv_tr_generator<sc_uint<8>, sc_uint<8> > read_gen;
scv_tr_generator<sc_uint<8>, sc_uint<8> > write_gen;
scv_tr_generator<sc_uint<8> > addr_gen;
scv_tr_generator<_scv_tr_generator_default_data, sc_uint<8> > rdata_gen;
scv_tr_generator<sc_uint<8> > wdata_gen;
scv_tr_generator<sc_uint<8>, sc_uint<8>> read_gen;
scv_tr_generator<sc_uint<8>, sc_uint<8>> write_gen;
scv_tr_generator<sc_uint<8>> addr_gen;
scv_tr_generator<_scv_tr_generator_default_data, sc_uint<8>> rdata_gen;
scv_tr_generator<sc_uint<8>> wdata_gen;
public:
rw_pipelined_transactor(sc_module_name nm)
: pipelined_bus_ports(nm)
, addr_phase("addr_phase")
, data_phase("data_phase")
, pipelined_stream((std::string(name()) +".pipelined_stream").c_str(), "transactor")
, addr_stream( (std::string(name()) +".addr_stream").c_str(), "transactor")
, data_stream((std::string(name()) +".data_stream").c_str(), "transactor")
, pipelined_stream((std::string(name()) + ".pipelined_stream").c_str(), "transactor")
, addr_stream((std::string(name()) + ".addr_stream").c_str(), "transactor")
, data_stream((std::string(name()) + ".data_stream").c_str(), "transactor")
, read_gen("read", pipelined_stream, "addr", "data")
, write_gen("write", pipelined_stream, "addr", "data")
, addr_gen("addr", addr_stream, "addr")
, rdata_gen("rdata", data_stream, NULL, "data")
, wdata_gen("wdata", data_stream, "data")
{
}
virtual data_t read(const addr_t* p_addr);
virtual void write(const write_t * req);
, wdata_gen("wdata", data_stream, "data") {}
virtual data_t read(const addr_t *p_addr);
virtual void write(const write_t *req);
};
rw_task_if::data_t rw_pipelined_transactor::read(const addr_t* addr) {
rw_task_if::data_t rw_pipelined_transactor::read(const addr_t *addr) {
addr_phase.lock();
scv_tr_handle h = read_gen.begin_transaction(*addr);
h.record_attribute("data_size", sizeof(data_t));
scv_tr_handle h1 = addr_gen.begin_transaction(*addr, "addr_phase", h);
wait(clk->posedge_event());
bus_addr = *addr;
rw=false;
rw = false;
addr_req = 1;
wait(addr_ack->posedge_event());
wait(clk->negedge_event());
@ -132,14 +135,14 @@ rw_task_if::data_t rw_pipelined_transactor::read(const addr_t* addr) {
return data;
}
void rw_pipelined_transactor::write(const write_t * req) {
void rw_pipelined_transactor::write(const write_t *req) {
addr_phase.lock();
scv_tr_handle h = write_gen.begin_transaction(req->addr);
h.record_attribute("data_size", sizeof(data_t));
scv_tr_handle h1 = addr_gen.begin_transaction(req->addr, "addr_phase", h);
wait(clk->posedge_event());
bus_addr = req->addr;
rw=true;
rw = true;
addr_req = 1;
wait(addr_ack->posedge_event());
wait(clk->negedge_event());
@ -150,7 +153,7 @@ void rw_pipelined_transactor::write(const write_t * req) {
data_phase.lock();
scv_tr_handle h2 = wdata_gen.begin_transaction(req->data, "data_phase", h);
bus_data=req->data;
bus_data = req->data;
wait(data_rdy->posedge_event());
wait(data_rdy->negedge_event());
wdata_gen.end_transaction(h2);
@ -158,11 +161,11 @@ void rw_pipelined_transactor::write(const write_t * req) {
data_phase.unlock();
}
class test: public sc_module {
class test : public sc_module {
public:
sc_port<rw_task_if> transactor;
SC_HAS_PROCESS(test);
test( ::sc_core::sc_module_name ){
test(::sc_core::sc_module_name) {
SC_THREAD(main1);
SC_THREAD(main2);
}
@ -170,16 +173,16 @@ public:
void main2();
};
class write_constraint: virtual public scv_constraint_base {
class write_constraint : virtual public scv_constraint_base {
public:
scv_smart_ptr<rw_task_if::write_t> write;SCV_CONSTRAINT_CTOR(write_constraint) {
scv_smart_ptr<rw_task_if::write_t> write;
SCV_CONSTRAINT_CTOR(write_constraint) {
SCV_CONSTRAINT(write->addr() <= ram_size);
SCV_CONSTRAINT(write->addr() != write->data());
}
};
inline void process(scv_smart_ptr<int> data) {
}
inline void process(scv_smart_ptr<int> data) {}
inline void test::main1() {
// simple sequential tests
@ -250,15 +253,15 @@ inline void test::main2() {
process(data);
}
}
class design: public pipelined_bus_ports {
std::list<sc_uint<8> > outstandingAddresses;
class design : public pipelined_bus_ports {
std::list<sc_uint<8>> outstandingAddresses;
std::list<bool> outstandingType;
sc_uint<8> memory[ram_size];
public:
SC_HAS_PROCESS(design);
design(sc_module_name nm) :
pipelined_bus_ports(nm) {
design(sc_module_name nm)
: pipelined_bus_ports(nm) {
for (unsigned i = 0; i < ram_size; ++i) {
memory[i] = i;
}
@ -311,9 +314,8 @@ inline void design::data_phase() {
data_rdy = 0;
} else {
cout << "writing memory address " << outstandingAddresses.front() << " with value "
<< bus_data << endl;
memory[outstandingAddresses.front().to_ulong()]=bus_data;
cout << "writing memory address " << outstandingAddresses.front() << " with value " << bus_data << endl;
memory[outstandingAddresses.front().to_ulong()] = bus_data;
data_rdy = 1;
wait(clk->posedge_event());
data_rdy = 0;
@ -332,19 +334,19 @@ int sc_main(int argc, char *argv[]) {
const char* fileName = "my_db.txlog";
#else
scv_tr_sqlite_init();
const char* fileName = "my_db";
const char *fileName = "my_db";
#endif
scv_tr_db db(fileName);
scv_tr_db::set_default_db(&db);
sc_trace_file* tf = sc_create_vcd_trace_file("my_db");
sc_trace_file *tf = sc_create_vcd_trace_file("my_db");
// create signals
sc_clock clk("clk", 20.0, SC_NS, 0.5, 0.0, SC_NS, true);
sc_signal<bool> rw;
sc_signal<bool> addr_req;
sc_signal<bool> addr_ack;
sc_signal<sc_uint<8> > bus_addr;
sc_signal<sc_uint<8>> bus_addr;
sc_signal<bool> data_rdy;
sc_signal<sc_uint<8> > bus_data;
sc_signal<sc_uint<8>> bus_data;
// create modules/channels
test t("t");
@ -380,4 +382,3 @@ int sc_main(int argc, char *argv[]) {
sc_close_vcd_trace_file(tf);
return 0;
}

2
sc-components

@ -1 +1 @@
Subproject commit 4bc26642e349906f6e81619ea8a26bf533c3f46f
Subproject commit cab7505af9f4093a93d7e41c519ad937bdc60f81

314
simple_system.txlog
View File

@ -1,314 +0,0 @@
scv_tr_stream (ID 1, name "i_simple_system.i_router.target_0.blocking", kind "TRANSACTOR")
scv_tr_generator (ID 2, name "read", scv_tr_stream 1,
begin_attribute (ID 0, name "start_delay", type "UNSIGNED")
end_attribute (ID 1, name "end_delay", type "UNSIGNED")
)
scv_tr_generator (ID 3, name "write", scv_tr_stream 1,
begin_attribute (ID 0, name "start_delay", type "UNSIGNED")
end_attribute (ID 1, name "end_delay", type "UNSIGNED")
)
scv_tr_generator (ID 4, name "ignore", scv_tr_stream 1,
begin_attribute (ID 0, name "start_delay", type "UNSIGNED")
end_attribute (ID 1, name "end_delay", type "UNSIGNED")
)
tx_begin 1 2 20 ns
a 0
scv_tr_stream (ID 5, name "i_simple_system.i_router.intor_0.blocking", kind "TRANSACTOR")
scv_tr_generator (ID 6, name "read", scv_tr_stream 5,
begin_attribute (ID 0, name "start_delay", type "UNSIGNED")
end_attribute (ID 1, name "end_delay", type "UNSIGNED")
)
scv_tr_generator (ID 7, name "write", scv_tr_stream 5,
begin_attribute (ID 0, name "start_delay", type "UNSIGNED")
end_attribute (ID 1, name "end_delay", type "UNSIGNED")
)
scv_tr_generator (ID 8, name "ignore", scv_tr_stream 5,
begin_attribute (ID 0, name "start_delay", type "UNSIGNED")
end_attribute (ID 1, name "end_delay", type "UNSIGNED")
)
tx_begin 2 6 20 ns
a 0
tx_relation "PRED/SUCC" 2 1
scv_tr_stream (ID 9, name "i_simple_system.i_plic.socket.blocking", kind "TRANSACTOR")
scv_tr_generator (ID 10, name "read", scv_tr_stream 9,
begin_attribute (ID 0, name "start_delay", type "UNSIGNED")
end_attribute (ID 1, name "end_delay", type "UNSIGNED")
)
scv_tr_generator (ID 11, name "write", scv_tr_stream 9,
begin_attribute (ID 0, name "start_delay", type "UNSIGNED")
end_attribute (ID 1, name "end_delay", type "UNSIGNED")
)
scv_tr_generator (ID 12, name "ignore", scv_tr_stream 9,
begin_attribute (ID 0, name "start_delay", type "UNSIGNED")
end_attribute (ID 1, name "end_delay", type "UNSIGNED")
)
tx_begin 3 10 20 ns
a 0
tx_relation "PRED/SUCC" 3 2
tx_record_attribute 3 "trans.address" UNSIGNED = 4
tx_record_attribute 3 "trans.command" ENUMERATION = "tlm::TLM_READ_COMMAND"
tx_record_attribute 3 "trans.data" POINTER = 0
tx_record_attribute 3 "trans.data_length" UNSIGNED = 4
tx_record_attribute 3 "trans.response_status" ENUMERATION = "tlm::TLM_OK_RESPONSE"
tx_record_attribute 3 "trans.dmi" BOOLEAN = false
tx_record_attribute 3 "trans.byte_enable" POINTER = 0
tx_record_attribute 3 "trans.byte_enable_length" UNSIGNED = 0
tx_record_attribute 3 "trans.streaming_width" UNSIGNED = 4
tx_record_attribute 3 "trans.gp_option" ENUMERATION = "tlm::TLM_MIN_PAYLOAD"
tx_record_attribute 3 "trans.data_value" UNSIGNED = 0
tx_end 3 10 20 ns
a 10000
tx_record_attribute 2 "trans.address" UNSIGNED = 4
tx_record_attribute 2 "trans.command" ENUMERATION = "tlm::TLM_READ_COMMAND"
tx_record_attribute 2 "trans.data" POINTER = 0
tx_record_attribute 2 "trans.data_length" UNSIGNED = 4
tx_record_attribute 2 "trans.response_status" ENUMERATION = "tlm::TLM_OK_RESPONSE"
tx_record_attribute 2 "trans.dmi" BOOLEAN = false
tx_record_attribute 2 "trans.byte_enable" POINTER = 0
tx_record_attribute 2 "trans.byte_enable_length" UNSIGNED = 0
tx_record_attribute 2 "trans.streaming_width" UNSIGNED = 4
tx_record_attribute 2 "trans.gp_option" ENUMERATION = "tlm::TLM_MIN_PAYLOAD"
tx_record_attribute 2 "trans.data_value" UNSIGNED = 0
tx_end 2 6 20 ns
a 10000
tx_record_attribute 1 "trans.address" UNSIGNED = 201326596
tx_record_attribute 1 "trans.command" ENUMERATION = "tlm::TLM_READ_COMMAND"
tx_record_attribute 1 "trans.data" POINTER = 0
tx_record_attribute 1 "trans.data_length" UNSIGNED = 4
tx_record_attribute 1 "trans.response_status" ENUMERATION = "tlm::TLM_OK_RESPONSE"
tx_record_attribute 1 "trans.dmi" BOOLEAN = false
tx_record_attribute 1 "trans.byte_enable" POINTER = 0
tx_record_attribute 1 "trans.byte_enable_length" UNSIGNED = 0
tx_record_attribute 1 "trans.streaming_width" UNSIGNED = 4
tx_record_attribute 1 "trans.gp_option" ENUMERATION = "tlm::TLM_MIN_PAYLOAD"
tx_record_attribute 1 "trans.data_value" UNSIGNED = 0
tx_end 1 2 20 ns
a 10000
scv_tr_stream (ID 13, name "i_simple_system.i_plic.socket.bl_t_ann", kind "TRANSACTOR")
scv_tr_generator (ID 14, name "read", scv_tr_stream 13,
begin_attribute (ID 0, name "<anonymous>", type "ENUMERATION")
end_attribute (ID 1, name "<anonymous>", type "ENUMERATION")
)
scv_tr_generator (ID 15, name "write", scv_tr_stream 13,
begin_attribute (ID 0, name "<anonymous>", type "ENUMERATION")
end_attribute (ID 1, name "<anonymous>", type "ENUMERATION")
)
scv_tr_generator (ID 16, name "ignore", scv_tr_stream 13,
begin_attribute (ID 0, name "<anonymous>", type "ENUMERATION")
end_attribute (ID 1, name "<anonymous>", type "ENUMERATION")
)
tx_begin 4 14 20 ns
a "tlm::TLM_READ_COMMAND"
tx_record_attribute 4 "trans.address" UNSIGNED = 4
tx_record_attribute 4 "trans.command" ENUMERATION = "tlm::TLM_READ_COMMAND"
tx_record_attribute 4 "trans.data" POINTER = 0
tx_record_attribute 4 "trans.data_length" UNSIGNED = 4
tx_record_attribute 4 "trans.response_status" ENUMERATION = "tlm::TLM_INCOMPLETE_RESPONSE"
tx_record_attribute 4 "trans.dmi" BOOLEAN = false
tx_record_attribute 4 "trans.byte_enable" POINTER = 0
tx_record_attribute 4 "trans.byte_enable_length" UNSIGNED = 0
tx_record_attribute 4 "trans.streaming_width" UNSIGNED = 4
tx_record_attribute 4 "trans.gp_option" ENUMERATION = "tlm::TLM_MIN_PAYLOAD"
tx_relation "PARENT/CHILD" 4 3
scv_tr_stream (ID 17, name "i_simple_system.i_router.intor_0.bl_t_ann", kind "TRANSACTOR")
scv_tr_generator (ID 18, name "read", scv_tr_stream 17,
begin_attribute (ID 0, name "<anonymous>", type "ENUMERATION")
end_attribute (ID 1, name "<anonymous>", type "ENUMERATION")
)
scv_tr_generator (ID 19, name "write", scv_tr_stream 17,
begin_attribute (ID 0, name "<anonymous>", type "ENUMERATION")
end_attribute (ID 1, name "<anonymous>", type "ENUMERATION")
)
scv_tr_generator (ID 20, name "ignore", scv_tr_stream 17,
begin_attribute (ID 0, name "<anonymous>", type "ENUMERATION")
end_attribute (ID 1, name "<anonymous>", type "ENUMERATION")
)
tx_begin 5 18 20 ns
a "tlm::TLM_READ_COMMAND"
tx_record_attribute 5 "trans.address" UNSIGNED = 4
tx_record_attribute 5 "trans.command" ENUMERATION = "tlm::TLM_READ_COMMAND"
tx_record_attribute 5 "trans.data" POINTER = 0
tx_record_attribute 5 "trans.data_length" UNSIGNED = 4
tx_record_attribute 5 "trans.response_status" ENUMERATION = "tlm::TLM_INCOMPLETE_RESPONSE"
tx_record_attribute 5 "trans.dmi" BOOLEAN = false
tx_record_attribute 5 "trans.byte_enable" POINTER = 0
tx_record_attribute 5 "trans.byte_enable_length" UNSIGNED = 0
tx_record_attribute 5 "trans.streaming_width" UNSIGNED = 4
tx_record_attribute 5 "trans.gp_option" ENUMERATION = "tlm::TLM_MIN_PAYLOAD"
tx_relation "PARENT/CHILD" 5 2
scv_tr_stream (ID 21, name "i_simple_system.i_router.target_0.bl_t_ann", kind "TRANSACTOR")
scv_tr_generator (ID 22, name "read", scv_tr_stream 21,
begin_attribute (ID 0, name "<anonymous>", type "ENUMERATION")
end_attribute (ID 1, name "<anonymous>", type "ENUMERATION")
)
scv_tr_generator (ID 23, name "write", scv_tr_stream 21,
begin_attribute (ID 0, name "<anonymous>", type "ENUMERATION")
end_attribute (ID 1, name "<anonymous>", type "ENUMERATION")
)
scv_tr_generator (ID 24, name "ignore", scv_tr_stream 21,
begin_attribute (ID 0, name "<anonymous>", type "ENUMERATION")
end_attribute (ID 1, name "<anonymous>", type "ENUMERATION")
)
tx_begin 6 22 20 ns
a "tlm::TLM_READ_COMMAND"
tx_record_attribute 6 "trans.address" UNSIGNED = 201326596
tx_record_attribute 6 "trans.command" ENUMERATION = "tlm::TLM_READ_COMMAND"
tx_record_attribute 6 "trans.data" POINTER = 0
tx_record_attribute 6 "trans.data_length" UNSIGNED = 4
tx_record_attribute 6 "trans.response_status" ENUMERATION = "tlm::TLM_INCOMPLETE_RESPONSE"
tx_record_attribute 6 "trans.dmi" BOOLEAN = false
tx_record_attribute 6 "trans.byte_enable" POINTER = 0
tx_record_attribute 6 "trans.byte_enable_length" UNSIGNED = 0
tx_record_attribute 6 "trans.streaming_width" UNSIGNED = 4
tx_record_attribute 6 "trans.gp_option" ENUMERATION = "tlm::TLM_MIN_PAYLOAD"
tx_relation "PARENT/CHILD" 6 1
tx_end 6 22 30 ns
a "tlm::TLM_INCOMPLETE_RESPONSE"
tx_end 5 18 30 ns
a "tlm::TLM_INCOMPLETE_RESPONSE"
tx_end 4 14 30 ns
a "tlm::TLM_INCOMPLETE_RESPONSE"
tx_begin 7 3 30 ns
a 10000
scv_tr_stream (ID 25, name "i_simple_system.i_router.intor_1.blocking", kind "TRANSACTOR")
scv_tr_generator (ID 26, name "read", scv_tr_stream 25,
begin_attribute (ID 0, name "start_delay", type "UNSIGNED")
end_attribute (ID 1, name "end_delay", type "UNSIGNED")
)
scv_tr_generator (ID 27, name "write", scv_tr_stream 25,
begin_attribute (ID 0, name "start_delay", type "UNSIGNED")
end_attribute (ID 1, name "end_delay", type "UNSIGNED")
)
scv_tr_generator (ID 28, name "ignore", scv_tr_stream 25,
begin_attribute (ID 0, name "start_delay", type "UNSIGNED")
end_attribute (ID 1, name "end_delay", type "UNSIGNED")
)
tx_begin 8 27 30 ns
a 10000
tx_relation "PRED/SUCC" 8 7
scv_tr_stream (ID 29, name "i_simple_system.i_gpio.socket.blocking", kind "TRANSACTOR")
scv_tr_generator (ID 30, name "read", scv_tr_stream 29,
begin_attribute (ID 0, name "start_delay", type "UNSIGNED")
end_attribute (ID 1, name "end_delay", type "UNSIGNED")
)
scv_tr_generator (ID 31, name "write", scv_tr_stream 29,
begin_attribute (ID 0, name "start_delay", type "UNSIGNED")
end_attribute (ID 1, name "end_delay", type "UNSIGNED")
)
scv_tr_generator (ID 32, name "ignore", scv_tr_stream 29,
begin_attribute (ID 0, name "start_delay", type "UNSIGNED")
end_attribute (ID 1, name "end_delay", type "UNSIGNED")
)
tx_begin 9 31 30 ns
a 10000
tx_relation "PRED/SUCC" 9 8
tx_record_attribute 9 "trans.address" UNSIGNED = 0
tx_record_attribute 9 "trans.command" ENUMERATION = "tlm::TLM_WRITE_COMMAND"
tx_record_attribute 9 "trans.data" POINTER = 0
tx_record_attribute 9 "trans.data_length" UNSIGNED = 4
tx_record_attribute 9 "trans.response_status" ENUMERATION = "tlm::TLM_OK_RESPONSE"
tx_record_attribute 9 "trans.dmi" BOOLEAN = false
tx_record_attribute 9 "trans.byte_enable" POINTER = 0
tx_record_attribute 9 "trans.byte_enable_length" UNSIGNED = 0
tx_record_attribute 9 "trans.streaming_width" UNSIGNED = 4
tx_record_attribute 9 "trans.gp_option" ENUMERATION = "tlm::TLM_MIN_PAYLOAD"
tx_record_attribute 9 "trans.data_value" UNSIGNED = 165
tx_end 9 31 30 ns
a 10000
tx_record_attribute 8 "trans.address" UNSIGNED = 0
tx_record_attribute 8 "trans.command" ENUMERATION = "tlm::TLM_WRITE_COMMAND"
tx_record_attribute 8 "trans.data" POINTER = 0
tx_record_attribute 8 "trans.data_length" UNSIGNED = 4
tx_record_attribute 8 "trans.response_status" ENUMERATION = "tlm::TLM_OK_RESPONSE"
tx_record_attribute 8 "trans.dmi" BOOLEAN = false
tx_record_attribute 8 "trans.byte_enable" POINTER = 0
tx_record_attribute 8 "trans.byte_enable_length" UNSIGNED = 0
tx_record_attribute 8 "trans.streaming_width" UNSIGNED = 4
tx_record_attribute 8 "trans.gp_option" ENUMERATION = "tlm::TLM_MIN_PAYLOAD"
tx_record_attribute 8 "trans.data_value" UNSIGNED = 165
tx_end 8 27 30 ns
a 10000
tx_record_attribute 7 "trans.address" UNSIGNED = 268509184
tx_record_attribute 7 "trans.command" ENUMERATION = "tlm::TLM_WRITE_COMMAND"
tx_record_attribute 7 "trans.data" POINTER = 0
tx_record_attribute 7 "trans.data_length" UNSIGNED = 4
tx_record_attribute 7 "trans.response_status" ENUMERATION = "tlm::TLM_OK_RESPONSE"
tx_record_attribute 7 "trans.dmi" BOOLEAN = false
tx_record_attribute 7 "trans.byte_enable" POINTER = 0
tx_record_attribute 7 "trans.byte_enable_length" UNSIGNED = 0
tx_record_attribute 7 "trans.streaming_width" UNSIGNED = 4
tx_record_attribute 7 "trans.gp_option" ENUMERATION = "tlm::TLM_MIN_PAYLOAD"
tx_record_attribute 7 "trans.data_value" UNSIGNED = 165
tx_end 7 3 30 ns
a 10000
tx_begin 10 23 40 ns
a "tlm::TLM_WRITE_COMMAND"
tx_record_attribute 10 "trans.address" UNSIGNED = 268509184
tx_record_attribute 10 "trans.command" ENUMERATION = "tlm::TLM_WRITE_COMMAND"
tx_record_attribute 10 "trans.data" POINTER = 0
tx_record_attribute 10 "trans.data_length" UNSIGNED = 4
tx_record_attribute 10 "trans.response_status" ENUMERATION = "tlm::TLM_OK_RESPONSE"
tx_record_attribute 10 "trans.dmi" BOOLEAN = false
tx_record_attribute 10 "trans.byte_enable" POINTER = 0
tx_record_attribute 10 "trans.byte_enable_length" UNSIGNED = 0
tx_record_attribute 10 "trans.streaming_width" UNSIGNED = 4
tx_record_attribute 10 "trans.gp_option" ENUMERATION = "tlm::TLM_MIN_PAYLOAD"
tx_relation "PARENT/CHILD" 10 7
tx_end 10 23 40 ns
a "tlm::TLM_OK_RESPONSE"
scv_tr_stream (ID 33, name "i_simple_system.i_gpio.socket.bl_t_ann", kind "TRANSACTOR")
scv_tr_generator (ID 34, name "read", scv_tr_stream 33,
begin_attribute (ID 0, name "<anonymous>", type "ENUMERATION")
end_attribute (ID 1, name "<anonymous>", type "ENUMERATION")
)
scv_tr_generator (ID 35, name "write", scv_tr_stream 33,
begin_attribute (ID 0, name "<anonymous>", type "ENUMERATION")
end_attribute (ID 1, name "<anonymous>", type "ENUMERATION")
)
scv_tr_generator (ID 36, name "ignore", scv_tr_stream 33,
begin_attribute (ID 0, name "<anonymous>", type "ENUMERATION")
end_attribute (ID 1, name "<anonymous>", type "ENUMERATION")
)
tx_begin 11 35 40 ns
a "tlm::TLM_WRITE_COMMAND"
tx_record_attribute 11 "trans.address" UNSIGNED = 0
tx_record_attribute 11 "trans.command" ENUMERATION = "tlm::TLM_WRITE_COMMAND"
tx_record_attribute 11 "trans.data" POINTER = 0
tx_record_attribute 11 "trans.data_length" UNSIGNED = 4
tx_record_attribute 11 "trans.response_status" ENUMERATION = "tlm::TLM_OK_RESPONSE"
tx_record_attribute 11 "trans.dmi" BOOLEAN = false
tx_record_attribute 11 "trans.byte_enable" POINTER = 0
tx_record_attribute 11 "trans.byte_enable_length" UNSIGNED = 0
tx_record_attribute 11 "trans.streaming_width" UNSIGNED = 4
tx_record_attribute 11 "trans.gp_option" ENUMERATION = "tlm::TLM_MIN_PAYLOAD"
tx_relation "PARENT/CHILD" 11 9
tx_end 11 35 40 ns
a "tlm::TLM_OK_RESPONSE"
scv_tr_stream (ID 37, name "i_simple_system.i_router.intor_1.bl_t_ann", kind "TRANSACTOR")
scv_tr_generator (ID 38, name "read", scv_tr_stream 37,
begin_attribute (ID 0, name "<anonymous>", type "ENUMERATION")
end_attribute (ID 1, name "<anonymous>", type "ENUMERATION")
)
scv_tr_generator (ID 39, name "write", scv_tr_stream 37,
begin_attribute (ID 0, name "<anonymous>", type "ENUMERATION")
end_attribute (ID 1, name "<anonymous>", type "ENUMERATION")
)
scv_tr_generator (ID 40, name "ignore", scv_tr_stream 37,
begin_attribute (ID 0, name "<anonymous>", type "ENUMERATION")
end_attribute (ID 1, name "<anonymous>", type "ENUMERATION")
)
tx_begin 12 39 40 ns
a "tlm::TLM_WRITE_COMMAND"
tx_record_attribute 12 "trans.address" UNSIGNED = 0
tx_record_attribute 12 "trans.command" ENUMERATION = "tlm::TLM_WRITE_COMMAND"
tx_record_attribute 12 "trans.data" POINTER = 0
tx_record_attribute 12 "trans.data_length" UNSIGNED = 4
tx_record_attribute 12 "trans.response_status" ENUMERATION = "tlm::TLM_OK_RESPONSE"
tx_record_attribute 12 "trans.dmi" BOOLEAN = false
tx_record_attribute 12 "trans.byte_enable" POINTER = 0
tx_record_attribute 12 "trans.byte_enable_length" UNSIGNED = 0
tx_record_attribute 12 "trans.streaming_width" UNSIGNED = 4
tx_record_attribute 12 "trans.gp_option" ENUMERATION = "tlm::TLM_MIN_PAYLOAD"
tx_relation "PARENT/CHILD" 12 8
tx_end 12 39 40 ns
a "tlm::TLM_OK_RESPONSE"