SystemC/SystemC-Components-Test
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Added clang format

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This commit is contained in:
Eyck Jentzsch
2017-09-25 22:00:46 +02:00
parent 363d03ebad
commit a29bfe6bae
24 changed files with 468 additions and 842 deletions
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131
examples/transaction_recording/scv_tr_recording_example.cpp
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@@ -22,7 +22,7 @@
const unsigned ram_size = 256;
class rw_task_if: virtual public sc_interface {
class rw_task_if : virtual public sc_interface {
public:
typedef sc_uint<8> addr_t;
typedef sc_uint<8> data_t;
@@ -31,38 +31,42 @@ public:
data_t data;
};
virtual data_t read(const addr_t*) = 0;
virtual void write(const write_t*) = 0;
virtual data_t read(const addr_t *) = 0;
virtual void write(const write_t *) = 0;
};
SCV_EXTENSIONS(rw_task_if::write_t){
SCV_EXTENSIONS(rw_task_if::write_t) {
public:
scv_extensions<rw_task_if::addr_t> addr;
scv_extensions<rw_task_if::data_t> data;
SCV_EXTENSIONS_CTOR(rw_task_if::write_t) {
SCV_FIELD(addr);
SCV_FIELD(data);
}
scv_extensions<rw_task_if::addr_t> addr;
scv_extensions<rw_task_if::data_t> data;
SCV_EXTENSIONS_CTOR(rw_task_if::write_t) {
SCV_FIELD(addr);
SCV_FIELD(data);
}
};
class pipelined_bus_ports: public sc_module {
class pipelined_bus_ports : public sc_module {
public:
sc_in<bool> clk;
sc_inout<bool> rw;
sc_inout<bool> addr_req;
sc_inout<bool> addr_ack;
sc_inout<sc_uint<8> > bus_addr;
sc_inout<sc_uint<8>> bus_addr;
sc_inout<bool> data_rdy;
sc_inout<sc_uint<8> > bus_data;
sc_inout<sc_uint<8>> bus_data;
SC_CTOR(pipelined_bus_ports) :
clk("clk"), rw("rw"), addr_req("addr_req"), addr_ack("addr_ack"), bus_addr("bus_addr"), data_rdy("data_rdy"), bus_data(
"bus_data") {
}
virtual void trace( sc_trace_file* tf ) const;
SC_CTOR(pipelined_bus_ports)
: clk("clk")
, rw("rw")
, addr_req("addr_req")
, addr_ack("addr_ack")
, bus_addr("bus_addr")
, data_rdy("data_rdy")
, bus_data("bus_data") {}
virtual void trace(sc_trace_file *tf) const;
};
void pipelined_bus_ports::trace( sc_trace_file* tf ) const {
void pipelined_bus_ports::trace(sc_trace_file *tf) const {
sc_trace(tf, clk, clk.name());
sc_trace(tf, rw, rw.name());
sc_trace(tf, addr_req, addr_req.name());
@@ -72,46 +76,45 @@ void pipelined_bus_ports::trace( sc_trace_file* tf ) const {
sc_trace(tf, bus_data, bus_data.name());
}
class rw_pipelined_transactor: public rw_task_if, public pipelined_bus_ports {
class rw_pipelined_transactor : public rw_task_if, public pipelined_bus_ports {
fifo_mutex addr_phase;fifo_mutex data_phase;
fifo_mutex addr_phase;
fifo_mutex data_phase;
scv_tr_stream pipelined_stream;
scv_tr_stream addr_stream;
scv_tr_stream data_stream;
scv_tr_generator<sc_uint<8>, sc_uint<8> > read_gen;
scv_tr_generator<sc_uint<8>, sc_uint<8> > write_gen;
scv_tr_generator<sc_uint<8> > addr_gen;
scv_tr_generator<_scv_tr_generator_default_data, sc_uint<8> > rdata_gen;
scv_tr_generator<sc_uint<8> > wdata_gen;
scv_tr_generator<sc_uint<8>, sc_uint<8>> read_gen;
scv_tr_generator<sc_uint<8>, sc_uint<8>> write_gen;
scv_tr_generator<sc_uint<8>> addr_gen;
scv_tr_generator<_scv_tr_generator_default_data, sc_uint<8>> rdata_gen;
scv_tr_generator<sc_uint<8>> wdata_gen;
public:
rw_pipelined_transactor(sc_module_name nm)
: pipelined_bus_ports(nm)
, addr_phase("addr_phase")
, data_phase("data_phase")
, pipelined_stream((std::string(name()) +".pipelined_stream").c_str(), "transactor")
, addr_stream( (std::string(name()) +".addr_stream").c_str(), "transactor")
, data_stream((std::string(name()) +".data_stream").c_str(), "transactor")
, read_gen("read", pipelined_stream, "addr", "data")
, write_gen("write", pipelined_stream, "addr", "data")
, addr_gen("addr", addr_stream, "addr")
, rdata_gen("rdata", data_stream, NULL, "data")
, wdata_gen("wdata", data_stream, "data")
{
}
virtual data_t read(const addr_t* p_addr);
virtual void write(const write_t * req);
: pipelined_bus_ports(nm)
, addr_phase("addr_phase")
, data_phase("data_phase")
, pipelined_stream((std::string(name()) + ".pipelined_stream").c_str(), "transactor")
, addr_stream((std::string(name()) + ".addr_stream").c_str(), "transactor")
, data_stream((std::string(name()) + ".data_stream").c_str(), "transactor")
, read_gen("read", pipelined_stream, "addr", "data")
, write_gen("write", pipelined_stream, "addr", "data")
, addr_gen("addr", addr_stream, "addr")
, rdata_gen("rdata", data_stream, NULL, "data")
, wdata_gen("wdata", data_stream, "data") {}
virtual data_t read(const addr_t *p_addr);
virtual void write(const write_t *req);
};
rw_task_if::data_t rw_pipelined_transactor::read(const addr_t* addr) {
rw_task_if::data_t rw_pipelined_transactor::read(const addr_t *addr) {
addr_phase.lock();
scv_tr_handle h = read_gen.begin_transaction(*addr);
h.record_attribute("data_size", sizeof(data_t));
scv_tr_handle h1 = addr_gen.begin_transaction(*addr, "addr_phase", h);
wait(clk->posedge_event());
bus_addr = *addr;
rw=false;
rw = false;
addr_req = 1;
wait(addr_ack->posedge_event());
wait(clk->negedge_event());
@@ -132,14 +135,14 @@ rw_task_if::data_t rw_pipelined_transactor::read(const addr_t* addr) {
return data;
}
void rw_pipelined_transactor::write(const write_t * req) {
void rw_pipelined_transactor::write(const write_t *req) {
addr_phase.lock();
scv_tr_handle h = write_gen.begin_transaction(req->addr);
h.record_attribute("data_size", sizeof(data_t));
scv_tr_handle h1 = addr_gen.begin_transaction(req->addr, "addr_phase", h);
wait(clk->posedge_event());
bus_addr = req->addr;
rw=true;
rw = true;
addr_req = 1;
wait(addr_ack->posedge_event());
wait(clk->negedge_event());
@@ -150,7 +153,7 @@ void rw_pipelined_transactor::write(const write_t * req) {
data_phase.lock();
scv_tr_handle h2 = wdata_gen.begin_transaction(req->data, "data_phase", h);
bus_data=req->data;
bus_data = req->data;
wait(data_rdy->posedge_event());
wait(data_rdy->negedge_event());
wdata_gen.end_transaction(h2);
@@ -158,11 +161,11 @@ void rw_pipelined_transactor::write(const write_t * req) {
data_phase.unlock();
}
class test: public sc_module {
class test : public sc_module {
public:
sc_port<rw_task_if> transactor;
SC_HAS_PROCESS(test);
test( ::sc_core::sc_module_name ){
test(::sc_core::sc_module_name) {
SC_THREAD(main1);
SC_THREAD(main2);
}
@@ -170,16 +173,16 @@ public:
void main2();
};
class write_constraint: virtual public scv_constraint_base {
class write_constraint : virtual public scv_constraint_base {
public:
scv_smart_ptr<rw_task_if::write_t> write;SCV_CONSTRAINT_CTOR(write_constraint) {
scv_smart_ptr<rw_task_if::write_t> write;
SCV_CONSTRAINT_CTOR(write_constraint) {
SCV_CONSTRAINT(write->addr() <= ram_size);
SCV_CONSTRAINT(write->addr() != write->data());
}
};
inline void process(scv_smart_ptr<int> data) {
}
inline void process(scv_smart_ptr<int> data) {}
inline void test::main1() {
// simple sequential tests
@@ -250,15 +253,15 @@ inline void test::main2() {
process(data);
}
}
class design: public pipelined_bus_ports {
std::list<sc_uint<8> > outstandingAddresses;
class design : public pipelined_bus_ports {
std::list<sc_uint<8>> outstandingAddresses;
std::list<bool> outstandingType;
sc_uint<8> memory[ram_size];
public:
SC_HAS_PROCESS(design);
design(sc_module_name nm) :
pipelined_bus_ports(nm) {
design(sc_module_name nm)
: pipelined_bus_ports(nm) {
for (unsigned i = 0; i < ram_size; ++i) {
memory[i] = i;
}
@@ -304,16 +307,15 @@ inline void design::data_phase() {
}
if (outstandingType.front() == false) {
cout << "reading memory address " << outstandingAddresses.front() << " with value "
<< memory[outstandingAddresses.front().to_ulong()] << endl;
<< memory[outstandingAddresses.front().to_ulong()] << endl;
bus_data = memory[outstandingAddresses.front().to_ulong()];
data_rdy = 1;
wait(clk->posedge_event());
data_rdy = 0;
} else {
cout << "writing memory address " << outstandingAddresses.front() << " with value "
<< bus_data << endl;
memory[outstandingAddresses.front().to_ulong()]=bus_data;
cout << "writing memory address " << outstandingAddresses.front() << " with value " << bus_data << endl;
memory[outstandingAddresses.front().to_ulong()] = bus_data;
data_rdy = 1;
wait(clk->posedge_event());
data_rdy = 0;
@@ -332,19 +334,19 @@ int sc_main(int argc, char *argv[]) {
const char* fileName = "my_db.txlog";
#else
scv_tr_sqlite_init();
const char* fileName = "my_db";
const char *fileName = "my_db";
#endif
scv_tr_db db(fileName);
scv_tr_db::set_default_db(&db);
sc_trace_file* tf = sc_create_vcd_trace_file("my_db");
sc_trace_file *tf = sc_create_vcd_trace_file("my_db");
// create signals
sc_clock clk("clk", 20.0, SC_NS, 0.5, 0.0, SC_NS, true);
sc_signal<bool> rw;
sc_signal<bool> addr_req;
sc_signal<bool> addr_ack;
sc_signal<sc_uint<8> > bus_addr;
sc_signal<sc_uint<8>> bus_addr;
sc_signal<bool> data_rdy;
sc_signal<sc_uint<8> > bus_data;
sc_signal<sc_uint<8>> bus_data;
// create modules/channels
test t("t");
@@ -380,4 +382,3 @@ int sc_main(int argc, char *argv[]) {
sc_close_vcd_trace_file(tf);
return 0;
}