extends cxs_tlm test to support tracing
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2025-09-22 11:54:46 +02:00
parent 572b4a2b27
commit 73e4d5d644
9 changed files with 71 additions and 45 deletions

View File

@@ -5,7 +5,6 @@
#undef CHECK
#include <catch2/catch_all.hpp>
#include <deque>
#include <unordered_map>
using namespace sc_core;
namespace cxs {
@@ -17,6 +16,7 @@ template <unsigned WIDTH, typename STATE> unsigned run_scenario(STATE& state, un
auto& dut = factory::get<testbench<WIDTH>>();
if(burst_factor)
dut.tx.burst_len.set_value(burst_factor);
dut.rx.max_credit.set_value(5);
dut.rst.write(true);
sc_start(state.reset_cycles * dut.clk.period());
dut.rst.write(false);

View File

@@ -2,12 +2,12 @@
#define _TESTBENCH_H_
#include <cxs/cxs_tlm.h>
#include <cxs/scv/tlm_recording.h>
#include <scc/cci_util.h>
#include <scc/configurer.h>
#include <scc/observer.h>
#include <scc/sc_variable.h>
#include <scc/tracer.h>
#include <string>
#include <systemc>
#include <tlm/nw/initiator_mixin.h>
#include <tlm/nw/target_mixin.h>
@@ -27,7 +27,9 @@ template <unsigned PHIT_WIDTH> struct testbench : public sc_core::sc_module {
sc_core::sc_signal<bool> rst{"rst"};
tlm::nw::initiator_mixin<cxs_pkt_initiator_socket<>, cxs_packet_types> isck{"isck"};
cxs_transmitter<PHIT_WIDTH> tx{"tx"};
tlm::nw::scv::tlm_recorder_module<CXS_CMD, PHIT_WIDTH, cxs_flit_types> tx_rec{"tx_rec"};
cxs_channel<PHIT_WIDTH> cxs_chan{"cxs_chan"};
tlm::nw::scv::tlm_recorder_module<CXS_CMD, PHIT_WIDTH, cxs_flit_types> rx_rec{"rx_rec"};
cxs_receiver<PHIT_WIDTH> rx{"rx"};
tlm::nw::target_mixin<cxs_pkt_target_socket<>, false, cxs_packet_types> tsck{"tsck"};
@@ -43,12 +45,25 @@ template <unsigned PHIT_WIDTH> struct testbench : public sc_core::sc_module {
isck(tx.tsck);
tx.clk_i(clk);
tx.rst_i(rst);
cxs_chan.tx_clk_i(clk);
cxs_chan.rx_clk_i(clk);
#if 0
tx.isck(cxs_chan.tsck);
cxs_chan.isck(rx.tsck);
#else
tx.isck(tx_rec.ts);
tx_rec.is(cxs_chan.tsck);
cxs_chan.isck(rx_rec.ts);
rx_rec.is(rx.tsck);
#endif
rx.clk_i(clk);
rx.rst_i(rst);
rx.isck(tsck);
tx.clock_period.set_value(1_ns);
cxs_chan.tx_clock_period.set_value(1_ns);
cxs_chan.channel_delay.set_value(100_ns);
cxs_chan.rx_clock_period.set_value(1_ns);
rx.clock_period.set_value(1_ns);
rx.max_credit.set_value(15);
}