SystemC/SystemC-Components-Test
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update SCC to latest

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This commit is contained in:
Eyck Jentzsch
2021-06-01 18:08:32 +02:00
parent 0a86bd9493
commit 6cc42f08b3
18 changed files with 256 additions and 516 deletions
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20
examples/simple_system/gpio.cpp
View File

@@ -63,7 +63,7 @@ gpio::gpio(sc_module_name nm)
SC_METHOD(reset_cb);
sensitive << rst_i;
dont_initialize();
auto pins_i_cb =[this](unsigned int tag, tlm::tlm_signal_gp<>& gp,
auto pins_i_cb =[this](unsigned int tag, tlm::scc::tlm_signal_gp<>& gp,
tlm::tlm_phase& phase, sc_time& delay)->tlm::tlm_sync_enum{
this->pin_input(tag, gp, delay);
return tlm::TLM_COMPLETED;
@@ -73,7 +73,7 @@ gpio::gpio(sc_module_name nm)
s.register_nb_transport(pins_i_cb, i);
++i;
}
auto iof0_i_cb =[this](unsigned int tag, tlm::tlm_signal_gp<>& gp,
auto iof0_i_cb =[this](unsigned int tag, tlm::scc::tlm_signal_gp<>& gp,
tlm::tlm_phase& phase, sc_time& delay)->tlm::tlm_sync_enum{
last_iof0[tag]=gp.get_value();
this->iof_input(tag, 0, gp, delay);
@@ -84,7 +84,7 @@ gpio::gpio(sc_module_name nm)
s.register_nb_transport(iof0_i_cb, i);
++i;
}
auto iof1_i_cb =[this](unsigned int tag, tlm::tlm_signal_gp<>& gp,
auto iof1_i_cb =[this](unsigned int tag, tlm::scc::tlm_signal_gp<>& gp,
tlm::tlm_phase& phase, sc_time& delay)->tlm::tlm_sync_enum{
last_iof1[tag]=gp.get_value();
this->iof_input(tag, 1, gp, delay);
@@ -125,7 +125,7 @@ void gpio::clock_cb() {
this->clk = clk_i.read();
}
tlm::tlm_phase gpio::write_output(tlm::tlm_signal_gp<bool>& gp, size_t i, bool val) {
tlm::tlm_phase gpio::write_output(tlm::scc::tlm_signal_gp<bool>& gp, size_t i, bool val) {
sc_time delay{SC_ZERO_TIME};
tlm::tlm_phase phase{ tlm::BEGIN_REQ };
gp.set_command(tlm::TLM_WRITE_COMMAND);
@@ -137,7 +137,7 @@ tlm::tlm_phase gpio::write_output(tlm::tlm_signal_gp<bool>& gp, size_t i, bool v
void gpio::update_pins(uint32_t changed_bits) {
sc_inout_rv<32>::data_type out_val;
tlm::tlm_signal_gp<bool> gp;
tlm::scc::tlm_signal_gp<bool> gp;
bool val;
for(size_t i=0, mask = 1; i<32; ++i, mask<<=1){
if(changed_bits&mask){
@@ -159,7 +159,7 @@ void gpio::update_pins(uint32_t changed_bits) {
}
}
void gpio::pin_input(unsigned int tag, tlm::tlm_signal_gp<bool>& gp, sc_time& delay) {
void gpio::pin_input(unsigned int tag, tlm::scc::tlm_signal_gp<bool>& gp, sc_time& delay) {
if(delay>SC_ZERO_TIME){
wait(delay);
delay=SC_ZERO_TIME;
@@ -178,11 +178,11 @@ void gpio::pin_input(unsigned int tag, tlm::tlm_signal_gp<bool>& gp, sc_time& de
}
}
void gpio::forward_pin_input(unsigned int tag, tlm::tlm_signal_gp<bool>& gp) {
void gpio::forward_pin_input(unsigned int tag, tlm::scc::tlm_signal_gp<bool>& gp) {
const auto mask = 1U<<tag;
if(regs->iof_en&mask){
auto& socket = regs->iof_sel&mask?iof1_o[tag]:iof0_o[tag];
tlm::tlm_signal_gp<> new_gp;
tlm::scc::tlm_signal_gp<> new_gp;
for(size_t i=0; i<socket.size(); ++i){
sc_time delay{SC_ZERO_TIME};
tlm::tlm_phase phase{tlm::BEGIN_REQ};
@@ -195,7 +195,7 @@ void gpio::forward_pin_input(unsigned int tag, tlm::tlm_signal_gp<bool>& gp) {
}
}
void gpio::iof_input(unsigned int tag, unsigned iof_idx, tlm::tlm_signal_gp<>& gp, sc_time& delay) {
void gpio::iof_input(unsigned int tag, unsigned iof_idx, tlm::scc::tlm_signal_gp<>& gp, sc_time& delay) {
if(delay>SC_ZERO_TIME){
wait(delay);
delay=SC_ZERO_TIME;
@@ -208,7 +208,7 @@ void gpio::iof_input(unsigned int tag, unsigned iof_idx, tlm::tlm_signal_gp<>& g
for(size_t i=0; i<socket.size(); ++i){
sc_time delay{SC_ZERO_TIME};
tlm::tlm_phase phase{tlm::BEGIN_REQ};
tlm::tlm_signal_gp<> new_gp;
tlm::scc::tlm_signal_gp<> new_gp;
new_gp.set_command(tlm::TLM_WRITE_COMMAND);
auto val = gp.get_value();
new_gp.set_value(val);

26
examples/simple_system/gpio.h
View File

@@ -38,9 +38,9 @@
#define _GPIO_H_
#include "scc/tlm_target.h"
#include "scc/signal_target_mixin.h"
#include "scc/signal_initiator_mixin.h"
#include <tlm/tlm_signal.h>
#include "tlm/scc/signal_target_mixin.h"
#include "tlm/scc/signal_initiator_mixin.h"
#include <tlm/scc/tlm_signal.h>
namespace sysc {
@@ -54,13 +54,13 @@ public:
sc_core::sc_in<bool> rst_i;
// sc_core::sc_inout_rv<32> pins_io;
sc_core::sc_vector<scc::tlm_signal_bool_out> pins_o;
sc_core::sc_vector<scc::tlm_signal_bool_in> pins_i;
sc_core::sc_vector<tlm::scc::tlm_signal_bool_out> pins_o;
sc_core::sc_vector<tlm::scc::tlm_signal_bool_in> pins_i;
sc_core::sc_vector<scc::tlm_signal_bool_opt_out> iof0_o;
sc_core::sc_vector<scc::tlm_signal_bool_opt_out> iof1_o;
sc_core::sc_vector<scc::tlm_signal_bool_opt_in> iof0_i;
sc_core::sc_vector<scc::tlm_signal_bool_opt_in> iof1_i;
sc_core::sc_vector<tlm::scc::tlm_signal_bool_opt_out> iof0_o;
sc_core::sc_vector<tlm::scc::tlm_signal_bool_opt_out> iof1_o;
sc_core::sc_vector<tlm::scc::tlm_signal_bool_opt_in> iof0_i;
sc_core::sc_vector<tlm::scc::tlm_signal_bool_opt_in> iof1_i;
gpio(sc_core::sc_module_name nm);
virtual ~gpio() override; // need to keep it in source file because of fwd declaration of gpio_regs
@@ -69,16 +69,16 @@ protected:
void clock_cb();
void reset_cb();
void update_pins(uint32_t changed_bits);
void pin_input(unsigned int tag, tlm::tlm_signal_gp<>& gp, sc_core::sc_time& delay);
void forward_pin_input(unsigned int tag, tlm::tlm_signal_gp<>& gp);
void iof_input(unsigned int tag, unsigned iof_idx, tlm::tlm_signal_gp<>& gp, sc_core::sc_time& delay);
void pin_input(unsigned int tag, tlm::scc::tlm_signal_gp<>& gp, sc_core::sc_time& delay);
void forward_pin_input(unsigned int tag, tlm::scc::tlm_signal_gp<>& gp);
void iof_input(unsigned int tag, unsigned iof_idx, tlm::scc::tlm_signal_gp<>& gp, sc_core::sc_time& delay);
sc_core::sc_time clk;
std::array<bool, 32> last_iof0, last_iof1;
std::unique_ptr<gpio_regs> regs;
std::shared_ptr<sysc::WsHandler> handler;
private:
tlm::tlm_phase write_output(tlm::tlm_signal_gp<>& gp, size_t i, bool val);
tlm::tlm_phase write_output(tlm::scc::tlm_signal_gp<>& gp, size_t i, bool val);
};
} /* namespace sysc */

8
examples/simple_system/plic.cpp
View File

@@ -119,7 +119,7 @@ void plic::global_int_port_cb() {
if (enable && global_interrupts_i[i].read() == 1) {
regs->r_pending = regs->r_pending | (0x1 << i);
SCDEBUG("plic") << "pending interrupt identified: " << i;
SCCDEBUG("plic") << "pending interrupt identified: " << i;
}
}
@@ -147,7 +147,7 @@ void plic::handle_pending_int() {
claim_prio = prio;
claim_int = i;
raise_int = 1;
SCDEBUG("plic") << "pending interrupt activated: " << i;
SCCDEBUG("plic") << "pending interrupt activated: " << i;
}
}
}
@@ -158,14 +158,14 @@ void plic::handle_pending_int() {
// todo: evluate clock period
} else {
regs->r_claim_complete = 0;
SCDEBUG("plic") << "no further pending interrupt.";
SCCDEBUG("plic") << "no further pending interrupt.";
}
}
void plic::reset_pending_int(uint32_t irq) {
// todo: evaluate enable register (see spec)
// todo: make sure that pending is set, otherwise don't reset irq ... read spec.
SCDEBUG("plic") << "reset pending interrupt: " << irq;
SCCDEBUG("plic") << "reset pending interrupt: " << irq;
// reset related pending bit
regs->r_pending &= ~(0x1 << irq);
core_interrupt_o.write(0);

5
examples/simple_system/sc_main.cpp
View File

@@ -22,7 +22,6 @@
#include "simple_system.h"
#include <scc/report.h>
#include <scc/scv_tr_db.h>
#include <scc/tracer.h>
#include <boost/program_options.hpp>
@@ -67,7 +66,7 @@ int sc_main(int argc, char *argv[]) {
///////////////////////////////////////////////////////////////////////////
// configure logging
///////////////////////////////////////////////////////////////////////////
scc::init_logging(vm.count("debug")?logging::DEBUG:logging::INFO);
scc::init_logging(vm.count("debug")?scc::log::DEBUG:scc::log::INFO);
///////////////////////////////////////////////////////////////////////////
// set up tracing & transaction recording
///////////////////////////////////////////////////////////////////////////
@@ -86,7 +85,7 @@ int sc_main(int argc, char *argv[]) {
// todo: provide end-of-simulation macros
if (!sc_core::sc_end_of_simulation_invoked()) {
SCERR() << "simulation timed out";
SCCERR() << "simulation timed out";
sc_core::sc_stop();
}
return SUCCESS;

2
examples/simple_system/simple_system.h
View File

@@ -49,7 +49,7 @@ public:
sc_core::sc_signal<bool> s_rst;
sc_core::sc_vector<sc_core::sc_signal<bool>> s_global_interrupts;
sc_core::sc_signal<bool, sc_core::SC_MANY_WRITERS> s_core_interrupt;
sc_core::sc_vector<tlm::tlm_signal<>> s_gpio;
sc_core::sc_vector<tlm::scc::tlm_signal<>> s_gpio;
simple_system(sc_core::sc_module_name nm);

10
examples/simple_system/test_initiator.cpp
View File

@@ -215,7 +215,7 @@ void test_initiator::write_bus(std::uint32_t adr, std::uint32_t dat) {
data[1] = 0xff & dat >> 8;
data[0] = 0xff & dat;
SCDEBUG("test_initiator") << "write_bus(0x" << std::hex << adr << ") : " << dat;
SCCDEBUG("test_initiator") << "write_bus(0x" << std::hex << adr << ") : " << dat;
gp.set_command(tlm::TLM_WRITE_COMMAND);
gp.set_address(adr);
@@ -252,21 +252,21 @@ std::uint32_t test_initiator::read_bus(std::uint32_t adr) {
// todo: use reinterpret_cast instead
std::uint32_t rdat = data[3] << 24 | data[2] << 16 | data[1] << 8 | data[0];
SCDEBUG("test_initiator") << "read_bus(0x" << std::hex << adr << ") -> " << rdat;
SCCDEBUG("test_initiator") << "read_bus(0x" << std::hex << adr << ") -> " << rdat;
return rdat;
}
void test_initiator::reg_check(std::uint32_t adr, std::uint32_t exp) {
uint32_t dat = read_bus(adr);
if (dat != exp) {
SCERR("test_initiator") << "register check failed for address 0x" << std::hex << adr << ": " << dat << " != " << exp;
SCCERR("test_initiator") << "register check failed for address 0x" << std::hex << adr << ": " << dat << " != " << exp;
} else {
SCDEBUG("test_initiator") << "register check passed for address 0x" << std::hex << adr << ": " << dat;
SCCDEBUG("test_initiator") << "register check passed for address 0x" << std::hex << adr << ": " << dat;
}
}
void test_initiator::core_irq_handler() {
SCDEBUG("test_initiator") << "core_interrupt_i edge detected -> " << core_interrupt_i.read();
SCCDEBUG("test_initiator") << "core_interrupt_i edge detected -> " << core_interrupt_i.read();
}
} /* namespace sysc */