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Completely changed register instantiation

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This commit is contained in:
Eyck Jentzsch 2017-09-19 18:06:11 +02:00
parent 010c5590d8
commit 68a3a36d5d
9 changed files with 203 additions and 113 deletions
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15
examples/simple_system/gen/e300_plat_t.h
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@ -1,18 +1,3 @@
/*******************************************************************************
* Copyright 2017 eyck@minres.com
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may not
* use this file except in compliance with the License. You may obtain a copy
* of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations under
* the License.
******************************************************************************/
#ifndef _E300_PLAT_MAP_H_
#define _E300_PLAT_MAP_H_
// need double braces, see https://stackoverflow.com/questions/6893700/how-to-construct-stdarray-object-with-initializer-list#6894191

56
examples/simple_system/gen/gpio_regs.h
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@ -1,25 +1,44 @@
/*******************************************************************************
* Copyright 2017 eyck@minres.com
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may not
* use this file except in compliance with the License. You may obtain a copy
* of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations under
* the License.
******************************************************************************/
////////////////////////////////////////////////////////////////////////////////
// Copyright (C) 2017, MINRES Technologies GmbH
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are met:
//
// 1. Redistributions of source code must retain the above copyright notice,
// this list of conditions and the following disclaimer.
//
// 2. Redistributions in binary form must reproduce the above copyright notice,
// this list of conditions and the following disclaimer in the documentation
// and/or other materials provided with the distribution.
//
// 3. Neither the name of the copyright holder nor the names of its contributors
// may be used to endorse or promote products derived from this software
// without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//
// Created on: Tue Sep 19 18:02:10 CEST 2017
// * gpio_regs.h Author: <RDL Generator>
//
////////////////////////////////////////////////////////////////////////////////
#ifndef _GPIO_REGS_H_
#define _GPIO_REGS_H_
#include <sysc/utilities.h>
#include <util/bit_field.h>
#include <sysc/register.h>
#include <sysc/utilities.h>
#include <sysc/tlm_target.h>
namespace sysc {
@ -28,7 +47,7 @@ class gpio_regs :
public sc_core::sc_module,
public sysc::resetable
{
public:
protected:
// storage declarations
uint32_t r_value;
@ -83,14 +102,13 @@ public:
sysc::sc_register<uint32_t> iof_sel;
sysc::sc_register<uint32_t> out_xor;
public:
gpio_regs(sc_core::sc_module_name nm);
template<unsigned BUSWIDTH=32>
void registerResources(sysc::tlm_target<BUSWIDTH>& target);
};
}
//////////////////////////////////////////////////////////////////////////////
// member functions
//////////////////////////////////////////////////////////////////////////////

99
examples/simple_system/gen/spi_regs.h
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@ -1,33 +1,50 @@
/*******************************************************************************
* Copyright 2017 eyck@minres.com
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may not
* use this file except in compliance with the License. You may obtain a copy
* of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations under
* the License.
******************************************************************************/
////////////////////////////////////////////////////////////////////////////////
// Copyright (C) 2017, MINRES Technologies GmbH
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are met:
//
// 1. Redistributions of source code must retain the above copyright notice,
// this list of conditions and the following disclaimer.
//
// 2. Redistributions in binary form must reproduce the above copyright notice,
// this list of conditions and the following disclaimer in the documentation
// and/or other materials provided with the distribution.
//
// 3. Neither the name of the copyright holder nor the names of its contributors
// may be used to endorse or promote products derived from this software
// without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//
// Created on: Tue Sep 19 18:02:09 CEST 2017
// * spi_regs.h Author: <RDL Generator>
//
////////////////////////////////////////////////////////////////////////////////
#ifndef _SPI_REGS_H_
#define _SPI_REGS_H_
#include <sysc/utilities.h>
#include <util/bit_field.h>
#include <sysc/register.h>
#include <sysc/utilities.h>
#include <sysc/tlm_target.h>
namespace sysc {
template<unsigned BUSWIDTH=32>
class spi_regs :
public sc_core::sc_module,
public sysc::tlm_target<BUSWIDTH>,
public sysc::resetable
{
protected:
@ -127,18 +144,19 @@ protected:
sysc::sc_register<typename ie_t::StorageType> ie;
sysc::sc_register<typename ip_t::StorageType> ip;
public:
spi_regs(sc_core::sc_module_name nm);
protected:
sc_core::sc_time clk;
template<unsigned BUSWIDTH=32>
void registerResources(sysc::tlm_target<BUSWIDTH>& target);
};
}
//////////////////////////////////////////////////////////////////////////////
// member functions
//////////////////////////////////////////////////////////////////////////////
template<unsigned BUSWIDTH>
spi_regs<BUSWIDTH>::spi_regs(sc_core::sc_module_name nm)
inline sysc::spi_regs::spi_regs(sc_core::sc_module_name nm)
: sc_core::sc_module(nm)
, sysc::tlm_target<BUSWIDTH>(clk)
, NAMED(sckdiv, r_sckdiv, 0, *this)
, NAMED(sckmode, r_sckmode, 0, *this)
, NAMED(csid, r_csid, 0, *this)
@ -156,23 +174,26 @@ spi_regs<BUSWIDTH>::spi_regs(sc_core::sc_module_name nm)
, NAMED(ie, r_ie, 0, *this)
, NAMED(ip, r_ip, 0, *this)
{
this->socket_map.addEntry(&sckdiv, 0x0UL, 0x4UL);
this->socket_map.addEntry(&sckmode, 0x4UL, 0x4UL);
this->socket_map.addEntry(&csid, 0x10UL, 0x4UL);
this->socket_map.addEntry(&csdef, 0x14UL, 0x4UL);
this->socket_map.addEntry(&csmode, 0x18UL, 0x4UL);
this->socket_map.addEntry(&delay0, 0x28UL, 0x4UL);
this->socket_map.addEntry(&delay1, 0x2cUL, 0x4UL);
this->socket_map.addEntry(&fmt, 0x40UL, 0x4UL);
this->socket_map.addEntry(&txdata, 0x48UL, 0x4UL);
this->socket_map.addEntry(&rxdata, 0x4cUL, 0x4UL);
this->socket_map.addEntry(&txmark, 0x50UL, 0x4UL);
this->socket_map.addEntry(&rxmark, 0x54UL, 0x4UL);
this->socket_map.addEntry(&fctrl, 0x60UL, 0x4UL);
this->socket_map.addEntry(&ffmt, 0x64UL, 0x4UL);
this->socket_map.addEntry(&ie, 0x70UL, 0x4UL);
this->socket_map.addEntry(&ip, 0x74UL, 0x4UL);
}
template<unsigned BUSWIDTH>
inline void sysc::spi_regs::registerResources(sysc::tlm_target<BUSWIDTH>& target) {
target.addResource(sckdiv, 0x0UL, 0x4UL);
target.addResource(sckmode, 0x4UL, 0x4UL);
target.addResource(csid, 0x10UL, 0x4UL);
target.addResource(csdef, 0x14UL, 0x4UL);
target.addResource(csmode, 0x18UL, 0x4UL);
target.addResource(delay0, 0x28UL, 0x4UL);
target.addResource(delay1, 0x2cUL, 0x4UL);
target.addResource(fmt, 0x40UL, 0x4UL);
target.addResource(txdata, 0x48UL, 0x4UL);
target.addResource(rxdata, 0x4cUL, 0x4UL);
target.addResource(txmark, 0x50UL, 0x4UL);
target.addResource(rxmark, 0x54UL, 0x4UL);
target.addResource(fctrl, 0x60UL, 0x4UL);
target.addResource(ffmt, 0x64UL, 0x4UL);
target.addResource(ie, 0x70UL, 0x4UL);
target.addResource(ip, 0x74UL, 0x4UL);
}
#endif // _SPI_REGS_H_

81
examples/simple_system/gen/uart_regs.h
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@ -1,33 +1,50 @@
/*******************************************************************************
* Copyright 2017 eyck@minres.com
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may not
* use this file except in compliance with the License. You may obtain a copy
* of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations under
* the License.
******************************************************************************/
////////////////////////////////////////////////////////////////////////////////
// Copyright (C) 2017, MINRES Technologies GmbH
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are met:
//
// 1. Redistributions of source code must retain the above copyright notice,
// this list of conditions and the following disclaimer.
//
// 2. Redistributions in binary form must reproduce the above copyright notice,
// this list of conditions and the following disclaimer in the documentation
// and/or other materials provided with the distribution.
//
// 3. Neither the name of the copyright holder nor the names of its contributors
// may be used to endorse or promote products derived from this software
// without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//
// Created on: Tue Sep 19 18:02:09 CEST 2017
// * uart_regs.h Author: <RDL Generator>
//
////////////////////////////////////////////////////////////////////////////////
#ifndef _UART_REGS_H_
#define _UART_REGS_H_
#include <sysc/utilities.h>
#include <util/bit_field.h>
#include <sysc/register.h>
#include <sysc/utilities.h>
#include <sysc/tlm_target.h>
namespace sysc {
template<unsigned BUSWIDTH=32>
class uart_regs :
public sc_core::sc_module,
public sysc::tlm_target<BUSWIDTH>,
public sysc::resetable
{
protected:
@ -78,18 +95,19 @@ protected:
sysc::sc_register<typename ip_t::StorageType> ip;
sysc::sc_register<typename div_t::StorageType> div;
public:
uart_regs(sc_core::sc_module_name nm);
protected:
sc_core::sc_time clk;
template<unsigned BUSWIDTH=32>
void registerResources(sysc::tlm_target<BUSWIDTH>& target);
};
}
//////////////////////////////////////////////////////////////////////////////
// member functions
//////////////////////////////////////////////////////////////////////////////
template<unsigned BUSWIDTH>
uart_regs<BUSWIDTH>::uart_regs(sc_core::sc_module_name nm)
inline sysc::uart_regs::uart_regs(sc_core::sc_module_name nm)
: sc_core::sc_module(nm)
, sysc::tlm_target<BUSWIDTH>(clk)
, NAMED(txdata, r_txdata, 0, *this)
, NAMED(rxdata, r_rxdata, 0, *this)
, NAMED(txctrl, r_txctrl, 0, *this)
@ -98,14 +116,17 @@ uart_regs<BUSWIDTH>::uart_regs(sc_core::sc_module_name nm)
, NAMED(ip, r_ip, 0, *this)
, NAMED(div, r_div, 0, *this)
{
this->socket_map.addEntry(&txdata, 0x0UL, 0x4UL);
this->socket_map.addEntry(&rxdata, 0x4UL, 0x4UL);
this->socket_map.addEntry(&txctrl, 0x8UL, 0x4UL);
this->socket_map.addEntry(&rxctrl, 0xcUL, 0x4UL);
this->socket_map.addEntry(&ie, 0x10UL, 0x4UL);
this->socket_map.addEntry(&ip, 0x14UL, 0x4UL);
this->socket_map.addEntry(&div, 0x18UL, 0x4UL);
}
template<unsigned BUSWIDTH>
inline void sysc::uart_regs::registerResources(sysc::tlm_target<BUSWIDTH>& target) {
target.addResource(txdata, 0x0UL, 0x4UL);
target.addResource(rxdata, 0x4UL, 0x4UL);
target.addResource(txctrl, 0x8UL, 0x4UL);
target.addResource(rxctrl, 0xcUL, 0x4UL);
target.addResource(ie, 0x10UL, 0x4UL);
target.addResource(ip, 0x14UL, 0x4UL);
target.addResource(div, 0x18UL, 0x4UL);
}
#endif // _UART_REGS_H_

3
examples/simple_system/simple_system.cpp
View File

@ -45,6 +45,9 @@ simple_system::simple_system(sc_core::sc_module_name nm)
i_spi.clk_i(s_clk);
i_gpio.clk_i(s_clk);
s_clk.write(10_ns);
i_uart.rst_i(s_rst);
i_spi.rst_i(s_rst);
i_gpio.rst_i(s_rst);
i_master.rst_i(s_rst);

17
examples/simple_system/spi.cpp
View File

@ -15,15 +15,23 @@
////////////////////////////////////////////////////////////////////////////////
#include "spi.h"
#include "gen/spi_regs.h"
#include "sysc/utilities.h"
namespace sysc {
spi::spi(sc_core::sc_module_name nm)
: spi_regs<>(nm)
: sc_core::sc_module(nm)
, tlm_target<>(clk)
, NAMED(clk_i)
, NAMED(rst_i)
, NAMEDD(spi_regs, regs)
{
regs->registerResources(*this);
SC_METHOD(clock_cb);
sensitive<<clk_i;
SC_METHOD(reset_cb);
sensitive<<rst_i;
}
spi::~spi() {
@ -33,4 +41,11 @@ void spi::clock_cb() {
this->clk=clk_i.read();
}
void spi::reset_cb() {
if(rst_i.read())
regs->reset_start();
else
regs->reset_stop();
}
} /* namespace sysc */

10
examples/simple_system/spi.h
View File

@ -17,18 +17,24 @@
#ifndef _SPI_H_
#define _SPI_H_
#include "gen/spi_regs.h"
#include <sysc/tlm_target.h>
namespace sysc {
class spi: public spi_regs<> {
class spi_regs;
class spi: public sc_core::sc_module, public tlm_target<> {
public:
SC_HAS_PROCESS(spi);
sc_core::sc_in<sc_core::sc_time> clk_i;
sc_core::sc_in<bool> rst_i;
spi(sc_core::sc_module_name nm);
virtual ~spi();
protected:
void clock_cb();
void reset_cb();
sc_core::sc_time clk;
std::unique_ptr<spi_regs> regs;
};
} /* namespace sysc */

17
examples/simple_system/uart.cpp
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@ -15,15 +15,23 @@
////////////////////////////////////////////////////////////////////////////////
#include "uart.h"
#include "gen/uart_regs.h"
#include "sysc/utilities.h"
namespace sysc {
uart::uart(sc_core::sc_module_name nm)
: uart_regs<>(nm)
: sc_core::sc_module(nm)
, tlm_target<>(clk)
, NAMED(clk_i)
, NAMED(rst_i)
, NAMEDD(uart_regs, regs)
{
regs->registerResources(*this);
SC_METHOD(clock_cb);
sensitive<<clk_i;
SC_METHOD(reset_cb);
sensitive<<rst_i;
}
uart::~uart() {
@ -33,4 +41,11 @@ void uart::clock_cb() {
this->clk=clk_i.read();
}
void uart::reset_cb() {
if(rst_i.read())
regs->reset_start();
else
regs->reset_stop();
}
} /* namespace sysc */

10
examples/simple_system/uart.h
View File

@ -17,18 +17,24 @@
#ifndef _UART_H_
#define _UART_H_
#include "gen/uart_regs.h"
#include <sysc/tlm_target.h>
namespace sysc {
class uart: public uart_regs<> {
class uart_regs;
class uart: public sc_core::sc_module, public tlm_target<> {
public:
SC_HAS_PROCESS(uart);
sc_core::sc_in<sc_core::sc_time> clk_i;
sc_core::sc_in<bool> rst_i;
uart(sc_core::sc_module_name nm);
virtual ~uart();
protected:
void clock_cb();
void reset_cb();
sc_core::sc_time clk;
std::unique_ptr<uart_regs> regs;
};
} /* namespace sysc */