Completely changed register instantiation
This commit is contained in:
parent
010c5590d8
commit
68a3a36d5d
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@ -1,18 +1,3 @@
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/*******************************************************************************
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* Copyright 2017 eyck@minres.com
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*
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* Licensed under the Apache License, Version 2.0 (the "License"); you may not
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* use this file except in compliance with the License. You may obtain a copy
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* of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations under
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* the License.
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******************************************************************************/
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#ifndef _E300_PLAT_MAP_H_
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#ifndef _E300_PLAT_MAP_H_
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#define _E300_PLAT_MAP_H_
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#define _E300_PLAT_MAP_H_
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// need double braces, see https://stackoverflow.com/questions/6893700/how-to-construct-stdarray-object-with-initializer-list#6894191
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// need double braces, see https://stackoverflow.com/questions/6893700/how-to-construct-stdarray-object-with-initializer-list#6894191
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@ -1,25 +1,44 @@
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/*******************************************************************************
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////////////////////////////////////////////////////////////////////////////////
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* Copyright 2017 eyck@minres.com
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// Copyright (C) 2017, MINRES Technologies GmbH
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*
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// All rights reserved.
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* Licensed under the Apache License, Version 2.0 (the "License"); you may not
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//
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* use this file except in compliance with the License. You may obtain a copy
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// Redistribution and use in source and binary forms, with or without
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* of the License at
|
// modification, are permitted provided that the following conditions are met:
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*
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//
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||||||
* http://www.apache.org/licenses/LICENSE-2.0
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// 1. Redistributions of source code must retain the above copyright notice,
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||||||
*
|
// this list of conditions and the following disclaimer.
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||||||
* Unless required by applicable law or agreed to in writing, software
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//
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
|
// 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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// this list of conditions and the following disclaimer in the documentation
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||||||
* License for the specific language governing permissions and limitations under
|
// and/or other materials provided with the distribution.
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* the License.
|
//
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******************************************************************************/
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// 3. Neither the name of the copyright holder nor the names of its contributors
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// may be used to endorse or promote products derived from this software
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// without specific prior written permission.
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||||||
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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// POSSIBILITY OF SUCH DAMAGE.
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//
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// Created on: Tue Sep 19 18:02:10 CEST 2017
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// * gpio_regs.h Author: <RDL Generator>
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//
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////////////////////////////////////////////////////////////////////////////////
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#ifndef _GPIO_REGS_H_
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#ifndef _GPIO_REGS_H_
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#define _GPIO_REGS_H_
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#define _GPIO_REGS_H_
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#include <sysc/utilities.h>
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#include <util/bit_field.h>
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#include <util/bit_field.h>
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#include <sysc/register.h>
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#include <sysc/register.h>
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#include <sysc/utilities.h>
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#include <sysc/tlm_target.h>
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#include <sysc/tlm_target.h>
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namespace sysc {
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namespace sysc {
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@ -28,7 +47,7 @@ class gpio_regs :
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public sc_core::sc_module,
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public sc_core::sc_module,
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public sysc::resetable
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public sysc::resetable
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{
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{
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public:
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protected:
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// storage declarations
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// storage declarations
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uint32_t r_value;
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uint32_t r_value;
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@ -83,14 +102,13 @@ public:
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sysc::sc_register<uint32_t> iof_sel;
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sysc::sc_register<uint32_t> iof_sel;
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sysc::sc_register<uint32_t> out_xor;
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sysc::sc_register<uint32_t> out_xor;
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public:
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gpio_regs(sc_core::sc_module_name nm);
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gpio_regs(sc_core::sc_module_name nm);
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template<unsigned BUSWIDTH=32>
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template<unsigned BUSWIDTH=32>
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void registerResources(sysc::tlm_target<BUSWIDTH>& target);
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void registerResources(sysc::tlm_target<BUSWIDTH>& target);
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};
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};
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}
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}
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//////////////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////////////
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// member functions
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// member functions
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//////////////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////////////
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@ -1,35 +1,52 @@
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/*******************************************************************************
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////////////////////////////////////////////////////////////////////////////////
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* Copyright 2017 eyck@minres.com
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// Copyright (C) 2017, MINRES Technologies GmbH
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*
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// All rights reserved.
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* Licensed under the Apache License, Version 2.0 (the "License"); you may not
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//
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||||||
* use this file except in compliance with the License. You may obtain a copy
|
// Redistribution and use in source and binary forms, with or without
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* of the License at
|
// modification, are permitted provided that the following conditions are met:
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*
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//
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* http://www.apache.org/licenses/LICENSE-2.0
|
// 1. Redistributions of source code must retain the above copyright notice,
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||||||
*
|
// this list of conditions and the following disclaimer.
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* Unless required by applicable law or agreed to in writing, software
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//
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||||||
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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// 2. Redistributions in binary form must reproduce the above copyright notice,
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||||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
|
// this list of conditions and the following disclaimer in the documentation
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* License for the specific language governing permissions and limitations under
|
// and/or other materials provided with the distribution.
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* the License.
|
//
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******************************************************************************/
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// 3. Neither the name of the copyright holder nor the names of its contributors
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// may be used to endorse or promote products derived from this software
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// without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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||||||
|
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||||
|
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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||||||
|
// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
|
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// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||||
|
// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||||
|
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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||||||
|
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||||
|
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||||
|
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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// POSSIBILITY OF SUCH DAMAGE.
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//
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// Created on: Tue Sep 19 18:02:09 CEST 2017
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// * spi_regs.h Author: <RDL Generator>
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//
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////////////////////////////////////////////////////////////////////////////////
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#ifndef _SPI_REGS_H_
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#ifndef _SPI_REGS_H_
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#define _SPI_REGS_H_
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#define _SPI_REGS_H_
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#include <sysc/utilities.h>
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#include <util/bit_field.h>
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#include <util/bit_field.h>
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#include <sysc/register.h>
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#include <sysc/register.h>
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#include <sysc/utilities.h>
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#include <sysc/tlm_target.h>
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#include <sysc/tlm_target.h>
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namespace sysc {
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namespace sysc {
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template<unsigned BUSWIDTH=32>
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class spi_regs :
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class spi_regs :
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public sc_core::sc_module,
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public sc_core::sc_module,
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public sysc::tlm_target<BUSWIDTH>,
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public sysc::resetable
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public sysc::resetable
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{
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{
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protected:
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protected:
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// storage declarations
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// storage declarations
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BEGIN_BF_DECL(sckdiv_t, uint32_t);
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BEGIN_BF_DECL(sckdiv_t, uint32_t);
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@ -127,18 +144,19 @@ protected:
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sysc::sc_register<typename ie_t::StorageType> ie;
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sysc::sc_register<typename ie_t::StorageType> ie;
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sysc::sc_register<typename ip_t::StorageType> ip;
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sysc::sc_register<typename ip_t::StorageType> ip;
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public:
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spi_regs(sc_core::sc_module_name nm);
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spi_regs(sc_core::sc_module_name nm);
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protected:
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sc_core::sc_time clk;
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template<unsigned BUSWIDTH=32>
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void registerResources(sysc::tlm_target<BUSWIDTH>& target);
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};
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};
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}
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//////////////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////////////
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// member functions
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// member functions
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//////////////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////////////
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template<unsigned BUSWIDTH>
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inline sysc::spi_regs::spi_regs(sc_core::sc_module_name nm)
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spi_regs<BUSWIDTH>::spi_regs(sc_core::sc_module_name nm)
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: sc_core::sc_module(nm)
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: sc_core::sc_module(nm)
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, sysc::tlm_target<BUSWIDTH>(clk)
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, NAMED(sckdiv, r_sckdiv, 0, *this)
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, NAMED(sckdiv, r_sckdiv, 0, *this)
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, NAMED(sckmode, r_sckmode, 0, *this)
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, NAMED(sckmode, r_sckmode, 0, *this)
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, NAMED(csid, r_csid, 0, *this)
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, NAMED(csid, r_csid, 0, *this)
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@ -156,23 +174,26 @@ spi_regs<BUSWIDTH>::spi_regs(sc_core::sc_module_name nm)
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, NAMED(ie, r_ie, 0, *this)
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, NAMED(ie, r_ie, 0, *this)
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, NAMED(ip, r_ip, 0, *this)
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, NAMED(ip, r_ip, 0, *this)
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{
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{
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this->socket_map.addEntry(&sckdiv, 0x0UL, 0x4UL);
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this->socket_map.addEntry(&sckmode, 0x4UL, 0x4UL);
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this->socket_map.addEntry(&csid, 0x10UL, 0x4UL);
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this->socket_map.addEntry(&csdef, 0x14UL, 0x4UL);
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this->socket_map.addEntry(&csmode, 0x18UL, 0x4UL);
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this->socket_map.addEntry(&delay0, 0x28UL, 0x4UL);
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this->socket_map.addEntry(&delay1, 0x2cUL, 0x4UL);
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this->socket_map.addEntry(&fmt, 0x40UL, 0x4UL);
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this->socket_map.addEntry(&txdata, 0x48UL, 0x4UL);
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this->socket_map.addEntry(&rxdata, 0x4cUL, 0x4UL);
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this->socket_map.addEntry(&txmark, 0x50UL, 0x4UL);
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this->socket_map.addEntry(&rxmark, 0x54UL, 0x4UL);
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this->socket_map.addEntry(&fctrl, 0x60UL, 0x4UL);
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this->socket_map.addEntry(&ffmt, 0x64UL, 0x4UL);
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this->socket_map.addEntry(&ie, 0x70UL, 0x4UL);
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this->socket_map.addEntry(&ip, 0x74UL, 0x4UL);
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}
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}
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template<unsigned BUSWIDTH>
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inline void sysc::spi_regs::registerResources(sysc::tlm_target<BUSWIDTH>& target) {
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target.addResource(sckdiv, 0x0UL, 0x4UL);
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target.addResource(sckmode, 0x4UL, 0x4UL);
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target.addResource(csid, 0x10UL, 0x4UL);
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target.addResource(csdef, 0x14UL, 0x4UL);
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target.addResource(csmode, 0x18UL, 0x4UL);
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target.addResource(delay0, 0x28UL, 0x4UL);
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target.addResource(delay1, 0x2cUL, 0x4UL);
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target.addResource(fmt, 0x40UL, 0x4UL);
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target.addResource(txdata, 0x48UL, 0x4UL);
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target.addResource(rxdata, 0x4cUL, 0x4UL);
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target.addResource(txmark, 0x50UL, 0x4UL);
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target.addResource(rxmark, 0x54UL, 0x4UL);
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target.addResource(fctrl, 0x60UL, 0x4UL);
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target.addResource(ffmt, 0x64UL, 0x4UL);
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target.addResource(ie, 0x70UL, 0x4UL);
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target.addResource(ip, 0x74UL, 0x4UL);
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}
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}
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#endif // _SPI_REGS_H_
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#endif // _SPI_REGS_H_
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@ -1,35 +1,52 @@
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/*******************************************************************************
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////////////////////////////////////////////////////////////////////////////////
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* Copyright 2017 eyck@minres.com
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// Copyright (C) 2017, MINRES Technologies GmbH
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*
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// All rights reserved.
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||||||
* Licensed under the Apache License, Version 2.0 (the "License"); you may not
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//
|
||||||
* use this file except in compliance with the License. You may obtain a copy
|
// Redistribution and use in source and binary forms, with or without
|
||||||
* of the License at
|
// modification, are permitted provided that the following conditions are met:
|
||||||
*
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//
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* http://www.apache.org/licenses/LICENSE-2.0
|
// 1. Redistributions of source code must retain the above copyright notice,
|
||||||
*
|
// this list of conditions and the following disclaimer.
|
||||||
* Unless required by applicable law or agreed to in writing, software
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//
|
||||||
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
|
// 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
|
// this list of conditions and the following disclaimer in the documentation
|
||||||
* License for the specific language governing permissions and limitations under
|
// and/or other materials provided with the distribution.
|
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* the License.
|
//
|
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******************************************************************************/
|
// 3. Neither the name of the copyright holder nor the names of its contributors
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||||||
|
// may be used to endorse or promote products derived from this software
|
||||||
|
// without specific prior written permission.
|
||||||
|
//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||||
|
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||||
|
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||||
|
// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
|
||||||
|
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||||
|
// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||||
|
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||||
|
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||||
|
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||||
|
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
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|
// POSSIBILITY OF SUCH DAMAGE.
|
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//
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// Created on: Tue Sep 19 18:02:09 CEST 2017
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// * uart_regs.h Author: <RDL Generator>
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//
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////////////////////////////////////////////////////////////////////////////////
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#ifndef _UART_REGS_H_
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#ifndef _UART_REGS_H_
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#define _UART_REGS_H_
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#define _UART_REGS_H_
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#include <sysc/utilities.h>
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#include <util/bit_field.h>
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#include <util/bit_field.h>
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#include <sysc/register.h>
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#include <sysc/register.h>
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#include <sysc/utilities.h>
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#include <sysc/tlm_target.h>
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#include <sysc/tlm_target.h>
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namespace sysc {
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namespace sysc {
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template<unsigned BUSWIDTH=32>
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class uart_regs :
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class uart_regs :
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public sc_core::sc_module,
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public sc_core::sc_module,
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public sysc::tlm_target<BUSWIDTH>,
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public sysc::resetable
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public sysc::resetable
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{
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{
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protected:
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protected:
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// storage declarations
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// storage declarations
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BEGIN_BF_DECL(txdata_t, uint32_t);
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BEGIN_BF_DECL(txdata_t, uint32_t);
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@ -78,18 +95,19 @@ protected:
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sysc::sc_register<typename ip_t::StorageType> ip;
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sysc::sc_register<typename ip_t::StorageType> ip;
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sysc::sc_register<typename div_t::StorageType> div;
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sysc::sc_register<typename div_t::StorageType> div;
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public:
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uart_regs(sc_core::sc_module_name nm);
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uart_regs(sc_core::sc_module_name nm);
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protected:
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sc_core::sc_time clk;
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template<unsigned BUSWIDTH=32>
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void registerResources(sysc::tlm_target<BUSWIDTH>& target);
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};
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};
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}
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//////////////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////////////
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// member functions
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// member functions
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//////////////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////////////
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template<unsigned BUSWIDTH>
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inline sysc::uart_regs::uart_regs(sc_core::sc_module_name nm)
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uart_regs<BUSWIDTH>::uart_regs(sc_core::sc_module_name nm)
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: sc_core::sc_module(nm)
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: sc_core::sc_module(nm)
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, sysc::tlm_target<BUSWIDTH>(clk)
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, NAMED(txdata, r_txdata, 0, *this)
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, NAMED(txdata, r_txdata, 0, *this)
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, NAMED(rxdata, r_rxdata, 0, *this)
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, NAMED(rxdata, r_rxdata, 0, *this)
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, NAMED(txctrl, r_txctrl, 0, *this)
|
, NAMED(txctrl, r_txctrl, 0, *this)
|
||||||
|
@ -98,14 +116,17 @@ uart_regs<BUSWIDTH>::uart_regs(sc_core::sc_module_name nm)
|
||||||
, NAMED(ip, r_ip, 0, *this)
|
, NAMED(ip, r_ip, 0, *this)
|
||||||
, NAMED(div, r_div, 0, *this)
|
, NAMED(div, r_div, 0, *this)
|
||||||
{
|
{
|
||||||
this->socket_map.addEntry(&txdata, 0x0UL, 0x4UL);
|
|
||||||
this->socket_map.addEntry(&rxdata, 0x4UL, 0x4UL);
|
|
||||||
this->socket_map.addEntry(&txctrl, 0x8UL, 0x4UL);
|
|
||||||
this->socket_map.addEntry(&rxctrl, 0xcUL, 0x4UL);
|
|
||||||
this->socket_map.addEntry(&ie, 0x10UL, 0x4UL);
|
|
||||||
this->socket_map.addEntry(&ip, 0x14UL, 0x4UL);
|
|
||||||
this->socket_map.addEntry(&div, 0x18UL, 0x4UL);
|
|
||||||
}
|
}
|
||||||
|
|
||||||
|
template<unsigned BUSWIDTH>
|
||||||
|
inline void sysc::uart_regs::registerResources(sysc::tlm_target<BUSWIDTH>& target) {
|
||||||
|
target.addResource(txdata, 0x0UL, 0x4UL);
|
||||||
|
target.addResource(rxdata, 0x4UL, 0x4UL);
|
||||||
|
target.addResource(txctrl, 0x8UL, 0x4UL);
|
||||||
|
target.addResource(rxctrl, 0xcUL, 0x4UL);
|
||||||
|
target.addResource(ie, 0x10UL, 0x4UL);
|
||||||
|
target.addResource(ip, 0x14UL, 0x4UL);
|
||||||
|
target.addResource(div, 0x18UL, 0x4UL);
|
||||||
}
|
}
|
||||||
|
|
||||||
#endif // _UART_REGS_H_
|
#endif // _UART_REGS_H_
|
||||||
|
|
|
@ -45,6 +45,9 @@ simple_system::simple_system(sc_core::sc_module_name nm)
|
||||||
i_spi.clk_i(s_clk);
|
i_spi.clk_i(s_clk);
|
||||||
i_gpio.clk_i(s_clk);
|
i_gpio.clk_i(s_clk);
|
||||||
s_clk.write(10_ns);
|
s_clk.write(10_ns);
|
||||||
|
|
||||||
|
i_uart.rst_i(s_rst);
|
||||||
|
i_spi.rst_i(s_rst);
|
||||||
i_gpio.rst_i(s_rst);
|
i_gpio.rst_i(s_rst);
|
||||||
i_master.rst_i(s_rst);
|
i_master.rst_i(s_rst);
|
||||||
|
|
||||||
|
|
|
@ -15,15 +15,23 @@
|
||||||
////////////////////////////////////////////////////////////////////////////////
|
////////////////////////////////////////////////////////////////////////////////
|
||||||
|
|
||||||
#include "spi.h"
|
#include "spi.h"
|
||||||
|
#include "gen/spi_regs.h"
|
||||||
|
#include "sysc/utilities.h"
|
||||||
|
|
||||||
namespace sysc {
|
namespace sysc {
|
||||||
|
|
||||||
spi::spi(sc_core::sc_module_name nm)
|
spi::spi(sc_core::sc_module_name nm)
|
||||||
: spi_regs<>(nm)
|
: sc_core::sc_module(nm)
|
||||||
|
, tlm_target<>(clk)
|
||||||
, NAMED(clk_i)
|
, NAMED(clk_i)
|
||||||
|
, NAMED(rst_i)
|
||||||
|
, NAMEDD(spi_regs, regs)
|
||||||
{
|
{
|
||||||
|
regs->registerResources(*this);
|
||||||
SC_METHOD(clock_cb);
|
SC_METHOD(clock_cb);
|
||||||
sensitive<<clk_i;
|
sensitive<<clk_i;
|
||||||
|
SC_METHOD(reset_cb);
|
||||||
|
sensitive<<rst_i;
|
||||||
}
|
}
|
||||||
|
|
||||||
spi::~spi() {
|
spi::~spi() {
|
||||||
|
@ -33,4 +41,11 @@ void spi::clock_cb() {
|
||||||
this->clk=clk_i.read();
|
this->clk=clk_i.read();
|
||||||
}
|
}
|
||||||
|
|
||||||
|
void spi::reset_cb() {
|
||||||
|
if(rst_i.read())
|
||||||
|
regs->reset_start();
|
||||||
|
else
|
||||||
|
regs->reset_stop();
|
||||||
|
}
|
||||||
|
|
||||||
} /* namespace sysc */
|
} /* namespace sysc */
|
||||||
|
|
|
@ -17,18 +17,24 @@
|
||||||
#ifndef _SPI_H_
|
#ifndef _SPI_H_
|
||||||
#define _SPI_H_
|
#define _SPI_H_
|
||||||
|
|
||||||
#include "gen/spi_regs.h"
|
#include <sysc/tlm_target.h>
|
||||||
|
|
||||||
namespace sysc {
|
namespace sysc {
|
||||||
|
|
||||||
class spi: public spi_regs<> {
|
class spi_regs;
|
||||||
|
|
||||||
|
class spi: public sc_core::sc_module, public tlm_target<> {
|
||||||
public:
|
public:
|
||||||
SC_HAS_PROCESS(spi);
|
SC_HAS_PROCESS(spi);
|
||||||
sc_core::sc_in<sc_core::sc_time> clk_i;
|
sc_core::sc_in<sc_core::sc_time> clk_i;
|
||||||
|
sc_core::sc_in<bool> rst_i;
|
||||||
spi(sc_core::sc_module_name nm);
|
spi(sc_core::sc_module_name nm);
|
||||||
virtual ~spi();
|
virtual ~spi();
|
||||||
protected:
|
protected:
|
||||||
void clock_cb();
|
void clock_cb();
|
||||||
|
void reset_cb();
|
||||||
|
sc_core::sc_time clk;
|
||||||
|
std::unique_ptr<spi_regs> regs;
|
||||||
};
|
};
|
||||||
|
|
||||||
} /* namespace sysc */
|
} /* namespace sysc */
|
||||||
|
|
|
@ -15,15 +15,23 @@
|
||||||
////////////////////////////////////////////////////////////////////////////////
|
////////////////////////////////////////////////////////////////////////////////
|
||||||
|
|
||||||
#include "uart.h"
|
#include "uart.h"
|
||||||
|
#include "gen/uart_regs.h"
|
||||||
|
#include "sysc/utilities.h"
|
||||||
|
|
||||||
namespace sysc {
|
namespace sysc {
|
||||||
|
|
||||||
uart::uart(sc_core::sc_module_name nm)
|
uart::uart(sc_core::sc_module_name nm)
|
||||||
: uart_regs<>(nm)
|
: sc_core::sc_module(nm)
|
||||||
|
, tlm_target<>(clk)
|
||||||
, NAMED(clk_i)
|
, NAMED(clk_i)
|
||||||
|
, NAMED(rst_i)
|
||||||
|
, NAMEDD(uart_regs, regs)
|
||||||
{
|
{
|
||||||
|
regs->registerResources(*this);
|
||||||
SC_METHOD(clock_cb);
|
SC_METHOD(clock_cb);
|
||||||
sensitive<<clk_i;
|
sensitive<<clk_i;
|
||||||
|
SC_METHOD(reset_cb);
|
||||||
|
sensitive<<rst_i;
|
||||||
}
|
}
|
||||||
|
|
||||||
uart::~uart() {
|
uart::~uart() {
|
||||||
|
@ -33,4 +41,11 @@ void uart::clock_cb() {
|
||||||
this->clk=clk_i.read();
|
this->clk=clk_i.read();
|
||||||
}
|
}
|
||||||
|
|
||||||
|
void uart::reset_cb() {
|
||||||
|
if(rst_i.read())
|
||||||
|
regs->reset_start();
|
||||||
|
else
|
||||||
|
regs->reset_stop();
|
||||||
|
}
|
||||||
|
|
||||||
} /* namespace sysc */
|
} /* namespace sysc */
|
||||||
|
|
|
@ -17,18 +17,24 @@
|
||||||
#ifndef _UART_H_
|
#ifndef _UART_H_
|
||||||
#define _UART_H_
|
#define _UART_H_
|
||||||
|
|
||||||
#include "gen/uart_regs.h"
|
#include <sysc/tlm_target.h>
|
||||||
|
|
||||||
namespace sysc {
|
namespace sysc {
|
||||||
|
|
||||||
class uart: public uart_regs<> {
|
class uart_regs;
|
||||||
|
|
||||||
|
class uart: public sc_core::sc_module, public tlm_target<> {
|
||||||
public:
|
public:
|
||||||
SC_HAS_PROCESS(uart);
|
SC_HAS_PROCESS(uart);
|
||||||
sc_core::sc_in<sc_core::sc_time> clk_i;
|
sc_core::sc_in<sc_core::sc_time> clk_i;
|
||||||
|
sc_core::sc_in<bool> rst_i;
|
||||||
uart(sc_core::sc_module_name nm);
|
uart(sc_core::sc_module_name nm);
|
||||||
virtual ~uart();
|
virtual ~uart();
|
||||||
protected:
|
protected:
|
||||||
void clock_cb();
|
void clock_cb();
|
||||||
|
void reset_cb();
|
||||||
|
sc_core::sc_time clk;
|
||||||
|
std::unique_ptr<uart_regs> regs;
|
||||||
};
|
};
|
||||||
|
|
||||||
} /* namespace sysc */
|
} /* namespace sysc */
|
||||||
|
|
Loading…
Reference in New Issue