cleans up project and adds axi4_pin_level test
This commit is contained in:
9
tests/axi4_pin_level/CMakeLists.txt
Normal file
9
tests/axi4_pin_level/CMakeLists.txt
Normal file
@ -0,0 +1,9 @@
|
||||
project (axi4_pin_level)
|
||||
|
||||
add_executable(${PROJECT_NAME}
|
||||
sc_main.cpp
|
||||
narrow_burst_test.cpp
|
||||
)
|
||||
target_link_libraries (${PROJECT_NAME} PUBLIC scc test_util Catch2::Catch2)
|
||||
|
||||
add_test(NAME narrow_burst COMMAND ${PROJECT_NAME})
|
||||
119
tests/axi4_pin_level/narrow_burst_test.cpp
Normal file
119
tests/axi4_pin_level/narrow_burst_test.cpp
Normal file
@ -0,0 +1,119 @@
|
||||
|
||||
#define SC_INCLUDE_DYNAMIC_PROCESSES
|
||||
#include "../axi4_pin_level/testbench.h"
|
||||
#include <factory.h>
|
||||
|
||||
#include <catch2/catch_all.hpp>
|
||||
|
||||
using namespace sc_core;
|
||||
|
||||
template<typename bus_cfg>
|
||||
tlm::tlm_generic_payload* prepare_trans(uint64_t start_address, size_t len, unsigned id_offs = 0,
|
||||
unsigned addr_offs = 0) {
|
||||
static uint8_t id{0};
|
||||
auto trans = tlm::scc::tlm_mm<>::get().allocate<axi::axi4_extension>(len);
|
||||
trans->set_address(start_address);
|
||||
tlm::scc::setId(*trans, id);
|
||||
auto ext = trans->get_extension<axi::axi4_extension>();
|
||||
trans->set_data_length(len);
|
||||
trans->set_streaming_width(len);
|
||||
ext->set_size(scc::ilog2(4));
|
||||
sc_assert(len < (bus_cfg::BUSWIDTH / 8) || len % (bus_cfg::BUSWIDTH / 8) == 0);
|
||||
auto length = (len * 8 - 1) / 32;
|
||||
if(start_address % (bus_cfg::BUSWIDTH / 8))
|
||||
length++;
|
||||
ext->set_length(length);
|
||||
// ext->set_burst(len * 8 > bus_cfg::buswidth ? axi::burst_e::INCR : axi::burst_e::FIXED);
|
||||
ext->set_burst(axi::burst_e::INCR);
|
||||
ext->set_id(id | id_offs);
|
||||
id = (id + 1) % 8;
|
||||
return trans;
|
||||
}
|
||||
|
||||
inline void randomize(tlm::tlm_generic_payload& gp) {
|
||||
static uint8_t req_cnt{0};
|
||||
auto addr = gp.get_address();
|
||||
uint8_t const* src = reinterpret_cast<uint8_t const*>(&addr);
|
||||
for(size_t i = 0; i < gp.get_data_length(); ++i) {
|
||||
*(gp.get_data_ptr() + i) = i % 2 ? i : req_cnt;
|
||||
}
|
||||
req_cnt++;
|
||||
}
|
||||
|
||||
TEST_CASE("AXI", "[axi]") {
|
||||
struct {
|
||||
unsigned int ResetCycles{10};
|
||||
unsigned int BurstLengthByte{16};
|
||||
unsigned int NumberOfIterations{10};
|
||||
unsigned resp_cnt{0};
|
||||
} setup;
|
||||
|
||||
auto& dut = factory::get<testbench>();
|
||||
dut.tgt_pe.set_operation_cb([&setup](axi::axi_protocol_types::tlm_payload_type& trans) -> unsigned {
|
||||
auto addr = trans.get_address();
|
||||
uint8_t const* src = reinterpret_cast<uint8_t const*>(&addr);
|
||||
for(size_t i = 0; i < trans.get_data_length(); ++i) {
|
||||
*(trans.get_data_ptr() + i) = i % 2 ? i : setup.resp_cnt;
|
||||
}
|
||||
setup.resp_cnt++;
|
||||
return 0;
|
||||
});
|
||||
|
||||
dut.rst.write(false);
|
||||
sc_start(3*dut.clk.period());
|
||||
dut.rst.write(true);
|
||||
sc_start(3*dut.clk.period());
|
||||
|
||||
auto run1 = sc_spawn([&dut, &setup](){
|
||||
unsigned int StartAddr{0x20};
|
||||
for(int i = 0; i < setup.NumberOfIterations; ++i) {
|
||||
SCCDEBUG("test") << "run0 executing transactions in iteration " << i;
|
||||
{ // 1
|
||||
tlm::scc::tlm_gp_shared_ptr trans = prepare_trans<testbench::bus_cfg>(StartAddr, setup.BurstLengthByte);
|
||||
randomize(*trans);
|
||||
trans->set_command(tlm::TLM_READ_COMMAND);
|
||||
dut.intor_pe.transport(*trans, false);
|
||||
if(trans->get_response_status() != tlm::TLM_OK_RESPONSE)
|
||||
SCCERR() << "Invalid response status" << trans->get_response_string();
|
||||
}
|
||||
StartAddr += setup.BurstLengthByte;
|
||||
{ // 2
|
||||
tlm::scc::tlm_gp_shared_ptr trans = prepare_trans<testbench::bus_cfg>(StartAddr, setup.BurstLengthByte);
|
||||
trans->set_command(tlm::TLM_WRITE_COMMAND);
|
||||
randomize(*trans);
|
||||
dut.intor_pe.transport(*trans, false);
|
||||
if(trans->get_response_status() != tlm::TLM_OK_RESPONSE)
|
||||
SCCERR() << "Invalid response status" << trans->get_response_string();
|
||||
}
|
||||
StartAddr += setup.BurstLengthByte;
|
||||
}
|
||||
});
|
||||
auto run2 = sc_spawn([&dut, &setup](){
|
||||
unsigned int StartAddr{0x1020};
|
||||
for(int i = 0; i < setup.NumberOfIterations; ++i) {
|
||||
SCCDEBUG("test") << "run1 executing transactions in iteration " << i;
|
||||
{ // 1
|
||||
tlm::scc::tlm_gp_shared_ptr trans = prepare_trans<testbench::bus_cfg>(StartAddr, setup.BurstLengthByte, 0x8);
|
||||
randomize(*trans);
|
||||
trans->set_command(tlm::TLM_READ_COMMAND);
|
||||
dut.intor_pe.transport(*trans, false);
|
||||
if(trans->get_response_status() != tlm::TLM_OK_RESPONSE)
|
||||
SCCERR() << "Invalid response status" << trans->get_response_string();
|
||||
}
|
||||
StartAddr += setup.BurstLengthByte;
|
||||
{ // 2
|
||||
tlm::scc::tlm_gp_shared_ptr trans = prepare_trans<testbench::bus_cfg>(StartAddr, setup.BurstLengthByte, 0x8);
|
||||
trans->set_command(tlm::TLM_WRITE_COMMAND);
|
||||
randomize(*trans);
|
||||
dut.intor_pe.transport(*trans, false);
|
||||
if(trans->get_response_status() != tlm::TLM_OK_RESPONSE)
|
||||
SCCERR() << "Invalid response status" << trans->get_response_string();
|
||||
}
|
||||
StartAddr += setup.BurstLengthByte;
|
||||
}
|
||||
});
|
||||
sc_start(1000 * dut.clk.period());
|
||||
REQUIRE(run1.terminated());
|
||||
REQUIRE(run2.terminated());
|
||||
REQUIRE(setup.resp_cnt==40);
|
||||
}
|
||||
25
tests/axi4_pin_level/sc_main.cpp
Normal file
25
tests/axi4_pin_level/sc_main.cpp
Normal file
@ -0,0 +1,25 @@
|
||||
/*
|
||||
* sc_main.cpp
|
||||
*
|
||||
* Created on:
|
||||
* Author:
|
||||
*/
|
||||
|
||||
#include "factory.h"
|
||||
#include <catch2/catch_session.hpp>
|
||||
#include "../axi4_pin_level/testbench.h"
|
||||
|
||||
using namespace scc;
|
||||
int sc_main(int argc, char* argv[]) {
|
||||
sc_report_handler::set_actions(SC_ID_MORE_THAN_ONE_SIGNAL_DRIVER_, SC_DO_NOTHING);
|
||||
scc::init_logging(LogConfig().logLevel(log::INFO).logAsync(false));
|
||||
scc::tracer trace("axi4_tlm_pin_tlm", scc::tracer::file_type::NONE, true);
|
||||
|
||||
factory::add<testbench> tb;
|
||||
|
||||
factory::get_instance().create();
|
||||
int result = Catch::Session().run( argc, argv );
|
||||
factory::get_instance().destroy();
|
||||
|
||||
return result + sc_report_handler::get_count(SC_ERROR) + sc_report_handler::get_count(SC_WARNING);
|
||||
}
|
||||
78
tests/axi4_pin_level/testbench.h
Normal file
78
tests/axi4_pin_level/testbench.h
Normal file
@ -0,0 +1,78 @@
|
||||
#ifndef _TESTBENCH_H_
|
||||
#define _TESTBENCH_H_
|
||||
|
||||
#include <axi/pe/axi_initiator.h>
|
||||
#include <axi/pe/simple_target.h>
|
||||
#include <axi/pin/axi4_initiator.h>
|
||||
#include <axi/pin/axi4_target.h>
|
||||
#include <axi/scv/recorder_modules.h>
|
||||
#include <scc.h>
|
||||
|
||||
using namespace sc_core;
|
||||
using namespace axi;
|
||||
using namespace axi::pe;
|
||||
|
||||
class testbench : public sc_core::sc_module {
|
||||
public:
|
||||
using bus_cfg = axi::axi4_cfg</*BUSWIDTH=*/64, /*ADDRWIDTH=*/32, /*IDWIDTH=*/4, /*USERWIDTH=*/1>;
|
||||
|
||||
sc_core::sc_time clk_period{10, sc_core::SC_NS};
|
||||
sc_core::sc_clock clk{"clk", clk_period, 0.5, sc_core::SC_ZERO_TIME, true};
|
||||
sc_core::sc_signal<bool> rst{"rst"};
|
||||
// initiator side
|
||||
axi::axi_initiator_socket<bus_cfg::BUSWIDTH> intor{"intor"};
|
||||
axi::scv::axi_recorder_module<bus_cfg::BUSWIDTH> intor_rec{"intor_rec"};
|
||||
axi::pin::axi4_initiator<bus_cfg> intor_bfm{"intor_bfm"};
|
||||
// signal accurate bus
|
||||
axi::aw_ch<bus_cfg, axi::signal_types> aw;
|
||||
axi::wdata_ch<bus_cfg, axi::signal_types> wdata;
|
||||
axi::b_ch<bus_cfg, axi::signal_types> b;
|
||||
axi::ar_ch<bus_cfg, axi::signal_types> ar;
|
||||
axi::rresp_ch<bus_cfg, axi::signal_types> rresp;
|
||||
axi::pin::axi4_target<bus_cfg> tgt_bfm{"tgt_bfm"};
|
||||
// target side
|
||||
axi::scv::axi_recorder_module<bus_cfg::BUSWIDTH> tgt_rec{"tgt_rec"};
|
||||
axi::axi_target_socket<bus_cfg::BUSWIDTH> tgt{"tgt"};
|
||||
// engines
|
||||
axi::pe::axi_initiator<bus_cfg::BUSWIDTH> intor_pe;
|
||||
axi::pe::simple_target<bus_cfg::BUSWIDTH> tgt_pe;
|
||||
|
||||
public:
|
||||
SC_HAS_PROCESS(testbench);
|
||||
testbench(): testbench("testbench") {}
|
||||
testbench(sc_core::sc_module_name nm)
|
||||
: sc_core::sc_module(nm)
|
||||
, intor_pe("intor_pe", intor)
|
||||
, tgt_pe("tgt_pe", tgt) {
|
||||
intor_pe.clk_i(clk);
|
||||
intor_bfm.clk_i(clk);
|
||||
tgt_bfm.clk_i(clk);
|
||||
tgt_pe.clk_i(clk);
|
||||
// pe socket to recorder
|
||||
intor(intor_rec.tsckt);
|
||||
// recorder to bfm
|
||||
intor_rec.isckt(intor_bfm.tsckt);
|
||||
// bfm to signals
|
||||
intor_bfm.bind_aw(aw);
|
||||
intor_bfm.bind_w(wdata);
|
||||
intor_bfm.bind_b(b);
|
||||
intor_bfm.bind_ar(ar);
|
||||
intor_bfm.bind_r(rresp);
|
||||
// signals to bfm
|
||||
tgt_bfm.bind_aw(aw);
|
||||
tgt_bfm.bind_w(wdata);
|
||||
tgt_bfm.bind_b(b);
|
||||
tgt_bfm.bind_ar(ar);
|
||||
tgt_bfm.bind_r(rresp);
|
||||
// bfm to recorder
|
||||
tgt_bfm.isckt(tgt_rec.tsckt);
|
||||
// recorder to target
|
||||
tgt_rec.isckt(tgt);
|
||||
}
|
||||
|
||||
|
||||
void run1() {
|
||||
}
|
||||
};
|
||||
|
||||
#endif // _TESTBENCH_H_
|
||||
Reference in New Issue
Block a user