SystemC/SystemC-Components-Test
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This commit is contained in:
Soeren Jung
2017-09-21 11:25:07 +02:00
parent e332ef87c1
commit 4b25eb0b29
2 changed files with 76 additions and 3 deletions
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60
etc/irq_wave.sav Normal file
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@@ -0,0 +1,60 @@
[*]
[*] GTKWave Analyzer v3.3.66 (w)1999-2015 BSI
[*] Fri Sep 22 20:16:21 2017
[*]
[dumpfile] "/home/valid/project/minres2/SystemC-Components-Test/simple_system.vcd"
[dumpfile_mtime] "Fri Sep 22 20:15:38 2017"
[dumpfile_size] 69714
[savefile] "/home/valid/project/minres2/SystemC-Components-Test/etc/irq_wave.sav"
[timestart] 4
[size] 1920 924
[pos] -1 -1
*-3.538420 30 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[sst_width] 397
[signals_width] 422
[sst_expanded] 1
[sst_vpaned_height] 334
@200
-System signals
@28
SystemC.\i_simple_system.s_rst
@24
SystemC.\i_simple_system.s_clk[63:0]
@28
SystemC.\i_simple_system.s_core_interrupt
SystemC.\i_simple_system.s_global_interrupts_0
SystemC.\i_simple_system.s_global_interrupts_1
SystemC.\i_simple_system.s_global_interrupts_2
SystemC.\i_simple_system.s_global_interrupts_3
SystemC.\i_simple_system.s_global_interrupts_4
@200
-Master
@28
SystemC.\i_simple_system.i_master.rst_i
SystemC.\i_simple_system.i_master.core_interrupt_i
@200
-PLIC ports
@24
SystemC.\i_simple_system.i_plic.rst_i
SystemC.\i_simple_system.i_plic.clk_i[63:0]
@28
SystemC.\i_simple_system.i_plic.global_interrupts_i_0
SystemC.\i_simple_system.i_plic.global_interrupts_i_1
SystemC.\i_simple_system.i_plic.global_interrupts_i_2
SystemC.\i_simple_system.i_plic.global_interrupts_i_3
SystemC.\i_simple_system.i_plic.global_interrupts_i_4
@200
-PLIC regs
@22
SystemC.\i_simple_system.i_plic.regs.enabled[31:0]
SystemC.\i_simple_system.i_plic.regs.pending[31:0]
@23
SystemC.\i_simple_system.i_plic.regs.priority0[31:0]
@22
SystemC.\i_simple_system.i_plic.regs.priority1[31:0]
SystemC.\i_simple_system.i_plic.regs.priority2[31:0]
SystemC.\i_simple_system.i_plic.regs.priority3[31:0]
SystemC.\i_simple_system.i_plic.regs.threshold[31:0]
SystemC.\i_simple_system.i_plic.regs.claim_complete[31:0]
[pattern_trace] 1
[pattern_trace] 0

19
examples/simple_system/sc_main.cpp
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@@ -23,7 +23,7 @@
#include "simple_system.h"
#include <sysc/tracer.h>
#include <sysc/scv_tr_db.h>
#include <sr_report/sr_report.h>
#include <sysc/report.h>
#include <boost/program_options.hpp>
#include <sysc/report.h>
#include <sstream>
@@ -38,8 +38,14 @@ const size_t ERROR_UNHANDLED_EXCEPTION = 2;
} // namespace
int sc_main(int argc, char* argv[]){
// Environment adaptations
putenv(const_cast<char*>("SC_SIGNAL_WRITE_CHECK=DISABLE"));
// sc_report_handler::set_handler(my_report_handler);
sysc::Logger::reporting_level()=log::DEBUG;
// todo: add module-name to log-file
///////////////////////////////////////////////////////////////////////////
// CLI argument parsing
///////////////////////////////////////////////////////////////////////////
@@ -67,6 +73,8 @@ int sc_main(int argc, char* argv[]){
// set up tracing & transaction recording
///////////////////////////////////////////////////////////////////////////
sysc::tracer trace("simple_system", sysc::tracer::TEXT, vm.count("trace"));
// todo: fix displayed clock period in VCD
///////////////////////////////////////////////////////////////////////////
// instantiate top level
///////////////////////////////////////////////////////////////////////////
@@ -76,8 +84,13 @@ int sc_main(int argc, char* argv[]){
///////////////////////////////////////////////////////////////////////////
// run simulation
///////////////////////////////////////////////////////////////////////////
sc_start(sc_core::sc_time(100, sc_core::SC_NS));
if(!sc_end_of_simulation_invoked()) sc_stop();
sc_start(sc_core::sc_time(1, sc_core::SC_MS));
// todo: provide end-of-simulation macros
if(!sc_core::sc_end_of_simulation_invoked()) {
LOG(logging::ERROR) << "simulation timed out";
sc_stop();
}
return 0;
}