adds AHB pin level adapter tests

.gitignore

@@ -40,3 +40,5 @@
 /*.vcd
 /.venv/
 /.pydevproject
+/*.fst
+/*.gtkw

.project

@@ -28,6 +28,5 @@
 		<nature>org.eclipse.cdt.core.ccnature</nature>
 		<nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
 		<nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
-		<nature>org.python.pydev.pythonNature</nature>
 	</natures>
 </projectDescription>

scc

@@ -1 +1 @@
-Subproject commit 77a9f223d7dc8cf838d95155f6023385bd6fdd03
+Subproject commit 94569eac10c4b8b5e3be6f8bcea7412b6e91396b

tests/CMakeLists.txt

@@ -1,5 +1,6 @@
 add_subdirectory(io-redirector)
 add_subdirectory(ordered_semaphore)
+add_subdirectory(ahb_pin_level)
 add_subdirectory(axi4_pin_level)
 add_subdirectory(ace_pin_level)
 add_subdirectory(configuration)

tests/ace_pin_level/ace_narrow_burst_test.cpp

@@ -10,20 +10,6 @@ using namespace sc_core;
 
 factory::add<testbench> tb;
 
-struct {
-    unsigned int ResetCycles{4};
-    unsigned int BurstLengthByte{16};
-//       unsigned int BurstLengthByte{32};
-    unsigned int BurstSizeBytes{8};
- //       unsigned int NumberOfIterations{8};
-   unsigned int NumberOfIterations{2};
-    unsigned int CachelineSizeBytes={64}; //
-    std::unordered_map<unsigned, std::pair<std::vector<tlm::scc::tlm_gp_shared_ptr>, std::vector<tlm::scc::tlm_gp_shared_ptr>>> read_tx;
-    std::unordered_map<unsigned, std::pair<std::vector<tlm::scc::tlm_gp_shared_ptr>, std::vector<tlm::scc::tlm_gp_shared_ptr>>> write_tx;
-    std::unordered_map<unsigned, std::pair<std::vector<tlm::scc::tlm_gp_shared_ptr>, std::vector<tlm::scc::tlm_gp_shared_ptr>>> snoop_tx;
-    unsigned resp_cnt{0};
-} state;
-
 int snoop_id=0;
 
 bool operator==(tlm::tlm_generic_payload const& a, tlm::tlm_generic_payload const& b){
@@ -77,31 +63,6 @@ inline void randomize(tlm::tlm_generic_payload& gp) {
     req_cnt++;
 }
 
-unsigned testbench::transport(tlm::tlm_generic_payload& trans) {
-    SCCDEBUG(__FUNCTION__)<<" update snoop trans, with snoop_id = " << snoop_id;
-  //  SCCDEBUG(__FUNCTION__)<<" in transport with trans " << trans;
-    // extracting address and snoop_e from ac_trans and pack them into cache data trans
-    auto ac_address = trans.get_address();
-    auto ext = trans.get_extension<ace_extension>();
-    auto ac_snoop=ext->get_snoop();
-
-    for(size_t i = 0; i < trans.get_data_length(); ++i) {
-        *(trans.get_data_ptr() + i) = i % 2 ? i : 128;
-    }
-    //SCCDEBUG(__FUNCTION__)<<" vector size " <<state.snoop_tx[snoop_id].second.size();
-    state.snoop_tx[snoop_id].second.emplace_back(&trans);
-
-    /*
-    ext->set_snoop_data_transfer(true);
-    ext->set_snoop_error(false);
-    ext->set_pass_dirty(false);
-    ext->set_shared(false);
-    ext->set_snoop_was_unique(false);
-    */
-    return 1;
-
-}
-
 template<typename STATE>
 unsigned run_scenario(STATE& state){
     auto& dut = factory::get<testbench>();
@@ -120,6 +81,18 @@ unsigned run_scenario(STATE& state){
         state.resp_cnt++;
         return 0;
     });
+    dut.transport_cb = [&state](tlm::tlm_generic_payload& trans) -> unsigned {
+        SCCDEBUG(__FUNCTION__)<<" update snoop trans, with snoop_id = " << snoop_id;
+        // extracting address and snoop_e from ac_trans and pack them into cache data trans
+        auto ac_address = trans.get_address();
+        auto ext = trans.get_extension<ace_extension>();
+        auto ac_snoop=ext->get_snoop();
+        for(size_t i = 0; i < trans.get_data_length(); ++i) {
+            *(trans.get_data_ptr() + i) = i % 2 ? i : 128;
+        }
+        state.snoop_tx[snoop_id].second.emplace_back(&trans);
+        return 1;
+    };
 
     dut.rst.write(false);
     sc_start(state.ResetCycles*dut.clk.period());
@@ -201,6 +174,17 @@ unsigned run_scenario(STATE& state){
 }
 
 TEST_CASE("ace_burst_alignment", "[AXI][pin-level]") {
+    struct {
+        unsigned int ResetCycles{4};
+        unsigned int BurstLengthByte{16};
+        unsigned int BurstSizeBytes{8};
+        unsigned int NumberOfIterations{2};
+        unsigned int CachelineSizeBytes={64}; //
+        std::unordered_map<unsigned, std::pair<std::vector<tlm::scc::tlm_gp_shared_ptr>, std::vector<tlm::scc::tlm_gp_shared_ptr>>> read_tx;
+        std::unordered_map<unsigned, std::pair<std::vector<tlm::scc::tlm_gp_shared_ptr>, std::vector<tlm::scc::tlm_gp_shared_ptr>>> write_tx;
+        std::unordered_map<unsigned, std::pair<std::vector<tlm::scc::tlm_gp_shared_ptr>, std::vector<tlm::scc::tlm_gp_shared_ptr>>> snoop_tx;
+        unsigned resp_cnt{0};
+    } state;
 
     state.resp_cnt=0;
     auto cycles = run_scenario(state);
@@ -250,7 +234,19 @@ TEST_CASE("ace_burst_alignment", "[AXI][pin-level]") {
 
 }
 
-TEST_CASE("axi4_narrow_burst", "[AXI][pin-level]") {
+TEST_CASE("ace_narrow_burst", "[AXI][pin-level]") {
+    struct {
+        unsigned int ResetCycles{4};
+        unsigned int BurstLengthByte{16};
+        unsigned int BurstSizeBytes{8};
+        unsigned int NumberOfIterations{2};
+        unsigned int CachelineSizeBytes={64}; //
+        std::unordered_map<unsigned, std::pair<std::vector<tlm::scc::tlm_gp_shared_ptr>, std::vector<tlm::scc::tlm_gp_shared_ptr>>> read_tx;
+        std::unordered_map<unsigned, std::pair<std::vector<tlm::scc::tlm_gp_shared_ptr>, std::vector<tlm::scc::tlm_gp_shared_ptr>>> write_tx;
+        std::unordered_map<unsigned, std::pair<std::vector<tlm::scc::tlm_gp_shared_ptr>, std::vector<tlm::scc::tlm_gp_shared_ptr>>> snoop_tx;
+        unsigned resp_cnt{0};
+    } state;
+
     state.resp_cnt=0;
     auto cycles = run_scenario(state);
 

tests/ace_pin_level/testbench.h

@@ -27,14 +27,14 @@ public:
     axi::ace_initiator_socket<bus_cfg::BUSWIDTH> intor{"ace_intor"};
     axi::pin::ace_initiator<bus_cfg> intor_bfm{"ace_intor_bfm"};
     // signal accurate bus
-    axi::aw_ch_ace<bus_cfg, axi::signal_types> aw;
+    axi::aw_ace<bus_cfg, axi::signal_types> aw;
-    axi::wdata_ch_ace<bus_cfg, axi::signal_types> wdata;
+    axi::wdata_ace<bus_cfg, axi::signal_types> wdata;
-    axi::b_ch_ace<bus_cfg, axi::signal_types> b;
+    axi::b_ace<bus_cfg, axi::signal_types> b;
-    axi::ar_ch_ace<bus_cfg, axi::signal_types> ar;
+    axi::ar_ace<bus_cfg, axi::signal_types> ar;
-    axi::rresp_ch_ace<bus_cfg, axi::signal_types> rresp;
+    axi::rresp_ace<bus_cfg, axi::signal_types> rresp;
-    axi::ac_ch_ace<bus_cfg, axi::signal_types> ac;
+    axi::ac_ace<bus_cfg, axi::signal_types> ac;
-    axi::cr_ch_ace<bus_cfg, axi::signal_types> cr;
+    axi::cr_ace<bus_cfg, axi::signal_types> cr;
-    axi::cd_ch_ace<bus_cfg, axi::signal_types> cd;
+    axi::cd_ace<bus_cfg, axi::signal_types> cd;
 
     axi::pin::ace_target<bus_cfg> tgt_bfm{"ace_tgt_bfm"};
     // target side
@@ -93,9 +93,8 @@ public:
 
     }
 
-    unsigned transport(tlm::tlm_generic_payload& trans) override ;
+    unsigned transport(tlm::tlm_generic_payload& trans) override { if(transport_cb) return transport_cb(trans); else return 0;}
-    void run1() {
+    std::function<unsigned(tlm::tlm_generic_payload&)> transport_cb;
-    }
 };
 
 #endif // _TESTBENCH_H_

tests/ahb_pin_level/CMakeLists.txt

@@ -0,0 +1,9 @@
+project (ahb_pin_level)
+
+add_executable(${PROJECT_NAME} 
+	bus_test.cpp
+	${test_util_SOURCE_DIR}/sc_main.cpp
+)
+target_link_libraries (${PROJECT_NAME} PUBLIC test_util)
+
+catch_discover_tests(${PROJECT_NAME})

tests/ahb_pin_level/bus_test.cpp

@@ -0,0 +1,260 @@
+
+#include "testbench.h"
+#include <factory.h>
+#include <tlm/scc/tlm_gp_shared.h>
+#undef CHECK
+#include <catch2/catch_all.hpp>
+#include <unordered_map>
+
+using namespace sc_core;
+using namespace ahb;
+
+factory::add<testbench> tb;
+
+bool operator==(tlm::tlm_generic_payload const& a, tlm::tlm_generic_payload const& b){
+    auto ret = true;
+    ret &= a.get_command() == b.get_command();
+    ret &= a.get_address() == b.get_address();
+    ret &= a.get_data_length() == b.get_data_length();
+    for(auto i=0u; i<a.get_data_length(); ++i)
+        ret &= a.get_data_ptr()[i] == b.get_data_ptr()[i];
+    //    if(a.get_byte_enable_ptr() && b.get_byte_enable_ptr()) {
+    //        ret &= a.get_byte_enable_length() == b.get_byte_enable_length();
+    //        for(auto i=0u; i<a.get_byte_enable_length(); ++i)
+    //            ret &= a.get_byte_enable_ptr()[i] == b.get_byte_enable_ptr()[i];
+    //    }
+    ret &= a.get_command() == b.get_command();
+    //if(!ret) SCCWARN()<<"Comparison failed: "<<a<<" and "<<b;
+    return ret;
+}
+
+template<unsigned BUSWIDTH>
+tlm::tlm_generic_payload* prepare_trans(uint64_t start_address, unsigned len, unsigned width) {
+    static unsigned id{0};
+    auto trans = tlm::scc::tlm_mm<>::get().allocate<ahb::ahb_extension>(len);
+    trans->set_address(start_address);
+    tlm::scc::setId(*trans, ++id);
+    auto ext = trans->get_extension<ahb::ahb_extension>();
+    trans->set_data_length(len);
+    trans->set_streaming_width(len);
+    ext->set_burst(ahb::burst_e::INCR);
+    return trans;
+}
+
+inline void randomize(tlm::tlm_generic_payload& gp) {
+    static uint8_t  req_cnt{0};
+    auto addr = gp.get_address();
+    uint8_t const* src = reinterpret_cast<uint8_t const*>(&addr);
+    for(size_t i = 0; i < gp.get_data_length(); ++i) {
+        *(gp.get_data_ptr() + i) = i % 2 ? i : req_cnt;
+    }
+    req_cnt++;
+}
+
+template<typename STATE>
+unsigned run_scenario(STATE& state, unsigned wait_states = 0){
+    auto& dut = factory::get<testbench>();
+    dut.tsck.register_b_transport([&state, wait_states](tlm::tlm_base_protocol_types::tlm_payload_type& trans, sc_core::sc_time& d) {
+        if(trans.is_read()) {
+            for(size_t i = 0; i < trans.get_data_length(); ++i) {
+                *(trans.get_data_ptr() + i) = i % 2 ? i : (state.resp_cnt+128);
+            }
+            state.read_tx.second.emplace_back(&trans);
+        }
+        if(trans.is_write())
+            state.write_tx.second.emplace_back(&trans);
+        SCCDEBUG(__FUNCTION__)<<"RX: "<<trans;
+        for(unsigned i=0; i<wait_states; ++i)
+            sc_core::wait(factory::get<testbench>().clk.posedge_event());
+        state.resp_cnt++;
+        return 0;
+    });
+
+    dut.rst_n.write(false);
+    sc_start(state.ResetCycles*dut.clk.period());
+    dut.rst_n.write(true);
+    sc_start(dut.clk.period());
+    dut.HSEL.write(true);
+    sc_start(dut.clk.period());
+
+    auto run1 = sc_spawn([&dut, &state](){
+        unsigned int StartAddr{0x0};
+        for(int i = 0; i < state.NumberOfIterations; ++i) {
+            tlm::scc::tlm_gp_shared_ptr trans = prepare_trans<testbench::DWIDTH>(StartAddr, state.BurstLengthByte, state.BurstSizeBytes);
+            trans->set_command(tlm::TLM_READ_COMMAND);
+            SCCDEBUG(__FUNCTION__) << "task run1, iteration " << i <<" TX: "<<*trans;
+            sc_core::sc_time d;
+            dut.isck->b_transport(*trans, d);
+            state.read_tx.first.emplace_back(trans);
+            StartAddr += state.BurstSizeBytes;
+        }
+        SCCDEBUG(__FUNCTION__) << "task run1 finished";
+    });
+    auto run2 = sc_spawn([&dut, &state](){
+        unsigned int StartAddr{0x2000};
+        for(int i = 0; i < state.NumberOfIterations; ++i) {
+            tlm::scc::tlm_gp_shared_ptr trans = prepare_trans<testbench::DWIDTH>(StartAddr, state.BurstLengthByte, state.BurstSizeBytes);
+            trans->set_command(tlm::TLM_WRITE_COMMAND);
+            randomize(*trans);
+            SCCDEBUG(__FUNCTION__) << "task run2, iteration " << i <<" TX: "<<*trans;
+            sc_core::sc_time d;
+            dut.isck->b_transport(*trans, d);
+            state.write_tx.first.emplace_back(trans);
+            StartAddr += state.BurstSizeBytes;
+        }
+        SCCDEBUG(__FUNCTION__) << "task run2 finished";
+    });
+    auto run3 = sc_spawn([&dut, &state](){
+        unsigned int StartAddr{0x1000};
+        for(int i = 0; i < state.NumberOfIterations; ++i) {
+            tlm::scc::tlm_gp_shared_ptr trans = prepare_trans<testbench::DWIDTH>(StartAddr, state.BurstLengthByte, state.BurstSizeBytes);
+            trans->set_command(tlm::TLM_READ_COMMAND);
+            SCCDEBUG(__FUNCTION__) << "task run3, iteration " << i <<" TX: "<<*trans;
+            sc_core::sc_time d;
+            dut.isck->b_transport(*trans, d);
+            state.read_tx.first.emplace_back(trans);
+            StartAddr += state.BurstSizeBytes;
+        }
+        SCCDEBUG(__FUNCTION__) << "task run3 finished";
+    });
+    auto run4 = sc_spawn([&dut, &state](){
+        unsigned int StartAddr{0x3000};
+        for(int i = 0; i < state.NumberOfIterations; ++i) {
+            tlm::scc::tlm_gp_shared_ptr trans = prepare_trans<testbench::DWIDTH>(StartAddr, state.BurstLengthByte, state.BurstSizeBytes);
+            trans->set_command(tlm::TLM_WRITE_COMMAND);
+            randomize(*trans);
+            SCCDEBUG(__FUNCTION__) << "task run4, iteration " << i <<" TX: "<<*trans;
+            sc_core::sc_time d;
+            dut.isck->b_transport(*trans, d);
+            state.write_tx.first.emplace_back(trans);
+            StartAddr += state.BurstSizeBytes;
+        }
+        SCCDEBUG(__FUNCTION__) << "task run4 finished";
+    });
+
+    unsigned cycles{0};
+    while(cycles<1000 && !(run1.terminated() && run2.terminated() && run3.terminated() && run4.terminated())){
+        sc_start(10 * dut.clk.period());
+        cycles+=10;
+    }
+    return cycles;
+}
+
+TEST_CASE("ahb_read_write", "[AHB][pin-level]") {
+    struct {
+        unsigned int ResetCycles{4};
+        unsigned int BurstLengthByte{4};
+        unsigned int BurstSizeBytes{4};
+        unsigned int NumberOfIterations{1};
+        std::pair<std::vector<tlm::scc::tlm_gp_shared_ptr>, std::vector<tlm::scc::tlm_gp_shared_ptr>> read_tx;
+        std::pair<std::vector<tlm::scc::tlm_gp_shared_ptr>, std::vector<tlm::scc::tlm_gp_shared_ptr>> write_tx;
+        unsigned resp_cnt{0};
+    } state;
+
+    auto cycles = run_scenario(state);
+
+    REQUIRE(cycles<1000);
+    REQUIRE(sc_report_handler::get_count(SC_ERROR) == 0);
+    REQUIRE(sc_report_handler::get_count(SC_WARNING) == 0);
+
+    REQUIRE(state.resp_cnt==4*state.NumberOfIterations);
+    {
+        auto& e = state.write_tx;
+        auto const& send_tx = e.first;
+        auto const& recv_tx = e.second;
+        REQUIRE(send_tx.size() == recv_tx.size());
+        for(auto i = 0; i<send_tx.size(); ++i) {
+            REQUIRE(send_tx[i]->get_response_status() == tlm::TLM_OK_RESPONSE);
+            CHECK(*send_tx[i] == *recv_tx[i]);
+        }
+    }
+    {
+        auto& e = state.read_tx;
+        auto const& send_tx = e.first;
+        auto const& recv_tx = e.second;
+        REQUIRE(send_tx.size() == recv_tx.size());
+        for(auto i = 0; i<send_tx.size(); ++i){
+            REQUIRE(send_tx[i]->get_response_status() == tlm::TLM_OK_RESPONSE);
+            CHECK(*send_tx[i] == *recv_tx[i]);
+        }
+    }
+}
+
+TEST_CASE("ahb_narrow_read_write", "[AHB][pin-level]") {
+    struct {
+        unsigned int ResetCycles{4};
+        unsigned int BurstLengthByte{1};
+        unsigned int BurstSizeBytes{1};
+        unsigned int NumberOfIterations{8};
+        std::pair<std::vector<tlm::scc::tlm_gp_shared_ptr>, std::vector<tlm::scc::tlm_gp_shared_ptr>> read_tx;
+        std::pair<std::vector<tlm::scc::tlm_gp_shared_ptr>, std::vector<tlm::scc::tlm_gp_shared_ptr>> write_tx;
+        unsigned resp_cnt{0};
+    } state;
+
+    auto cycles = run_scenario(state);
+
+    REQUIRE(cycles<1000);
+    REQUIRE(sc_report_handler::get_count(SC_ERROR) == 0);
+    REQUIRE(sc_report_handler::get_count(SC_WARNING) == 0);
+
+    REQUIRE(state.resp_cnt==4*state.NumberOfIterations);
+    {
+        auto& e = state.write_tx;
+        auto const& send_tx = e.first;
+        auto const& recv_tx = e.second;
+        REQUIRE(send_tx.size() == recv_tx.size());
+        for(auto i = 0; i<send_tx.size(); ++i)
+            CHECK(*send_tx[i] == *recv_tx[i]);
+
+    }
+    {
+        auto& e = state.read_tx;
+        auto const& send_tx = e.first;
+        auto const& recv_tx = e.second;
+        REQUIRE(send_tx.size() == recv_tx.size());
+        for(auto i = 0; i<send_tx.size(); ++i)
+            CHECK(*send_tx[i] == *recv_tx[i]);
+
+    }
+}
+
+TEST_CASE("ahb_delayed_read_write", "[AHB][pin-level]") {
+    struct {
+        unsigned int ResetCycles{4};
+        unsigned int BurstLengthByte{4};
+        unsigned int BurstSizeBytes{4};
+        unsigned int NumberOfIterations{2};
+        std::pair<std::vector<tlm::scc::tlm_gp_shared_ptr>, std::vector<tlm::scc::tlm_gp_shared_ptr>> read_tx;
+        std::pair<std::vector<tlm::scc::tlm_gp_shared_ptr>, std::vector<tlm::scc::tlm_gp_shared_ptr>> write_tx;
+        unsigned resp_cnt{0};
+    } state;
+
+    auto cycles = run_scenario(state, 1);
+
+    REQUIRE(cycles<1000);
+    REQUIRE(sc_report_handler::get_count(SC_ERROR) == 0);
+    REQUIRE(sc_report_handler::get_count(SC_WARNING) == 0);
+
+    REQUIRE(state.resp_cnt==4*state.NumberOfIterations);
+    {
+        auto& e = state.write_tx;
+        auto const& send_tx = e.first;
+        auto const& recv_tx = e.second;
+        REQUIRE(send_tx.size() == recv_tx.size());
+        for(auto i = 0; i<send_tx.size(); ++i) {
+            REQUIRE(send_tx[i]->get_response_status() == tlm::TLM_OK_RESPONSE);
+            CHECK(*send_tx[i] == *recv_tx[i]);
+        }
+    }
+    {
+        auto& e = state.read_tx;
+        auto const& send_tx = e.first;
+        auto const& recv_tx = e.second;
+        REQUIRE(send_tx.size() == recv_tx.size());
+        for(auto i = 0; i<send_tx.size(); ++i){
+            REQUIRE(send_tx[i]->get_response_status() == tlm::TLM_OK_RESPONSE);
+            CHECK(*send_tx[i] == *recv_tx[i]);
+        }
+    }
+}
+

tests/ahb_pin_level/testbench.h

@@ -0,0 +1,79 @@
+#ifndef _TESTBENCH_H_
+#define _TESTBENCH_H_
+
+#include <ahb/pin/initiator.h>
+#include <ahb/pin/target.h>
+#include <scc.h>
+
+using namespace sc_core;
+
+class testbench : public sc_core::sc_module {
+public:
+    enum { DWIDTH = 32};
+    sc_core::sc_time clk_period{10, sc_core::SC_NS};
+    sc_core::sc_clock clk{"clk", clk_period, 0.5, sc_core::SC_ZERO_TIME, true};
+    sc_core::sc_signal<bool> rst_n{"rst_n"};
+    // initiator side
+    tlm::scc::initiator_mixin<tlm::tlm_initiator_socket<DWIDTH>> isck{"isck"};
+    ahb::pin::initiator<DWIDTH> intor_bfm{"intor_bfm"};
+    // signal accurate bus
+    sc_core::sc_signal<sc_dt::sc_uint<32>> HADDR{"HADDR"};
+    sc_core::sc_signal<sc_dt::sc_uint<3>> HBURST{"HBURST"};
+    sc_core::sc_signal<bool> HMASTLOCK{"HMASTLOCK"};
+    sc_core::sc_signal<sc_dt::sc_uint<4>> HPROT{"HPROT"};
+    sc_core::sc_signal<sc_dt::sc_uint<3>> HSIZE{"HSIZE"};
+    sc_core::sc_signal<sc_dt::sc_uint<2>> HTRANS{"HTRANS"};
+    sc_core::sc_signal<sc_dt::sc_uint<DWIDTH>> HWDATA{"HWDATA"};
+    sc_core::sc_signal<bool> HWRITE{"HWRITE"};
+    sc_core::sc_signal<sc_dt::sc_uint<DWIDTH>> HRDATA{"HRDATA"};
+    sc_core::sc_signal<bool> HREADY{"HREADY"};
+    sc_core::sc_signal<bool> HRESP{"HRESP"};
+    sc_core::sc_signal<bool> HSEL{"HSEL"};
+    // target side
+    ahb::pin::target<DWIDTH, 32> tgt_bfm{"tgt_bfm"};
+    tlm::scc::target_mixin<tlm::tlm_target_socket<scc::LT>> tsck{"tsck"};
+
+public:
+    SC_HAS_PROCESS(testbench);
+    testbench(): testbench("testbench") {}
+    testbench(sc_core::sc_module_name nm)
+    : sc_core::sc_module(nm) {
+        intor_bfm.HCLK_i(clk);
+        tgt_bfm.HCLK_i(clk);
+        // bfm to signals
+        isck(intor_bfm.tsckt);
+        intor_bfm.HRESETn_i(rst_n);
+        intor_bfm.HADDR_o(HADDR);
+        intor_bfm.HBURST_o(HBURST);
+        intor_bfm.HMASTLOCK_o(HMASTLOCK);
+        intor_bfm.HPROT_o(HPROT);
+        intor_bfm.HSIZE_o(HSIZE);
+        intor_bfm.HTRANS_o(HTRANS);
+        intor_bfm.HWDATA_o(HWDATA);
+        intor_bfm.HWRITE_o(HWRITE);
+        intor_bfm.HRDATA_i(HRDATA);
+        intor_bfm.HREADY_i(HREADY);
+        intor_bfm.HRESP_i(HRESP);
+        // signals to bfm
+        tgt_bfm.HRESETn_i(rst_n);
+        tgt_bfm.HADDR_i(HADDR);
+        tgt_bfm.HBURST_i(HBURST);
+        tgt_bfm.HMASTLOCK_i(HMASTLOCK);
+        tgt_bfm.HPROT_i(HPROT);
+        tgt_bfm.HSIZE_i(HSIZE);
+        tgt_bfm.HTRANS_i(HTRANS);
+        tgt_bfm.HWDATA_i(HWDATA);
+        tgt_bfm.HWRITE_i(HWRITE);
+        tgt_bfm.HSEL_i(HSEL);
+        tgt_bfm.HRDATA_o(HRDATA);
+        tgt_bfm.HREADY_o(HREADY);
+        tgt_bfm.HRESP_o(HRESP);
+        tgt_bfm.isckt(tsck);
+    }
+
+
+    void run1() {
+    }
+};
+
+#endif // _TESTBENCH_H_

tests/axi4_pin_level/testbench.h

@@ -24,11 +24,11 @@ public:
     axi::scv::axi_recorder_module<bus_cfg::BUSWIDTH> intor_rec{"intor_rec"};
     axi::pin::axi4_initiator<bus_cfg> intor_bfm{"intor_bfm"};
     // signal accurate bus
-    axi::aw_ch<bus_cfg, axi::signal_types> aw;
+    axi::aw_axi<bus_cfg, axi::signal_types> aw;
-    axi::wdata_ch<bus_cfg, axi::signal_types> wdata;
+    axi::wdata_axi<bus_cfg, axi::signal_types> wdata;
-    axi::b_ch<bus_cfg, axi::signal_types> b;
+    axi::b_axi<bus_cfg, axi::signal_types> b;
-    axi::ar_ch<bus_cfg, axi::signal_types> ar;
+    axi::ar_axi<bus_cfg, axi::signal_types> ar;
-    axi::rresp_ch<bus_cfg, axi::signal_types> rresp;
+    axi::rresp_axi<bus_cfg, axi::signal_types> rresp;
     axi::pin::axi4_target<bus_cfg> tgt_bfm{"tgt_bfm"};
     // target side
     axi::scv::axi_recorder_module<bus_cfg::BUSWIDTH> tgt_rec{"tgt_rec"};