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extended example to demonstrate use of indexed registers

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This commit is contained in:
Eyck Jentzsch
2017-09-20 21:26:46 +02:00
parent 68a3a36d5d
commit 09aab928ba
14 changed files with 370 additions and 113 deletions
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1
examples/simple_system/CMakeLists.txt
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@@ -18,6 +18,7 @@ cmake_minimum_required (VERSION 2.8.12)
# Add executable called "simple_system" that is built from the source files
# "scv_tr_recording_example.cpp". The extensions are automatically found.
add_executable (simple_system
plic.cpp
uart.cpp
spi.cpp
gpio.cpp

9
examples/simple_system/gen/e300_plat_t.h
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@@ -1,10 +1,11 @@
#ifndef _E300_PLAT_MAP_H_
#define _E300_PLAT_MAP_H_
// need double braces, see https://stackoverflow.com/questions/6893700/how-to-construct-stdarray-object-with-initializer-list#6894191
const std::array<sysc::target_memory_map_entry<32>, 3> e300_plat_map = {{
{&i_gpio, 0x10012000, 0x1000},
{&i_uart, 0x10013000, 0x1000},
{&i_spi, 0x10014000, 0x1000}
const std::array<sysc::target_memory_map_entry<32>, 4> e300_plat_map = {{
{&i_plic, 0xc000000, 0x1000},
{&i_gpio, 0x10012000, 0x1000},
{&i_uart, 0x10013000, 0x1000},
{&i_spi, 0x10014000, 0x1000},
}};
#endif /* _E300_PLAT_MAP_H_ */

36
examples/simple_system/gen/gpio_regs.h
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@@ -28,7 +28,7 @@
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//
// Created on: Tue Sep 19 18:02:10 CEST 2017
// Created on: Wed Sep 20 11:47:24 CEST 2017
// * gpio_regs.h Author: <RDL Generator>
//
////////////////////////////////////////////////////////////////////////////////
@@ -137,23 +137,23 @@ inline sysc::gpio_regs::gpio_regs(sc_core::sc_module_name nm)
template<unsigned BUSWIDTH>
inline void sysc::gpio_regs::registerResources(sysc::tlm_target<BUSWIDTH>& target) {
target.addResource(value, 0x0UL, 0x4UL);
target.addResource(input_en, 0x4UL, 0x4UL);
target.addResource(output_en, 0x8UL, 0x4UL);
target.addResource(port, 0xcUL, 0x4UL);
target.addResource(pue, 0x10UL, 0x4UL);
target.addResource(ds, 0x14UL, 0x4UL);
target.addResource(rise_ie, 0x18UL, 0x4UL);
target.addResource(rise_ip, 0x1cUL, 0x4UL);
target.addResource(fall_ie, 0x20UL, 0x4UL);
target.addResource(fall_ip, 0x24UL, 0x4UL);
target.addResource(high_ie, 0x28UL, 0x4UL);
target.addResource(high_ip, 0x2cUL, 0x4UL);
target.addResource(low_ie, 0x30UL, 0x4UL);
target.addResource(low_ip, 0x34UL, 0x4UL);
target.addResource(iof_en, 0x38UL, 0x4UL);
target.addResource(iof_sel, 0x3cUL, 0x4UL);
target.addResource(out_xor, 0x40UL, 0x4UL);
target.addResource(value, 0x0UL);
target.addResource(input_en, 0x4UL);
target.addResource(output_en, 0x8UL);
target.addResource(port, 0xcUL);
target.addResource(pue, 0x10UL);
target.addResource(ds, 0x14UL);
target.addResource(rise_ie, 0x18UL);
target.addResource(rise_ip, 0x1cUL);
target.addResource(fall_ie, 0x20UL);
target.addResource(fall_ip, 0x24UL);
target.addResource(high_ie, 0x28UL);
target.addResource(high_ip, 0x2cUL);
target.addResource(low_ie, 0x30UL);
target.addResource(low_ip, 0x34UL);
target.addResource(iof_en, 0x38UL);
target.addResource(iof_sel, 0x3cUL);
target.addResource(out_xor, 0x40UL);
}
#endif // _GPIO_REGS_H_

104
examples/simple_system/gen/plic_regs.h Normal file
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@@ -0,0 +1,104 @@
////////////////////////////////////////////////////////////////////////////////
// Copyright (C) 2017, MINRES Technologies GmbH
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are met:
//
// 1. Redistributions of source code must retain the above copyright notice,
// this list of conditions and the following disclaimer.
//
// 2. Redistributions in binary form must reproduce the above copyright notice,
// this list of conditions and the following disclaimer in the documentation
// and/or other materials provided with the distribution.
//
// 3. Neither the name of the copyright holder nor the names of its contributors
// may be used to endorse or promote products derived from this software
// without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//
// Created on: Wed Sep 20 11:47:24 CEST 2017
// * plic_regs.h Author: <RDL Generator>
//
////////////////////////////////////////////////////////////////////////////////
#ifndef _PLIC_REGS_H_
#define _PLIC_REGS_H_
#include <sysc/utilities.h>
#include <util/bit_field.h>
#include <sysc/register.h>
#include <sysc/tlm_target.h>
namespace sysc {
class plic_regs :
public sc_core::sc_module,
public sysc::resetable
{
protected:
// storage declarations
BEGIN_BF_DECL(priority_t, uint32_t);
BF_FIELD(priority, 0, 3);
END_BF_DECL();
std::array<priority_t, 255> r_priority;
uint32_t r_pending;
uint32_t r_enabled;
BEGIN_BF_DECL(threshold_t, uint32_t);
BF_FIELD(threshold, 0, 3);
END_BF_DECL() r_threshold;
uint32_t r_claim_complete;
// register declarations
sysc::sc_register_field<priority_t, 255> priority;
sysc::sc_register<uint32_t> pending;
sysc::sc_register<uint32_t> enabled;
sysc::sc_register<threshold_t> threshold;
sysc::sc_register<uint32_t> claim_complete;
public:
plic_regs(sc_core::sc_module_name nm);
template<unsigned BUSWIDTH=32>
void registerResources(sysc::tlm_target<BUSWIDTH>& target);
};
}
//////////////////////////////////////////////////////////////////////////////
// member functions
//////////////////////////////////////////////////////////////////////////////
inline sysc::plic_regs::plic_regs(sc_core::sc_module_name nm)
: sc_core::sc_module(nm)
, NAMED(priority, r_priority, 0, *this)
, NAMED(pending, r_pending, 0, *this)
, NAMED(enabled, r_enabled, 0, *this)
, NAMED(threshold, r_threshold, 0, *this)
, NAMED(claim_complete, r_claim_complete, 0, *this)
{
}
template<unsigned BUSWIDTH>
inline void sysc::plic_regs::registerResources(sysc::tlm_target<BUSWIDTH>& target) {
target.addResource(priority, 0x4UL);
target.addResource(pending, 0x1000UL);
target.addResource(enabled, 0x2000UL);
target.addResource(threshold, 0xc200000UL);
target.addResource(claim_complete, 0xc200004UL);
}
#endif // _PLIC_REGS_H_

62
examples/simple_system/gen/spi_regs.h
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@@ -28,7 +28,7 @@
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//
// Created on: Tue Sep 19 18:02:09 CEST 2017
// Created on: Wed Sep 20 11:47:24 CEST 2017
// * spi_regs.h Author: <RDL Generator>
//
////////////////////////////////////////////////////////////////////////////////
@@ -127,22 +127,22 @@ protected:
END_BF_DECL() r_ip;
// register declarations
sysc::sc_register<typename sckdiv_t::StorageType> sckdiv;
sysc::sc_register<typename sckmode_t::StorageType> sckmode;
sysc::sc_register<sckdiv_t> sckdiv;
sysc::sc_register<sckmode_t> sckmode;
sysc::sc_register<uint32_t> csid;
sysc::sc_register<uint32_t> csdef;
sysc::sc_register<typename csmode_t::StorageType> csmode;
sysc::sc_register<typename delay0_t::StorageType> delay0;
sysc::sc_register<typename delay1_t::StorageType> delay1;
sysc::sc_register<typename fmt_t::StorageType> fmt;
sysc::sc_register<typename txdata_t::StorageType> txdata;
sysc::sc_register<typename rxdata_t::StorageType> rxdata;
sysc::sc_register<typename txmark_t::StorageType> txmark;
sysc::sc_register<typename rxmark_t::StorageType> rxmark;
sysc::sc_register<typename fctrl_t::StorageType> fctrl;
sysc::sc_register<typename ffmt_t::StorageType> ffmt;
sysc::sc_register<typename ie_t::StorageType> ie;
sysc::sc_register<typename ip_t::StorageType> ip;
sysc::sc_register<csmode_t> csmode;
sysc::sc_register<delay0_t> delay0;
sysc::sc_register<delay1_t> delay1;
sysc::sc_register<fmt_t> fmt;
sysc::sc_register<txdata_t> txdata;
sysc::sc_register<rxdata_t> rxdata;
sysc::sc_register<txmark_t> txmark;
sysc::sc_register<rxmark_t> rxmark;
sysc::sc_register<fctrl_t> fctrl;
sysc::sc_register<ffmt_t> ffmt;
sysc::sc_register<ie_t> ie;
sysc::sc_register<ip_t> ip;
public:
spi_regs(sc_core::sc_module_name nm);
@@ -178,22 +178,22 @@ inline sysc::spi_regs::spi_regs(sc_core::sc_module_name nm)
template<unsigned BUSWIDTH>
inline void sysc::spi_regs::registerResources(sysc::tlm_target<BUSWIDTH>& target) {
target.addResource(sckdiv, 0x0UL, 0x4UL);
target.addResource(sckmode, 0x4UL, 0x4UL);
target.addResource(csid, 0x10UL, 0x4UL);
target.addResource(csdef, 0x14UL, 0x4UL);
target.addResource(csmode, 0x18UL, 0x4UL);
target.addResource(delay0, 0x28UL, 0x4UL);
target.addResource(delay1, 0x2cUL, 0x4UL);
target.addResource(fmt, 0x40UL, 0x4UL);
target.addResource(txdata, 0x48UL, 0x4UL);
target.addResource(rxdata, 0x4cUL, 0x4UL);
target.addResource(txmark, 0x50UL, 0x4UL);
target.addResource(rxmark, 0x54UL, 0x4UL);
target.addResource(fctrl, 0x60UL, 0x4UL);
target.addResource(ffmt, 0x64UL, 0x4UL);
target.addResource(ie, 0x70UL, 0x4UL);
target.addResource(ip, 0x74UL, 0x4UL);
target.addResource(sckdiv, 0x0UL);
target.addResource(sckmode, 0x4UL);
target.addResource(csid, 0x10UL);
target.addResource(csdef, 0x14UL);
target.addResource(csmode, 0x18UL);
target.addResource(delay0, 0x28UL);
target.addResource(delay1, 0x2cUL);
target.addResource(fmt, 0x40UL);
target.addResource(txdata, 0x48UL);
target.addResource(rxdata, 0x4cUL);
target.addResource(txmark, 0x50UL);
target.addResource(rxmark, 0x54UL);
target.addResource(fctrl, 0x60UL);
target.addResource(ffmt, 0x64UL);
target.addResource(ie, 0x70UL);
target.addResource(ip, 0x74UL);
}
#endif // _SPI_REGS_H_

30
examples/simple_system/gen/uart_regs.h
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@@ -28,7 +28,7 @@
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//
// Created on: Tue Sep 19 18:02:09 CEST 2017
// Created on: Wed Sep 20 11:47:24 CEST 2017
// * uart_regs.h Author: <RDL Generator>
//
////////////////////////////////////////////////////////////////////////////////
@@ -87,13 +87,13 @@ protected:
END_BF_DECL() r_div;
// register declarations
sysc::sc_register<typename txdata_t::StorageType> txdata;
sysc::sc_register<typename rxdata_t::StorageType> rxdata;
sysc::sc_register<typename txctrl_t::StorageType> txctrl;
sysc::sc_register<typename rxctrl_t::StorageType> rxctrl;
sysc::sc_register<typename ie_t::StorageType> ie;
sysc::sc_register<typename ip_t::StorageType> ip;
sysc::sc_register<typename div_t::StorageType> div;
sysc::sc_register<txdata_t> txdata;
sysc::sc_register<rxdata_t> rxdata;
sysc::sc_register<txctrl_t> txctrl;
sysc::sc_register<rxctrl_t> rxctrl;
sysc::sc_register<ie_t> ie;
sysc::sc_register<ip_t> ip;
sysc::sc_register<div_t> div;
public:
uart_regs(sc_core::sc_module_name nm);
@@ -120,13 +120,13 @@ inline sysc::uart_regs::uart_regs(sc_core::sc_module_name nm)
template<unsigned BUSWIDTH>
inline void sysc::uart_regs::registerResources(sysc::tlm_target<BUSWIDTH>& target) {
target.addResource(txdata, 0x0UL, 0x4UL);
target.addResource(rxdata, 0x4UL, 0x4UL);
target.addResource(txctrl, 0x8UL, 0x4UL);
target.addResource(rxctrl, 0xcUL, 0x4UL);
target.addResource(ie, 0x10UL, 0x4UL);
target.addResource(ip, 0x14UL, 0x4UL);
target.addResource(div, 0x18UL, 0x4UL);
target.addResource(txdata, 0x0UL);
target.addResource(rxdata, 0x4UL);
target.addResource(txctrl, 0x8UL);
target.addResource(rxctrl, 0xcUL);
target.addResource(ie, 0x10UL);
target.addResource(ip, 0x14UL);
target.addResource(div, 0x18UL);
}
#endif // _UART_REGS_H_

51
examples/simple_system/plic.cpp Normal file
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@@ -0,0 +1,51 @@
////////////////////////////////////////////////////////////////////////////////
// Copyright 2017 eyck@minres.com
//
// Licensed under the Apache License, Version 2.0 (the "License"); you may not
// use this file except in compliance with the License. You may obtain a copy
// of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
// License for the specific language governing permissions and limitations under
// the License.
////////////////////////////////////////////////////////////////////////////////
#include "plic.h"
#include "gen/plic_regs.h"
#include "sysc/utilities.h"
namespace sysc {
plic::plic(sc_core::sc_module_name nm)
: sc_core::sc_module(nm)
, tlm_target<>(clk)
, NAMED(clk_i)
, NAMED(rst_i)
, NAMEDD(plic_regs, regs)
{
regs->registerResources(*this);
SC_METHOD(clock_cb);
sensitive<<clk_i;
SC_METHOD(reset_cb);
sensitive<<rst_i;
}
plic::~plic() {
}
void plic::clock_cb() {
this->clk=clk_i.read();
}
void plic::reset_cb() {
if(rst_i.read())
regs->reset_start();
else
regs->reset_stop();
}
} /* namespace sysc */

42
examples/simple_system/plic.h Normal file
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@@ -0,0 +1,42 @@
/*******************************************************************************
* Copyright 2017 eyck@minres.com
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may not
* use this file except in compliance with the License. You may obtain a copy
* of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations under
* the License.
******************************************************************************/
#ifndef _PLIC_H_
#define _PLIC_H_
#include <sysc/tlm_target.h>
namespace sysc {
class plic_regs;
class plic: public sc_core::sc_module, public tlm_target<> {
public:
SC_HAS_PROCESS(plic);
sc_core::sc_in<sc_core::sc_time> clk_i;
sc_core::sc_in<bool> rst_i;
plic(sc_core::sc_module_name nm);
virtual ~plic();
protected:
void clock_cb();
void reset_cb();
sc_core::sc_time clk;
std::unique_ptr<plic_regs> regs;
};
} /* namespace sysc */
#endif /* _PLIC_H_ */

7
examples/simple_system/simple_system.cpp
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@@ -27,28 +27,31 @@ namespace sysc {
simple_system::simple_system(sc_core::sc_module_name nm)
: sc_core::sc_module(nm)
, NAMED(i_master)
, NAMED(i_router, 3, 1)
, NAMED(i_router, 4, 1)
, NAMED(i_uart)
, NAMED(i_spi)
, NAMED(i_gpio)
, NAMED(i_plic)
, NAMED(s_clk)
, NAMED(s_rst)
{
i_master.intor(i_router.target[0]);
size_t i=0;
for(const auto& e: e300_plat_map){
i_router.initiator[i](e.target->socket);
i_router.initiator.at(i)(e.target->socket);
i_router.add_target_range(i, e.start, e.size);
i++;
}
i_uart.clk_i(s_clk);
i_spi.clk_i(s_clk);
i_gpio.clk_i(s_clk);
i_plic.clk_i(s_clk);
s_clk.write(10_ns);
i_uart.rst_i(s_rst);
i_spi.rst_i(s_rst);
i_gpio.rst_i(s_rst);
i_plic.rst_i(s_rst);
i_master.rst_i(s_rst);
SC_THREAD(gen_reset);

2
examples/simple_system/simple_system.h
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@@ -26,6 +26,7 @@
#include "uart.h"
#include "spi.h"
#include "gpio.h"
#include "plic.h"
#include "test_initiator.h"
#include <sysc/router.h>
@@ -44,6 +45,7 @@ public:
uart i_uart;
spi i_spi;
gpio i_gpio;
plic i_plic;
sc_core::sc_signal<sc_core::sc_time> s_clk;
sc_core::sc_signal<bool> s_rst;

3
examples/simple_system/test_initiator.cpp
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@@ -44,7 +44,8 @@ void test_initiator::run() {
std::array<uint8_t, 4> data;
srInfo()("group", "comm")("read access");
gp.set_command(tlm::TLM_READ_COMMAND);
gp.set_address(0x10012000);
// gp.set_address(0x10012000);
gp.set_address(0xc000004);
gp.set_data_ptr(data.data());
gp.set_data_length(data.size());
gp.set_streaming_width(4);