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SystemC-Components-Test/simple_system.txlog

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added missing sc_signal constructor call
2017-09-19 17:37:01 +02:00
scv_tr_stream (ID 1, name "i_simple_system.i_router.target_0.blocking", kind "TRANSACTOR")
scv_tr_generator (ID 2, name "read", scv_tr_stream 1,
begin_attribute (ID 0, name "start_delay", type "UNSIGNED")
end_attribute (ID 1, name "end_delay", type "UNSIGNED")
)
scv_tr_generator (ID 3, name "write", scv_tr_stream 1,
begin_attribute (ID 0, name "start_delay", type "UNSIGNED")
end_attribute (ID 1, name "end_delay", type "UNSIGNED")
)
scv_tr_generator (ID 4, name "ignore", scv_tr_stream 1,
begin_attribute (ID 0, name "start_delay", type "UNSIGNED")
end_attribute (ID 1, name "end_delay", type "UNSIGNED")
)
tx_begin 1 2 20 ns
a 0
scv_tr_stream (ID 5, name "i_simple_system.i_router.intor_0.blocking", kind "TRANSACTOR")
scv_tr_generator (ID 6, name "read", scv_tr_stream 5,
begin_attribute (ID 0, name "start_delay", type "UNSIGNED")
end_attribute (ID 1, name "end_delay", type "UNSIGNED")
)
scv_tr_generator (ID 7, name "write", scv_tr_stream 5,
begin_attribute (ID 0, name "start_delay", type "UNSIGNED")
end_attribute (ID 1, name "end_delay", type "UNSIGNED")
)
scv_tr_generator (ID 8, name "ignore", scv_tr_stream 5,
begin_attribute (ID 0, name "start_delay", type "UNSIGNED")
end_attribute (ID 1, name "end_delay", type "UNSIGNED")
)
tx_begin 2 6 20 ns
a 0
tx_relation "PRED/SUCC" 2 1
extended example to demonstrate use of indexed registers
2017-09-20 21:26:46 +02:00
scv_tr_stream (ID 9, name "i_simple_system.i_plic.socket.blocking", kind "TRANSACTOR")
added missing sc_signal constructor call
2017-09-19 17:37:01 +02:00
scv_tr_generator (ID 10, name "read", scv_tr_stream 9,
begin_attribute (ID 0, name "start_delay", type "UNSIGNED")
end_attribute (ID 1, name "end_delay", type "UNSIGNED")
)
scv_tr_generator (ID 11, name "write", scv_tr_stream 9,
begin_attribute (ID 0, name "start_delay", type "UNSIGNED")
end_attribute (ID 1, name "end_delay", type "UNSIGNED")
)
scv_tr_generator (ID 12, name "ignore", scv_tr_stream 9,
begin_attribute (ID 0, name "start_delay", type "UNSIGNED")
end_attribute (ID 1, name "end_delay", type "UNSIGNED")
)
tx_begin 3 10 20 ns
a 0
tx_relation "PRED/SUCC" 3 2
extended example to demonstrate use of indexed registers
2017-09-20 21:26:46 +02:00
tx_record_attribute 3 "trans.address" UNSIGNED = 4
added missing sc_signal constructor call
2017-09-19 17:37:01 +02:00
tx_record_attribute 3 "trans.command" ENUMERATION = "tlm::TLM_READ_COMMAND"
tx_record_attribute 3 "trans.data" POINTER = 0
tx_record_attribute 3 "trans.data_length" UNSIGNED = 4
tx_record_attribute 3 "trans.response_status" ENUMERATION = "tlm::TLM_OK_RESPONSE"
tx_record_attribute 3 "trans.dmi" BOOLEAN = false
tx_record_attribute 3 "trans.byte_enable" POINTER = 0
tx_record_attribute 3 "trans.byte_enable_length" UNSIGNED = 0
tx_record_attribute 3 "trans.streaming_width" UNSIGNED = 4
tx_record_attribute 3 "trans.gp_option" ENUMERATION = "tlm::TLM_MIN_PAYLOAD"
tx_record_attribute 3 "trans.data_value" UNSIGNED = 0
tx_end 3 10 20 ns
extended example to demonstrate use of indexed registers
2017-09-20 21:26:46 +02:00
a 10000
tx_record_attribute 2 "trans.address" UNSIGNED = 4
added missing sc_signal constructor call
2017-09-19 17:37:01 +02:00
tx_record_attribute 2 "trans.command" ENUMERATION = "tlm::TLM_READ_COMMAND"
tx_record_attribute 2 "trans.data" POINTER = 0
tx_record_attribute 2 "trans.data_length" UNSIGNED = 4
tx_record_attribute 2 "trans.response_status" ENUMERATION = "tlm::TLM_OK_RESPONSE"
tx_record_attribute 2 "trans.dmi" BOOLEAN = false
tx_record_attribute 2 "trans.byte_enable" POINTER = 0
tx_record_attribute 2 "trans.byte_enable_length" UNSIGNED = 0
tx_record_attribute 2 "trans.streaming_width" UNSIGNED = 4
tx_record_attribute 2 "trans.gp_option" ENUMERATION = "tlm::TLM_MIN_PAYLOAD"
tx_record_attribute 2 "trans.data_value" UNSIGNED = 0
tx_end 2 6 20 ns
extended example to demonstrate use of indexed registers
2017-09-20 21:26:46 +02:00
a 10000
tx_record_attribute 1 "trans.address" UNSIGNED = 201326596
added missing sc_signal constructor call
2017-09-19 17:37:01 +02:00
tx_record_attribute 1 "trans.command" ENUMERATION = "tlm::TLM_READ_COMMAND"
tx_record_attribute 1 "trans.data" POINTER = 0
tx_record_attribute 1 "trans.data_length" UNSIGNED = 4
tx_record_attribute 1 "trans.response_status" ENUMERATION = "tlm::TLM_OK_RESPONSE"
tx_record_attribute 1 "trans.dmi" BOOLEAN = false
tx_record_attribute 1 "trans.byte_enable" POINTER = 0
tx_record_attribute 1 "trans.byte_enable_length" UNSIGNED = 0
tx_record_attribute 1 "trans.streaming_width" UNSIGNED = 4
tx_record_attribute 1 "trans.gp_option" ENUMERATION = "tlm::TLM_MIN_PAYLOAD"
tx_record_attribute 1 "trans.data_value" UNSIGNED = 0
tx_end 1 2 20 ns
extended example to demonstrate use of indexed registers
2017-09-20 21:26:46 +02:00
a 10000
scv_tr_stream (ID 13, name "i_simple_system.i_plic.socket.bl_t_ann", kind "TRANSACTOR")
added missing sc_signal constructor call
2017-09-19 17:37:01 +02:00
scv_tr_generator (ID 14, name "read", scv_tr_stream 13,
begin_attribute (ID 0, name "<anonymous>", type "ENUMERATION")
end_attribute (ID 1, name "<anonymous>", type "ENUMERATION")
)
scv_tr_generator (ID 15, name "write", scv_tr_stream 13,
begin_attribute (ID 0, name "<anonymous>", type "ENUMERATION")
end_attribute (ID 1, name "<anonymous>", type "ENUMERATION")
)
scv_tr_generator (ID 16, name "ignore", scv_tr_stream 13,
begin_attribute (ID 0, name "<anonymous>", type "ENUMERATION")
end_attribute (ID 1, name "<anonymous>", type "ENUMERATION")
)
tx_begin 4 14 20 ns
a "tlm::TLM_READ_COMMAND"
extended example to demonstrate use of indexed registers
2017-09-20 21:26:46 +02:00
tx_record_attribute 4 "trans.address" UNSIGNED = 4
added missing sc_signal constructor call
2017-09-19 17:37:01 +02:00
tx_record_attribute 4 "trans.command" ENUMERATION = "tlm::TLM_READ_COMMAND"
tx_record_attribute 4 "trans.data" POINTER = 0
tx_record_attribute 4 "trans.data_length" UNSIGNED = 4
tx_record_attribute 4 "trans.response_status" ENUMERATION = "tlm::TLM_INCOMPLETE_RESPONSE"
tx_record_attribute 4 "trans.dmi" BOOLEAN = false
tx_record_attribute 4 "trans.byte_enable" POINTER = 0
tx_record_attribute 4 "trans.byte_enable_length" UNSIGNED = 0
tx_record_attribute 4 "trans.streaming_width" UNSIGNED = 4
tx_record_attribute 4 "trans.gp_option" ENUMERATION = "tlm::TLM_MIN_PAYLOAD"
tx_relation "PARENT/CHILD" 4 3
scv_tr_stream (ID 17, name "i_simple_system.i_router.intor_0.bl_t_ann", kind "TRANSACTOR")
scv_tr_generator (ID 18, name "read", scv_tr_stream 17,
begin_attribute (ID 0, name "<anonymous>", type "ENUMERATION")
end_attribute (ID 1, name "<anonymous>", type "ENUMERATION")
)
scv_tr_generator (ID 19, name "write", scv_tr_stream 17,
begin_attribute (ID 0, name "<anonymous>", type "ENUMERATION")
end_attribute (ID 1, name "<anonymous>", type "ENUMERATION")
)
scv_tr_generator (ID 20, name "ignore", scv_tr_stream 17,
begin_attribute (ID 0, name "<anonymous>", type "ENUMERATION")
end_attribute (ID 1, name "<anonymous>", type "ENUMERATION")
)
tx_begin 5 18 20 ns
a "tlm::TLM_READ_COMMAND"
extended example to demonstrate use of indexed registers
2017-09-20 21:26:46 +02:00
tx_record_attribute 5 "trans.address" UNSIGNED = 4
added missing sc_signal constructor call
2017-09-19 17:37:01 +02:00
tx_record_attribute 5 "trans.command" ENUMERATION = "tlm::TLM_READ_COMMAND"
tx_record_attribute 5 "trans.data" POINTER = 0
tx_record_attribute 5 "trans.data_length" UNSIGNED = 4
tx_record_attribute 5 "trans.response_status" ENUMERATION = "tlm::TLM_INCOMPLETE_RESPONSE"
tx_record_attribute 5 "trans.dmi" BOOLEAN = false
tx_record_attribute 5 "trans.byte_enable" POINTER = 0
tx_record_attribute 5 "trans.byte_enable_length" UNSIGNED = 0
tx_record_attribute 5 "trans.streaming_width" UNSIGNED = 4
tx_record_attribute 5 "trans.gp_option" ENUMERATION = "tlm::TLM_MIN_PAYLOAD"
tx_relation "PARENT/CHILD" 5 2
scv_tr_stream (ID 21, name "i_simple_system.i_router.target_0.bl_t_ann", kind "TRANSACTOR")
scv_tr_generator (ID 22, name "read", scv_tr_stream 21,
begin_attribute (ID 0, name "<anonymous>", type "ENUMERATION")
end_attribute (ID 1, name "<anonymous>", type "ENUMERATION")
)
scv_tr_generator (ID 23, name "write", scv_tr_stream 21,
begin_attribute (ID 0, name "<anonymous>", type "ENUMERATION")
end_attribute (ID 1, name "<anonymous>", type "ENUMERATION")
)
scv_tr_generator (ID 24, name "ignore", scv_tr_stream 21,
begin_attribute (ID 0, name "<anonymous>", type "ENUMERATION")
end_attribute (ID 1, name "<anonymous>", type "ENUMERATION")
)
tx_begin 6 22 20 ns
a "tlm::TLM_READ_COMMAND"
extended example to demonstrate use of indexed registers
2017-09-20 21:26:46 +02:00
tx_record_attribute 6 "trans.address" UNSIGNED = 201326596
added missing sc_signal constructor call
2017-09-19 17:37:01 +02:00
tx_record_attribute 6 "trans.command" ENUMERATION = "tlm::TLM_READ_COMMAND"
tx_record_attribute 6 "trans.data" POINTER = 0
tx_record_attribute 6 "trans.data_length" UNSIGNED = 4
tx_record_attribute 6 "trans.response_status" ENUMERATION = "tlm::TLM_INCOMPLETE_RESPONSE"
tx_record_attribute 6 "trans.dmi" BOOLEAN = false
tx_record_attribute 6 "trans.byte_enable" POINTER = 0
tx_record_attribute 6 "trans.byte_enable_length" UNSIGNED = 0
tx_record_attribute 6 "trans.streaming_width" UNSIGNED = 4
tx_record_attribute 6 "trans.gp_option" ENUMERATION = "tlm::TLM_MIN_PAYLOAD"
tx_relation "PARENT/CHILD" 6 1
extended example to demonstrate use of indexed registers
2017-09-20 21:26:46 +02:00
tx_end 6 22 30 ns
a "tlm::TLM_INCOMPLETE_RESPONSE"
tx_end 5 18 30 ns
a "tlm::TLM_INCOMPLETE_RESPONSE"
tx_end 4 14 30 ns
added missing sc_signal constructor call
2017-09-19 17:37:01 +02:00
a "tlm::TLM_INCOMPLETE_RESPONSE"
tx_begin 7 3 30 ns
extended example to demonstrate use of indexed registers
2017-09-20 21:26:46 +02:00
a 10000
scv_tr_stream (ID 25, name "i_simple_system.i_router.intor_1.blocking", kind "TRANSACTOR")
scv_tr_generator (ID 26, name "read", scv_tr_stream 25,
begin_attribute (ID 0, name "start_delay", type "UNSIGNED")
end_attribute (ID 1, name "end_delay", type "UNSIGNED")
)
scv_tr_generator (ID 27, name "write", scv_tr_stream 25,
begin_attribute (ID 0, name "start_delay", type "UNSIGNED")
end_attribute (ID 1, name "end_delay", type "UNSIGNED")
)
scv_tr_generator (ID 28, name "ignore", scv_tr_stream 25,
begin_attribute (ID 0, name "start_delay", type "UNSIGNED")
end_attribute (ID 1, name "end_delay", type "UNSIGNED")
)
tx_begin 8 27 30 ns
a 10000
added missing sc_signal constructor call
2017-09-19 17:37:01 +02:00
tx_relation "PRED/SUCC" 8 7
extended example to demonstrate use of indexed registers
2017-09-20 21:26:46 +02:00
scv_tr_stream (ID 29, name "i_simple_system.i_gpio.socket.blocking", kind "TRANSACTOR")
scv_tr_generator (ID 30, name "read", scv_tr_stream 29,
begin_attribute (ID 0, name "start_delay", type "UNSIGNED")
end_attribute (ID 1, name "end_delay", type "UNSIGNED")
)
scv_tr_generator (ID 31, name "write", scv_tr_stream 29,
begin_attribute (ID 0, name "start_delay", type "UNSIGNED")
end_attribute (ID 1, name "end_delay", type "UNSIGNED")
)
scv_tr_generator (ID 32, name "ignore", scv_tr_stream 29,
begin_attribute (ID 0, name "start_delay", type "UNSIGNED")
end_attribute (ID 1, name "end_delay", type "UNSIGNED")
)
tx_begin 9 31 30 ns
a 10000
added missing sc_signal constructor call
2017-09-19 17:37:01 +02:00
tx_relation "PRED/SUCC" 9 8
tx_record_attribute 9 "trans.address" UNSIGNED = 0
tx_record_attribute 9 "trans.command" ENUMERATION = "tlm::TLM_WRITE_COMMAND"
tx_record_attribute 9 "trans.data" POINTER = 0
tx_record_attribute 9 "trans.data_length" UNSIGNED = 4
tx_record_attribute 9 "trans.response_status" ENUMERATION = "tlm::TLM_OK_RESPONSE"
tx_record_attribute 9 "trans.dmi" BOOLEAN = false
tx_record_attribute 9 "trans.byte_enable" POINTER = 0
tx_record_attribute 9 "trans.byte_enable_length" UNSIGNED = 0
tx_record_attribute 9 "trans.streaming_width" UNSIGNED = 4
tx_record_attribute 9 "trans.gp_option" ENUMERATION = "tlm::TLM_MIN_PAYLOAD"
tx_record_attribute 9 "trans.data_value" UNSIGNED = 165
extended example to demonstrate use of indexed registers
2017-09-20 21:26:46 +02:00
tx_end 9 31 30 ns
a 10000
added missing sc_signal constructor call
2017-09-19 17:37:01 +02:00
tx_record_attribute 8 "trans.address" UNSIGNED = 0
tx_record_attribute 8 "trans.command" ENUMERATION = "tlm::TLM_WRITE_COMMAND"
tx_record_attribute 8 "trans.data" POINTER = 0
tx_record_attribute 8 "trans.data_length" UNSIGNED = 4
tx_record_attribute 8 "trans.response_status" ENUMERATION = "tlm::TLM_OK_RESPONSE"
tx_record_attribute 8 "trans.dmi" BOOLEAN = false
tx_record_attribute 8 "trans.byte_enable" POINTER = 0
tx_record_attribute 8 "trans.byte_enable_length" UNSIGNED = 0
tx_record_attribute 8 "trans.streaming_width" UNSIGNED = 4
tx_record_attribute 8 "trans.gp_option" ENUMERATION = "tlm::TLM_MIN_PAYLOAD"
tx_record_attribute 8 "trans.data_value" UNSIGNED = 165
extended example to demonstrate use of indexed registers
2017-09-20 21:26:46 +02:00
tx_end 8 27 30 ns
a 10000
added missing sc_signal constructor call
2017-09-19 17:37:01 +02:00
tx_record_attribute 7 "trans.address" UNSIGNED = 268509184
tx_record_attribute 7 "trans.command" ENUMERATION = "tlm::TLM_WRITE_COMMAND"
tx_record_attribute 7 "trans.data" POINTER = 0
tx_record_attribute 7 "trans.data_length" UNSIGNED = 4
tx_record_attribute 7 "trans.response_status" ENUMERATION = "tlm::TLM_OK_RESPONSE"
tx_record_attribute 7 "trans.dmi" BOOLEAN = false
tx_record_attribute 7 "trans.byte_enable" POINTER = 0
tx_record_attribute 7 "trans.byte_enable_length" UNSIGNED = 0
tx_record_attribute 7 "trans.streaming_width" UNSIGNED = 4
tx_record_attribute 7 "trans.gp_option" ENUMERATION = "tlm::TLM_MIN_PAYLOAD"
tx_record_attribute 7 "trans.data_value" UNSIGNED = 165
tx_end 7 3 30 ns
extended example to demonstrate use of indexed registers
2017-09-20 21:26:46 +02:00
a 10000
tx_begin 10 23 40 ns
added missing sc_signal constructor call
2017-09-19 17:37:01 +02:00
a "tlm::TLM_WRITE_COMMAND"
extended example to demonstrate use of indexed registers
2017-09-20 21:26:46 +02:00
tx_record_attribute 10 "trans.address" UNSIGNED = 268509184
added missing sc_signal constructor call
2017-09-19 17:37:01 +02:00
tx_record_attribute 10 "trans.command" ENUMERATION = "tlm::TLM_WRITE_COMMAND"
tx_record_attribute 10 "trans.data" POINTER = 0
tx_record_attribute 10 "trans.data_length" UNSIGNED = 4
tx_record_attribute 10 "trans.response_status" ENUMERATION = "tlm::TLM_OK_RESPONSE"
tx_record_attribute 10 "trans.dmi" BOOLEAN = false
tx_record_attribute 10 "trans.byte_enable" POINTER = 0
tx_record_attribute 10 "trans.byte_enable_length" UNSIGNED = 0
tx_record_attribute 10 "trans.streaming_width" UNSIGNED = 4
tx_record_attribute 10 "trans.gp_option" ENUMERATION = "tlm::TLM_MIN_PAYLOAD"
extended example to demonstrate use of indexed registers
2017-09-20 21:26:46 +02:00
tx_relation "PARENT/CHILD" 10 7
tx_end 10 23 40 ns
added missing sc_signal constructor call
2017-09-19 17:37:01 +02:00
a "tlm::TLM_OK_RESPONSE"
extended example to demonstrate use of indexed registers
2017-09-20 21:26:46 +02:00
scv_tr_stream (ID 33, name "i_simple_system.i_gpio.socket.bl_t_ann", kind "TRANSACTOR")
scv_tr_generator (ID 34, name "read", scv_tr_stream 33,
begin_attribute (ID 0, name "<anonymous>", type "ENUMERATION")
end_attribute (ID 1, name "<anonymous>", type "ENUMERATION")
)
scv_tr_generator (ID 35, name "write", scv_tr_stream 33,
begin_attribute (ID 0, name "<anonymous>", type "ENUMERATION")
end_attribute (ID 1, name "<anonymous>", type "ENUMERATION")
)
scv_tr_generator (ID 36, name "ignore", scv_tr_stream 33,
begin_attribute (ID 0, name "<anonymous>", type "ENUMERATION")
end_attribute (ID 1, name "<anonymous>", type "ENUMERATION")
)
tx_begin 11 35 40 ns
added missing sc_signal constructor call
2017-09-19 17:37:01 +02:00
a "tlm::TLM_WRITE_COMMAND"
tx_record_attribute 11 "trans.address" UNSIGNED = 0
tx_record_attribute 11 "trans.command" ENUMERATION = "tlm::TLM_WRITE_COMMAND"
tx_record_attribute 11 "trans.data" POINTER = 0
tx_record_attribute 11 "trans.data_length" UNSIGNED = 4
tx_record_attribute 11 "trans.response_status" ENUMERATION = "tlm::TLM_OK_RESPONSE"
tx_record_attribute 11 "trans.dmi" BOOLEAN = false
tx_record_attribute 11 "trans.byte_enable" POINTER = 0
tx_record_attribute 11 "trans.byte_enable_length" UNSIGNED = 0
tx_record_attribute 11 "trans.streaming_width" UNSIGNED = 4
tx_record_attribute 11 "trans.gp_option" ENUMERATION = "tlm::TLM_MIN_PAYLOAD"
extended example to demonstrate use of indexed registers
2017-09-20 21:26:46 +02:00
tx_relation "PARENT/CHILD" 11 9
tx_end 11 35 40 ns
added missing sc_signal constructor call
2017-09-19 17:37:01 +02:00
a "tlm::TLM_OK_RESPONSE"
extended example to demonstrate use of indexed registers
2017-09-20 21:26:46 +02:00
scv_tr_stream (ID 37, name "i_simple_system.i_router.intor_1.bl_t_ann", kind "TRANSACTOR")
scv_tr_generator (ID 38, name "read", scv_tr_stream 37,
begin_attribute (ID 0, name "<anonymous>", type "ENUMERATION")
end_attribute (ID 1, name "<anonymous>", type "ENUMERATION")
)
scv_tr_generator (ID 39, name "write", scv_tr_stream 37,
begin_attribute (ID 0, name "<anonymous>", type "ENUMERATION")
end_attribute (ID 1, name "<anonymous>", type "ENUMERATION")
)
scv_tr_generator (ID 40, name "ignore", scv_tr_stream 37,
begin_attribute (ID 0, name "<anonymous>", type "ENUMERATION")
end_attribute (ID 1, name "<anonymous>", type "ENUMERATION")
)
tx_begin 12 39 40 ns
added missing sc_signal constructor call
2017-09-19 17:37:01 +02:00
a "tlm::TLM_WRITE_COMMAND"
extended example to demonstrate use of indexed registers
2017-09-20 21:26:46 +02:00
tx_record_attribute 12 "trans.address" UNSIGNED = 0
added missing sc_signal constructor call
2017-09-19 17:37:01 +02:00
tx_record_attribute 12 "trans.command" ENUMERATION = "tlm::TLM_WRITE_COMMAND"
tx_record_attribute 12 "trans.data" POINTER = 0
tx_record_attribute 12 "trans.data_length" UNSIGNED = 4
tx_record_attribute 12 "trans.response_status" ENUMERATION = "tlm::TLM_OK_RESPONSE"
tx_record_attribute 12 "trans.dmi" BOOLEAN = false
tx_record_attribute 12 "trans.byte_enable" POINTER = 0
tx_record_attribute 12 "trans.byte_enable_length" UNSIGNED = 0
tx_record_attribute 12 "trans.streaming_width" UNSIGNED = 4
tx_record_attribute 12 "trans.gp_option" ENUMERATION = "tlm::TLM_MIN_PAYLOAD"
extended example to demonstrate use of indexed registers
2017-09-20 21:26:46 +02:00
tx_relation "PARENT/CHILD" 12 8
tx_end 12 39 40 ns
added missing sc_signal constructor call
2017-09-19 17:37:01 +02:00
a "tlm::TLM_OK_RESPONSE"