Added structural description
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@ -13,3 +13,6 @@ STDCXX=11 MAKE_NPROCS=32 pip install --verbose --force-reinstall --ignore-instal
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pip install conan
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```
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## TODO
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* pythonize `sc_module` with iteration protocol (`__next__` and `StopIteration` exception)
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@ -111,8 +111,7 @@ def _pythonizor(klass, name):
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# install the pythonizor as a callback on namespace 'Math' (default is the global namespace)
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cppyy.py.add_pythonization(_pythonizor, 'sc_core')
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# reflection methods
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def get_members(sc_object):
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def is_cpp_data_type(name, module):
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81
pysysc/structural.py
Normal file
81
pysysc/structural.py
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@ -0,0 +1,81 @@
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'''
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Created on 02.01.2019
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@author: eyck
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'''
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from cppyy import gbl as cpp
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from builtins import getattr
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import re
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class Module(object):
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'''
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classdocs
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'''
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def __init__(self, clazz):
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self.cppclazz=clazz
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self.instance=None
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def __getattr__(self, attr):
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if self.instance is None:
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raise AttributeError
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return getattr(self.instance, attr)
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def create(self, name):
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self.instance = self.cppclazz(cpp.sc_core.sc_module_name(str(name)))
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return self
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class Signal(object):
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'''
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classdocs
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'''
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_sc_inout_re = re.compile(r'^sc_core::sc_(?:_in)?out<(.*)>$')
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_sc_port_re = re.compile(r'^sc_core::sc_port<[^<]*<(.*)>>$')
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def __init__(self, name=None):
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self.name=name
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self.source=None
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self.targets=[]
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self.signal=None
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self.sig_data_type=None
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def src(self, module_port):
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self.source=module_port
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port_class_name=type(module_port).__cppname__
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match = self._sc_inout_re.match(port_class_name)
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if match:
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self.sig_data_type=match.group(1)
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else:
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match = self._sc_port_re.match(port_class_name)
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if match:
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self.sig_data_type=match.group(1)
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if self.sig_data_type is None:
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raise AttributeError;
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py_dt_name=self.sig_data_type.replace("::", ".").replace("<", "[").replace(">", "]")
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self.signal = eval("cpp.sc_core.sc_signal[cpp.%s](self.name)" % py_dt_name)
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module_port.bind(self.signal)
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return self
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def sink(self, module_port):
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self.targets.append(module_port)
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module_port.bind(self.signal)
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return self
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class Connection(object):
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'''
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classdocs
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'''
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def __init__(self):
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self.source=None
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self.targets=[]
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def src(self, module_port):
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self.source=module_port
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return self
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def sink(self, module_port):
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self.targets.append(module_port)
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self.source.bind(module_port)
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return self
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4
setup.py
4
setup.py
@ -12,9 +12,9 @@ setup(name='PySysC',
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long_description=readme(),
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classifiers=[
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'Development Status :: 3 - Alpha',
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'License :: OSI Approved :: Apache 2.0 License',
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'License :: OSI Approved :: Apache Software License',
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'Programming Language :: Python :: 3.6',
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'Topic :: Engineering :: Simulation'
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'Topic :: Scientific/Engineering :: Electronic Design Automation (EDA)'
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],
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keywords='SystemC simulation',
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url='https://git.minres.com/SystemC/PySysC',
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@ -22,6 +22,25 @@ intors = scpy.get_inititator_sockets(initiator)
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tgts = scpy.get_target_sockets(initiator)
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childs = scpy.get_submodules(initiator)
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cppyy.cppdef("""
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class my_module: public sc_core::sc_module {
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public:
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sc_core::sc_out<sc_dt::sc_uint<32>> port;
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my_module(sc_core::sc_module_name nm):sc_core::sc_module(nm), port("port"){}
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};
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void bind_port(sc_core::sc_signal<sc_dt::sc_uint<32>>& s, sc_core::sc_out<sc_dt::sc_uint<32>>& p){p(s);}
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""")
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class MyMod(cpp.sc_core.sc_module):
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def __init__(self, name):
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cpp.sc_core.sc_module.sc_module()
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mod = cpp.my_module(cpp.sc_core.sc_module_name("module"))
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sig = cpp.sc_core.sc_signal[cpp.sc_dt.sc_uint[32]]("signal")
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mod.port(sig)
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mod2 = MyMod("Blah")
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initiator.socket.bind(router.target_socket)
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for idx,m in enumerate(memories):
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router.initiator_socket.at(idx).bind(m.socket)
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