mirror of
https://github.com/riscv-software-src/opensbi.git
synced 2025-08-24 15:31:22 +01:00
fbb4a52330
This patch remove hard-coding of payload location in fw_payload.elf.ldS by adding compile-time option FW_PAYLOAD_OFFSET. With the new compile-time option, payload will be placed at PLAT_TEXT_START + FW_PAYLOAD_OFFSET address. Signed-off-by: Anup Patel <anup.patel@wdc.com>
RISC-V Open Source Supervisor Binary Interface (OpenSBI)
The RISC-V Supervisor Binary Interface (SBI) is a recommended interface between:
- platform specific firmware running in M-mode and bootloader running in S-mode
- platform specific firmware running in M-mode and general purpose operating system running in S-mode
- hypervisor runnng in HS-mode and general purpose operating system running in VS-mode.
The RISC-V SBI spec is maintained as independent project by RISC-V Foundation at https://github.com/riscv/riscv-sbi-doc
The RISC-V OpenSBI project aims to provides an open-source and extensible implementation of the SBI spec. This project can be easily extended by RISC-V platform or RISC-V System-on-Chip vendors.
How to Build?
Below are the steps to cross-compile and install RISC-V OpenSBI:
-
Setup build environment $ CROSS_COMPILE=riscv64-unknown-linux-gnu-
-
Build sources $ make PLAT=<platform_name> OR $ make PLAT=<platform_name> O=<build_directory>
-
Install blobs $ make PLAT=<platform_name> install OR $ make PLAT=<platform_name> I=<install_directory> install