mirror of
https://github.com/riscv-software-src/opensbi.git
synced 2026-09-08 18:21:29 +01:00
Ben Zong-You Xie
e01bd7926b
An IPI wakes a hart from light sleep and, once MSIP is kept as an SMU wakeup event, from deep sleep too. Drop the WAKEUP_CMD path and the boot state, hart type and sleep type conditions that selected it. Signed-off-by: Ben Zong-You Xie <ben717@andestech.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20260728081041.2724668-6-ben717@andestech.com Signed-off-by: Anup Patel <anup@brainfault.org>
120 lines
3.1 KiB
C
120 lines
3.1 KiB
C
/*
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* SPDX-License-Identifier: BSD-2-Clause
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*
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* Copyright (c) 2025 Andes Technology Corporation
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*/
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#include <andes/andes.h>
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#include <sbi/riscv_asm.h>
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#include <sbi/sbi_console.h>
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#include <sbi/sbi_domain.h>
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#include <sbi/sbi_error.h>
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#include <sbi/sbi_ecall_interface.h>
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#include <sbi/sbi_hart.h>
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#include <sbi/sbi_system.h>
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#include <sbi_utils/cache/fdt_cmo_helper.h>
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#include <sbi_utils/fdt/fdt_driver.h>
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#include <sbi_utils/fdt/fdt_helper.h>
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#include <sbi_utils/hsm/fdt_hsm_andes_atcsmu.h>
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static int check_secondary_harts_sleep(u32 hartid, bool deep_sleep)
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{
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const struct sbi_domain *dom = &root;
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unsigned long i;
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u32 target;
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/* Ensure the secondary harts entering the corresponding sleep state */
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sbi_hartmask_for_each_hartindex(i, dom->possible_harts) {
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target = sbi_hartindex_to_hartid(i);
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if (target != hartid && !atcsmu_pcs_is_sleep(target, deep_sleep))
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return SBI_EFAIL;
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}
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return SBI_OK;
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}
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static int ae350_system_suspend_check(u32 sleep_type)
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{
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return (sleep_type == SBI_SUSP_SLEEP_TYPE_SUSPEND ||
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sleep_type == SBI_SUSP_AE350_LIGHT_SLEEP) ? SBI_OK : SBI_EINVAL;
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}
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static int ae350_system_suspend(u32 sleep_type, unsigned long addr)
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{
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u32 hartid = current_hartid();
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int rc;
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/* Prevent the core leaving the WFI mode unexpectedly */
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csr_write(CSR_MIE, 0);
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/* SMU wakes the primary hart on RTC alarm / UART2 */
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atcsmu_set_wakeup_events(PCS_WAKEUP_RTC_ALARM_MASK | PCS_WAKEUP_UART2_MASK, hartid);
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if (sleep_type == SBI_SUSP_AE350_LIGHT_SLEEP) {
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rc = check_secondary_harts_sleep(hartid, false);
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if (rc)
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return rc;
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/* Clock-gated only: enable SEI to resume past the WFI */
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csr_set(CSR_MIE, MIP_SEIP);
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atcsmu_set_command(LIGHT_SLEEP_CMD, hartid);
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} else if (sleep_type == SBI_SUSP_SLEEP_TYPE_SUSPEND) {
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rc = check_secondary_harts_sleep(hartid, true);
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if (rc)
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return rc;
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atcsmu_set_command(DEEP_SLEEP_CMD, hartid);
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rc = atcsmu_set_reset_vector((ulong)ae350_enable_coherency_warmboot, hartid);
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if (rc)
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return rc;
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ae350_non_ret_save(sbi_scratch_thishart_ptr());
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fdt_cmo_llc_enable(false);
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rc = fdt_cmo_llc_flush_all();
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if (rc)
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return rc;
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}
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ae350_disable_coherency();
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wfi();
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/* Light sleep resumes here */
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ae350_enable_coherency();
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return SBI_OK;
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}
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static void ae350_system_resume(void)
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{
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u32 hartid = current_hartid();
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u32 sleep_type = atcsmu_get_sleep_type(hartid);
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if (sleep_type == SBI_SUSP_SLEEP_TYPE_SUSPEND) {
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fdt_cmo_llc_enable(true);
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ae350_non_ret_restore(sbi_scratch_thishart_ptr());
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}
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}
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static struct sbi_system_suspend_device suspend_andes_atcsmu = {
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.name = "andes_atcsmu",
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.system_suspend_check = ae350_system_suspend_check,
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.system_suspend = ae350_system_suspend,
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.system_resume = ae350_system_resume,
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};
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static int suspend_andes_atcsmu_probe(const void *fdt, int nodeoff, const struct fdt_match *match)
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{
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sbi_system_suspend_set_device(&suspend_andes_atcsmu);
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return 0;
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}
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static const struct fdt_match suspend_andes_atcsmu_match[] = {
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{ .compatible = "andestech,atcsmu-sys" },
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{ },
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};
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const struct fdt_driver fdt_suspend_andes_atcsmu = {
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.match_table = suspend_andes_atcsmu_match,
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.init = suspend_andes_atcsmu_probe,
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};
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