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https://github.com/riscv-software-src/opensbi.git
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c69c159bd0
In the multi-cluster system each cluster has its own CM (Coherency Manager). Every CM has its "global" memory address where it is accessible from any bus master. Initially, all CMs accessible from the local cluster using same "local" address. Transactions by local address are not routed through system bus and thus are faster. Remap CM in every cluster to the local address matching its global address. Then, every CM is always accessed using same address, but when transaction initiated from the local cluster it is routed internally. This removes need for 2 PMP regions covering local address access. CM accessor functions simplified because there's no need to detect whether transaction is local or global Access timer always in cluster 0 Signed-off-by: Vladimir Kondratiev <vladimir.kondratiev@mobileye.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20260223-for-upstream-eyeq7h-v3-7-621d004d1a21@mobileye.com Signed-off-by: Anup Patel <anup@brainfault.org>
307 lines
8.1 KiB
C
307 lines
8.1 KiB
C
/*
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* SPDX-License-Identifier: BSD-2-Clause
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*
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* Copyright (c) 2025 MIPS
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*
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*/
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#include <platform_override.h>
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#include <sbi/riscv_barrier.h>
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#include <sbi/riscv_io.h>
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#include <sbi/sbi_domain.h>
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#include <sbi/sbi_error.h>
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#include <sbi/sbi_hsm.h>
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#include <sbi/sbi_timer.h>
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#include <sbi/riscv_io.h>
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#include <sbi_utils/fdt/fdt_helper.h>
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#include <mips/p8700.h>
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#include <mips/mips-cm.h>
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extern void mips_warm_boot(void);
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#define MMIO_BASE 0x00000000
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#define MMIO_SIZE 0x80000000
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/* FIXME! Please change GLOBAL_CM_BASE for your platform */
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long GLOBAL_CM_BASE[CLUSTERS_IN_PLATFORM] = {CM_BASE};
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static void mips_p8700_pmp_set(unsigned int n, unsigned long flags,
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unsigned long prot, unsigned long addr,
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unsigned long log2len)
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{
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int pmacfg_csr, pmacfg_shift;
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unsigned long cfgmask;
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unsigned long pmacfg, cca;
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pmacfg_csr = (CSR_MIPSPMACFG0 + (n >> 2)) & ~1;
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pmacfg_shift = (n & 7) << 3;
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cfgmask = ~(0xffUL << pmacfg_shift);
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/* Read pmacfg to change cacheability */
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pmacfg = (csr_read_num(pmacfg_csr) & cfgmask);
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cca = (flags & SBI_DOMAIN_MEMREGION_MMIO) ? CCA_CACHE_DISABLE :
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CCA_CACHE_ENABLE | PMA_SPECULATION;
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pmacfg |= ((cca << pmacfg_shift) & ~cfgmask);
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csr_write_num(pmacfg_csr, pmacfg);
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}
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static void power_up_other_cluster(u32 hartid)
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{
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unsigned int cl = cpu_cluster(hartid);
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/* remap local cluster address to its global address */
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writeq(GLOBAL_CM_BASE[cl], (void*)GLOBAL_CM_BASE[cl] + GCR_BASE_OFFSET);
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wmb();
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/* Power up CM in cluster */
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write_cpc_pwrup_ctl(hartid, 1);
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/* Wait for the CM to start up */
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for (int i = 100; i > 0; i--) {
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u32 stat = read_cpc_cm_stat_conf(hartid);
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stat = EXT(stat, CPC_Cx_STAT_CONF_SEQ_STATE);
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if (stat == CPC_Cx_STAT_CONF_SEQ_STATE_U5)
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return;
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cpu_relax();
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}
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sbi_printf("ERROR: Fail to power up cluster %u\n", cl);
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}
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struct mips_boot_params {
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u32 hartid;
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u32 target_state;
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};
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static bool mips_hart_reached_state(void *arg)
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{
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struct mips_boot_params *p = arg;
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u32 stat = read_cpc_co_stat_conf(p->hartid);
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stat = EXT(stat, CPC_Cx_STAT_CONF_SEQ_STATE);
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return stat == p->target_state;
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}
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static int mips_hart_start(u32 hartid, ulong saddr)
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{
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/* Hart 0 is the boot hart, and we don't use the CPC cmd to start. */
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if (hartid == 0)
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return SBI_ENOTSUPP;
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/* Change reset base to mips_warm_boot */
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write_gcr_co_reset_base(hartid, (unsigned long)mips_warm_boot);
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if (cpu_hart(hartid) == 0) {
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unsigned int const timeout_ms = 10;
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bool booted;
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struct mips_boot_params p = {
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.hartid = hartid,
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.target_state = CPC_Cx_STAT_CONF_SEQ_STATE_U6,
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};
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/* Ensure its coherency is disabled */
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write_gcr_co_coherence(hartid, 0);
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/* Start cluster cl core co hart 0 */
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write_cpc_co_vp_run(hartid, 1 << cpu_hart(hartid));
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/* Reset cluster cl core co hart 0 */
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write_cpc_co_cmd(hartid, CPC_Cx_CMD_RESET);
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booted = sbi_timer_waitms_until(mips_hart_reached_state, &p, timeout_ms);
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if (!booted) {
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sbi_printf("ERROR: failed to boot hart 0x%x in %d ms\n",
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hartid, timeout_ms);
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return -SBI_ETIMEDOUT;
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}
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} else {
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write_cpc_co_vp_run(hartid, 1 << cpu_hart(hartid));
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}
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return 0;
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}
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static int mips_hart_stop()
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{
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u32 hartid = current_hartid();
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/* Hart 0 is the boot hart, and we don't use the CPC cmd to stop. */
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if (hartid == 0)
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return SBI_ENOTSUPP;
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write_cpc_co_vp_stop(hartid, 1 << cpu_hart(hartid));
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return 0;
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}
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static const struct sbi_hsm_device mips_hsm = {
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.name = "mips_hsm",
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.hart_start = mips_hart_start,
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.hart_stop = mips_hart_stop,
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};
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static int mips_p8700_final_init(bool cold_boot)
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{
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if (cold_boot)
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sbi_hsm_set_device(&mips_hsm);
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return generic_final_init(cold_boot);
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}
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static int mips_p8700_early_init(bool cold_boot)
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{
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int rc;
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int i;
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rc = generic_early_init(cold_boot);
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if (rc)
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return rc;
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if (!cold_boot)
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return 0;
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sbi_dprintf("Remap Cluster %d CM 0x%lx -> 0x%lx\n", 0,
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readq((void*)GLOBAL_CM_BASE[0] + GCR_BASE_OFFSET),
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GLOBAL_CM_BASE[0]);
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writeq(GLOBAL_CM_BASE[0], (void*)GLOBAL_CM_BASE[0] + GCR_BASE_OFFSET);
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wmb();
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/* Power up other clusters in the platform. */
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for (i = 1; i < CLUSTERS_IN_PLATFORM; i++) {
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power_up_other_cluster(i << NEW_CLUSTER_SHIFT);
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}
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/**
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* Memory map:
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* 0x00_20080000 0x00_20100000 M:IRW- S:---- GCR local access (CM_BASE)
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* 0x00_40000000 0x00_70000000 M:IRW- S:IRW- Peripherals
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* 0x00_48700000 0x00_48780000 M:IRW- S:---- GCR cluster 0
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* 0x00_67480000 0x00_67500000 M:IRW- S:---- GCR cluster 1
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* 0x00_67500000 0x00_67580000 M:IRW- S:---- GCR cluster 2
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* 0x00_67800000 0x00_67900000 M:IRW- S:---- Ncore
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* 0x00_70000000 0x00_80000000 M:---- S:IRW- PCI32 BARs, NOT USED - 32-bit mode
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* 0x01_00000000 0x08_00000000 M:---- S:IRW- PCI64 BARs, NOT USED - PCI2PCI
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* 0x08_00000000 0x10_00000000 M:---- S:-RWX DDR64
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* 0x10_00000000 0x20_00000000 M:---- S:IRW- PCI64 BARs
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*/
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for (i = 0; i < CLUSTERS_IN_PLATFORM; i++) {
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unsigned long cm_base = GLOBAL_CM_BASE[i];
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/* CM and MTIMER */
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rc = sbi_domain_root_add_memrange(cm_base, SIZE_FOR_CPC_MTIME,
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SIZE_FOR_CPC_MTIME,
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(SBI_DOMAIN_MEMREGION_MMIO |
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SBI_DOMAIN_MEMREGION_M_READABLE |
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SBI_DOMAIN_MEMREGION_M_WRITABLE));
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if (rc)
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return rc;
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/* For the APLIC and ACLINT m-mode region */
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rc = sbi_domain_root_add_memrange(cm_base + AIA_OFFSET, SIZE_FOR_AIA_M_MODE,
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SIZE_FOR_AIA_M_MODE,
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(SBI_DOMAIN_MEMREGION_MMIO |
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SBI_DOMAIN_MEMREGION_M_READABLE |
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SBI_DOMAIN_MEMREGION_M_WRITABLE));
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if (rc)
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return rc;
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}
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/* the rest of MMIO - shared with S-mode */
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rc = sbi_domain_root_add_memrange(MMIO_BASE, MMIO_SIZE, MMIO_SIZE,
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SBI_DOMAIN_MEMREGION_MMIO |
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SBI_DOMAIN_MEMREGION_SHARED_SURW_MRW);
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if (rc)
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return rc;
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/* PCIE BARs - MMIO S-mode */
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rc = sbi_domain_root_add_memrange(0x1000000000UL, 0x1000000000UL, 0x1000000000UL,
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SBI_DOMAIN_MEMREGION_MMIO |
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SBI_DOMAIN_MEMREGION_SU_READABLE |
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SBI_DOMAIN_MEMREGION_SU_WRITABLE);
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return 0;
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}
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static int mips_p8700_nascent_init(void)
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{
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u64 hartid = current_hartid();
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int cl = cpu_cluster(hartid);
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u64 cm_base = GLOBAL_CM_BASE[cl];
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int i;
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/* Coherence enable for every core */
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if (cpu_hart(hartid) == 0) {
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cm_base += (cpu_core(hartid) << CM_BASE_CORE_SHIFT);
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__raw_writeq(GCR_CORE_COH_EN_EN,
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(void *)(cm_base + GCR_OFF_LOCAL +
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GCR_CORE_COH_EN));
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mb();
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}
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/* Set up pmp for DRAM */
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csr_write(CSR_PMPADDR14, DRAM_PMP_ADDR);
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/* All from 0x0 */
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csr_write(CSR_PMPADDR15, 0x1fffffffffffffff);
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csr_write(CSR_PMPCFG2, ((PMP_A_NAPOT|PMP_R|PMP_W|PMP_X)<<56)|
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((PMP_A_NAPOT|PMP_R|PMP_W|PMP_X)<<48));
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/* Set cacheable for pmp6, uncacheable for pmp7 */
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csr_write(CSR_MIPSPMACFG2, ((u64)CCA_CACHE_DISABLE << 56)|
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((u64)CCA_CACHE_ENABLE << 48));
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/* Reset pmpcfg0 */
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csr_write(CSR_PMPCFG0, 0);
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/* Reset pmacfg0 */
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csr_write(CSR_MIPSPMACFG0, 0);
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mb();
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/* Per cluster set up */
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if (cpu_core(hartid) == 0 && cpu_hart(hartid) == 0) {
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/* Enable L2 prefetch */
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__raw_writel(0xfffff110,
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(void *)(cm_base + L2_PFT_CONTROL_OFFSET));
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__raw_writel(0x15ff,
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(void *)(cm_base + L2_PFT_CONTROL_B_OFFSET));
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}
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/* Per core set up */
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if (cpu_hart(hartid) == 0) {
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/* Enable load pair, store pair, and HTW */
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csr_clear(CSR_MIPSCONFIG7, (1<<12)|(1<<13)|(1<<7));
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/* Disable noRFO, misaligned load/store */
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csr_set(CSR_MIPSCONFIG7, (1<<25)|(1<<9));
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/* Enable L1-D$ Prefetch */
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csr_write(CSR_MIPSCONFIG11, 0xff);
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for (i = 0; i < 8; i++) {
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csr_set(CSR_MIPSCONFIG8, 4 + 0x100 * i);
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csr_set(CSR_MIPSCONFIG9, 8);
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mb();
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RISCV_FENCE_I;
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}
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}
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/* Per hart set up */
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/* Enable AMO and RDTIME illegal instruction exceptions. */
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csr_set(CSR_MIPSCONFIG6, (1<<2)|(1<<1));
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return 0;
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}
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static int mips_p8700_platform_init(const void *fdt, int nodeoff, const struct fdt_match *match)
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{
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generic_platform_ops.early_init = mips_p8700_early_init;
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generic_platform_ops.final_init = mips_p8700_final_init;
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generic_platform_ops.nascent_init = mips_p8700_nascent_init;
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generic_platform_ops.pmp_set = mips_p8700_pmp_set;
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return 0;
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}
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static const struct fdt_match mips_p8700_match[] = {
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{ .compatible = "mips,p8700" },
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{ },
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};
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const struct fdt_driver mips_p8700 = {
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.match_table = mips_p8700_match,
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.init = mips_p8700_platform_init,
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};
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