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c69c159bd0
In the multi-cluster system each cluster has its own CM (Coherency Manager). Every CM has its "global" memory address where it is accessible from any bus master. Initially, all CMs accessible from the local cluster using same "local" address. Transactions by local address are not routed through system bus and thus are faster. Remap CM in every cluster to the local address matching its global address. Then, every CM is always accessed using same address, but when transaction initiated from the local cluster it is routed internally. This removes need for 2 PMP regions covering local address access. CM accessor functions simplified because there's no need to detect whether transaction is local or global Access timer always in cluster 0 Signed-off-by: Vladimir Kondratiev <vladimir.kondratiev@mobileye.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20260223-for-upstream-eyeq7h-v3-7-621d004d1a21@mobileye.com Signed-off-by: Anup Patel <anup@brainfault.org>
83 lines
2.4 KiB
C
83 lines
2.4 KiB
C
/*
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* SPDX-License-Identifier: BSD-2-Clause
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*
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* Copyright (c) 2025 MIPS
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*
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*/
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#ifndef __MIPS_CM_H__
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#define __MIPS_CM_H__
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#include <mips/p8700.h>
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#include <sbi/sbi_console.h>
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/* Define 1 to print out CM read and write info */
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#define DEBUG_CM 0
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extern long GLOBAL_CM_BASE[];
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#define CPS_ACCESSOR_R(unit, sz, off, name) \
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static inline u##sz read_##unit##_##name(u32 hartid) \
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{ \
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u##sz value; \
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int cl = cpu_cluster(hartid); \
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int co = cpu_core(hartid); \
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long cmd_reg = GLOBAL_CM_BASE[cl] + (co << CM_BASE_CORE_SHIFT) \
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+ off; \
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if (DEBUG_CM) \
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sbi_printf("CM_READ%d(0x%lx) ...\n", sz, cmd_reg); \
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if (sz == 32) \
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asm volatile("lw %0,0(%1)":"=r"(value):"r"(cmd_reg)); \
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else if (sz == 64) \
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asm volatile("ld %0,0(%1)":"=r"(value):"r"(cmd_reg)); \
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asm volatile("fence"); \
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if (DEBUG_CM) \
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sbi_printf("CM_READ%d(0x%lx) -> 0x%lx\n", sz, cmd_reg, (unsigned long)value); \
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return value; \
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}
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#define CPS_ACCESSOR_W(unit, sz, off, name) \
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static inline void write_##unit##_##name(u32 hartid, u##sz value) \
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{ \
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int cl = cpu_cluster(hartid); \
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int co = cpu_core(hartid); \
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long cmd_reg = GLOBAL_CM_BASE[cl] + (co << CM_BASE_CORE_SHIFT) \
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+ off; \
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if (DEBUG_CM) \
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sbi_printf("CM_WRITE%d(0x%lx, 0x%lx)\n", sz, \
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cmd_reg, (unsigned long)value); \
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if (sz == 32) \
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asm volatile("sw %0,0(%1)"::"r"(value),"r"(cmd_reg)); \
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else if (sz == 64) \
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asm volatile("sd %0,0(%1)"::"r"(value),"r"(cmd_reg)); \
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asm volatile("fence"); \
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}
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#define CPS_ACCESSOR_RW(unit, sz, off, name) \
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CPS_ACCESSOR_R(unit, sz, off, name) \
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CPS_ACCESSOR_W(unit, sz, off, name)
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#define CPC_CX_ACCESSOR_RW(sz, off, name) \
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CPS_ACCESSOR_RW(cpc, sz, CPC_OFFSET + CPC_OFF_LOCAL + (off), co_##name)
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#define GCR_CX_ACCESSOR_RW(sz, off, name) \
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CPS_ACCESSOR_RW(gcr, sz, GCR_OFF_LOCAL + (off), co_##name)
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GCR_CX_ACCESSOR_RW(64, cpu_hart(hartid) << CM_BASE_HART_SHIFT, reset_base)
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GCR_CX_ACCESSOR_RW(32, GCR_CORE_COH_EN, coherence)
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GCR_CX_ACCESSOR_RW(64, GCR_BASE_OFFSET, base)
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CPC_CX_ACCESSOR_RW(32, CPC_Cx_VP_RUN, vp_run)
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CPC_CX_ACCESSOR_RW(32, CPC_Cx_VP_STOP, vp_stop)
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CPC_CX_ACCESSOR_RW(32, CPC_Cx_CMD, cmd)
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CPC_CX_ACCESSOR_RW(32, CPC_Cx_STAT_CONF, stat_conf)
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#define CPC_ACCESSOR_RW(sz, off, name) \
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CPS_ACCESSOR_RW(cpc, sz, CPC_OFFSET + (off), name)
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CPC_ACCESSOR_RW(32, CPC_PWRUP_CTL, pwrup_ctl)
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CPC_ACCESSOR_RW(32, CPC_CM_STAT_CONF, cm_stat_conf)
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#endif
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