mirror of
https://github.com/riscv-software-src/opensbi.git
synced 2026-03-21 03:21:45 +00:00
b5348006e9
The addw opcode is only defined in RV64, which produces 32-bit results.
On RV32, the default add opcode already produces 32-bit results.
Fixes: 995f226f3f ("lib: Emit lr and sc instructions based on -march flags")
Signed-off-by: Marti Alonso <martialonso11@gmail.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
Link: https://lore.kernel.org/r/20260301205421.2074835-1-martialonso11@gmail.com
Signed-off-by: Anup Patel <anup@brainfault.org>
91 lines
1.9 KiB
C
91 lines
1.9 KiB
C
/*
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* SPDX-License-Identifier: BSD-2-Clause
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*
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* Copyright (c) 2019 Western Digital Corporation or its affiliates.
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* Copyright (c) 2021 Christoph Müllner <cmuellner@linux.com>
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*/
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#include <sbi/riscv_barrier.h>
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#include <sbi/riscv_locks.h>
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static inline bool spin_lock_unlocked(spinlock_t lock)
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{
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return lock.owner == lock.next;
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}
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bool spin_lock_check(spinlock_t *lock)
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{
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RISCV_FENCE(r, rw);
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return !spin_lock_unlocked(*lock);
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}
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bool spin_trylock(spinlock_t *lock)
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{
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unsigned long inc = 1u << TICKET_SHIFT;
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unsigned long mask = 0xffffu << TICKET_SHIFT;
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u32 l0, tmp1, tmp2;
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__asm__ __volatile__(
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/* Get the current lock counters. */
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"1: lr.w.aq %0, %3\n"
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" slli %2, %0, %6\n"
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" and %2, %2, %5\n"
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" and %1, %0, %5\n"
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/* Is the lock free right now? */
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" bne %1, %2, 2f\n"
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" add %0, %0, %4\n"
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/* Acquire the lock. */
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" sc.w.rl %0, %0, %3\n"
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" bnez %0, 1b\n"
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"2:"
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: "=&r"(l0), "=&r"(tmp1), "=&r"(tmp2), "+A"(*lock)
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: "r"(inc), "r"(mask), "I"(TICKET_SHIFT)
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: "memory");
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return l0 == 0;
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}
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void spin_lock(spinlock_t *lock)
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{
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unsigned long inc = 1u << TICKET_SHIFT;
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unsigned long mask = 0xffffu;
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u32 l0, tmp1, tmp2;
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__asm__ __volatile__(
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/* Atomically increment the next ticket. */
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#if defined(__riscv_atomic) || defined(__riscv_zaamo)
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" amoadd.w.aqrl %0, %4, %3\n"
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#elif defined(__riscv_zalrsc)
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"3: lr.w.aqrl %0, %3\n"
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#if __riscv_xlen == 64
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" addw %1, %0, %4\n"
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#elif __riscv_xlen == 32
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" add %1, %0, %4\n"
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#endif
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" sc.w.aqrl %1, %1, %3\n"
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" bnez %1, 3b\n"
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#else
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#error "need A or Zaamo or Zalrsc"
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#endif
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/* Did we get the lock? */
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" srli %1, %0, %6\n"
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" and %1, %1, %5\n"
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"1: and %2, %0, %5\n"
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" beq %1, %2, 2f\n"
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/* If not, then spin on the lock. */
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" lw %0, %3\n"
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RISCV_ACQUIRE_BARRIER
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" j 1b\n"
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"2:"
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: "=&r"(l0), "=&r"(tmp1), "=&r"(tmp2), "+A"(*lock)
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: "r"(inc), "r"(mask), "I"(TICKET_SHIFT)
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: "memory");
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}
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void spin_unlock(spinlock_t *lock)
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{
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__smp_store_release(&lock->owner, lock->owner + 1);
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}
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