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a3aeef7c14
There's high-resolution (1GHz) timer found in the p8700 cluster. This timer used for precise time measurement by platform specific software. Synchronize this proprietary timers to reference in cluster 0. Procedure borrowed from the aclint mtimer. Signed-off-by: Vladimir Kondratiev <vladimir.kondratiev@mobileye.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20260223-for-upstream-eyeq7h-v3-17-621d004d1a21@mobileye.com Signed-off-by: Anup Patel <anup@brainfault.org>
188 lines
5.1 KiB
C
188 lines
5.1 KiB
C
/*
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* SPDX-License-Identifier: BSD-2-Clause
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*
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* Copyright (c) 2025 MIPS
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*
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*/
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#ifndef __P8700_H__
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#define __P8700_H__
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/** Coherence manager information
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*
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* @num_cm: Number of coherence manager
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* @gcr_base: Array of base address of the CM
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*/
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struct p8700_cm_info {
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unsigned int num_cm;
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unsigned long *gcr_base;
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};
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extern const struct p8700_cm_info *p8700_cm_info;
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/* PMA */
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#define CSR_MIPSPMACFG0 0x7e0
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#define CSR_MIPSPMACFG1 0x7e1
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#define CSR_MIPSPMACFG2 0x7e2
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#define CSR_MIPSPMACFG3 0x7e3
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#define CSR_MIPSPMACFG4 0x7e4
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#define CSR_MIPSPMACFG5 0x7e5
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#define CSR_MIPSPMACFG6 0x7e6
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#define CSR_MIPSPMACFG7 0x7e7
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#define CSR_MIPSPMACFG8 0x7e8
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#define CSR_MIPSPMACFG9 0x7e9
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#define CSR_MIPSPMACFG10 0x7ea
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#define CSR_MIPSPMACFG11 0x7eb
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#define CSR_MIPSPMACFG12 0x7ec
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#define CSR_MIPSPMACFG13 0x7ed
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#define CSR_MIPSPMACFG14 0x7ee
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#define CSR_MIPSPMACFG15 0x7ef
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/* MIPS CCA */
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#define CCA_CACHE_ENABLE 0
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#define CCA_CACHE_DISABLE 2
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#define PMA_SPECULATION (1 << 3)
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/* MIPS CSR */
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#define CSR_MIPSTVEC 0x7c0
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#define CSR_MIPSCONFIG0 0x7d0
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#define CSR_MIPSCONFIG1 0x7d1
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#define CSR_MIPSCONFIG2 0x7d2
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#define CSR_MIPSCONFIG3 0x7d3
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#define CSR_MIPSCONFIG4 0x7d4
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#define CSR_MIPSCONFIG5 0x7d5
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#define CSR_MIPSCONFIG6 0x7d6
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#define CSR_MIPSCONFIG7 0x7d7
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#define CSR_MIPSCONFIG8 0x7d8
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#define CSR_MIPSCONFIG9 0x7d9
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#define CSR_MIPSCONFIG10 0x7da
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#define CSR_MIPSCONFIG11 0x7db
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#define MIPSCONFIG1_L2C BIT(31)
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#define MIPSCONFIG1_IS GENMASK(24,22)
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#define MIPSCONFIG1_IL GENMASK(21,19)
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#define MIPSCONFIG1_IA GENMASK(18,16)
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#define MIPSCONFIG1_DS GENMASK(15,13)
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#define MIPSCONFIG1_DL GENMASK(12,10)
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#define MIPSCONFIG1_DA GENMASK(9,7)
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#define MIPSCONFIG5_MTW 4
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/* mhartID structure */
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#define P8700_HARTID_CLUSTER GENMASK(19, 16)
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#define P8700_HARTID_CORE GENMASK(11, 4)
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#define P8700_HARTID_HART GENMASK(3, 0)
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#define cpu_cluster(i) EXTRACT_FIELD(i, P8700_HARTID_CLUSTER)
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#define cpu_core(i) EXTRACT_FIELD(i, P8700_HARTID_CORE)
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#define cpu_hart(i) EXTRACT_FIELD(i, P8700_HARTID_HART)
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#define CPC_OFFSET (0x8000)
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#define SIZE_FOR_CPC_MTIME 0x10000 /* The size must be 2^order */
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#define AIA_OFFSET (0x40000)
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#define SIZE_FOR_AIA_M_MODE 0x20000 /* The size must be 2^order */
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#define P8700_ALIGN 0x10000
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#define CM_BASE_HART_SHIFT 3
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#define CM_BASE_CORE_SHIFT 8
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#define CM_BASE_CLUSTER_SHIFT 19
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/* GCR Block offsets */
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#define GCR_OFF_LOCAL 0x2000
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#define GCR_GLOBAL_CONFIG 0x0000
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#define GCR_GC_NUM_CORES GENMASK(7, 0)
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#define GCR_GC_NUM_IOCUS GENMASK(11, 8)
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#define GCR_GC_NUM_MMIOS GENMASK(19, 16)
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#define GCR_GC_NUM_AUX GENMASK(22, 20)
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#define GCR_GC_NUM_CLUSTERS GENMASK(29, 23)
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#define GCR_GC_HAS_ITU BIT(31)
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#define GCR_GC_CL_ID GENMASK(39, 32)
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#define GCR_GC_HAS_DBU BIT(40)
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#define GCR_GC_NOC GENMASK(43, 41)
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#define GCR_BASE_OFFSET 0x0008
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#define GCR_CORE_COH_EN 0x00f8
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#define GCR_CORE_COH_EN_EN (0x1 << 0)
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#define L2_PFT_CONTROL_OFFSET 0x0300
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#define L2_PFT_CONTROL_B_OFFSET 0x0308
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#define GCR_L2_CONFIG 0x0130
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#define GCR_L2_ASSOC GENMASK(7, 0)
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#define GCR_L2_LINE_SIZE GENMASK(11, 8)
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#define GCR_L2_SET_SIZE GENMASK(15, 12)
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#define GCR_L2_BYPASS BIT(20)
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#define GCR_L2_COP_DATA_ECC_WE BIT(24)
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#define GCR_L2_COP_TAG_ECC_WE BIT(25)
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#define GCR_L2_COP_LRU_WE BIT(26)
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#define GCR_L2_REG_EXISTS BIT(31)
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#define GCR_L2_TAG_ADDR 0x0600
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#define GCR_L2_TAG_STATE 0x0608
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#define GCR_L2_DATA 0x0610
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#define GCR_L2_ECC 0x0618
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#define GCR_L2SM_COP 0x0620
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#define GCR_L2SM_COP_CMD GENMASK(1, 0)
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#define L2SM_COP_CMD_NOP 0
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#define L2SM_COP_CMD_START 1
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#define L2SM_COP_CMD_ABORT 3
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#define GCR_L2SM_COP_TYPE GENMASK(4, 2)
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#define L2SM_COP_TYPE_IDX_WBINV 0
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#define L2SM_COP_TYPE_IDX_STORETAG 1
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#define L2SM_COP_TYPE_IDX_STORETAGDATA 2
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#define L2SM_COP_TYPE_HIT_INV 4
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#define L2SM_COP_TYPE_HIT_WBINV 5
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#define L2SM_COP_TYPE_HIT_WB 6
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#define L2SM_COP_TYPE_FETCHLOCK 7
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#define GCR_L2SM_COP_RUNNING BIT(5)
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#define GCR_L2SM_COP_RESULT GENMASK(8, 6)
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#define L2SM_COP_RESULT_DONTCARE 0
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#define L2SM_COP_RESULT_DONE_OK 1
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#define L2SM_COP_RESULT_DONE_ERROR 2
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#define L2SM_COP_RESULT_ABORT_OK 3
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#define L2SM_COP_RESULT_ABORT_ERROR 4
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#define GCR_L2SM_COP_PRESENT BIT(31)
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/* CPC Block offsets */
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#define CPC_PWRUP_CTL 0x0030
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#define CPC_HRTIME 0x0090
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#define CPC_CM_STAT_CONF 0x1008
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#define CPC_OFF_LOCAL 0x2000
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#define CPC_Cx_VP_STOP 0x0020
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#define CPC_Cx_VP_RUN 0x0028
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#define CPC_Cx_CMD 0x0000
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#define CPC_Cx_CMD_PWRUP 0x3
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#define CPC_Cx_CMD_RESET 0x4
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#define CPC_Cx_STAT_CONF 0x0008
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#define CPC_Cx_STAT_CONF_SEQ_STATE GENMASK(22, 19)
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#define CPC_Cx_STAT_CONF_SEQ_STATE_U5 6
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#define CPC_Cx_STAT_CONF_SEQ_STATE_U6 7
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extern const struct p8700_cm_info *p8700_cm_info;
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void mips_p8700_pmp_set(unsigned int n, unsigned long flags,
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unsigned long prot, unsigned long addr,
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unsigned long log2len);
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void mips_p8700_power_up_other_cluster(u32 hartid);
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int mips_p8700_hart_start(u32 hartid, ulong saddr);
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int mips_p8700_hart_stop(void);
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struct p8700_cache_info {
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u32 line;
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u32 assoc_ways;
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u32 sets;
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};
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void mips_p8700_cache_info(struct p8700_cache_info *l1d, struct p8700_cache_info *l1i,
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struct p8700_cache_info *l2);
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int mips_p8700_add_memranges(void);
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struct fdt_match;
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int mips_p8700_platform_init(const void *fdt, int nodeoff, const struct fdt_match *match);
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#endif
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