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https://github.com/riscv-software-src/opensbi.git
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9ffacc8ae1
Refactor ATCSMU (System Management Unit) support by moving it from a system utility into a dedicated FDT-based HSM driver. Key changes include: - Moving the functions in lib/utils/sys/atcsmu.c into the new HSM driver - Moving hart start and stop operations on AE350 platform into the new HSM driver - Converting the assembly-based functions in sleep.S to C code for the readability - Updating the ATCWDT200 driver Signed-off-by: Ben Zong-You Xie <ben717@andestech.com> Signed-off-by: Leo Yu-Chi Liang <ycliang@andestech.com> Link: https://lore.kernel.org/r/20251229071914.1451587-2-ben717@andestech.com Signed-off-by: Anup Patel <anup@brainfault.org>
133 lines
3.7 KiB
C
133 lines
3.7 KiB
C
/* SPDX-License-Identifier: BSD-2-Clause */
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/*
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* Copyright (C) 2024 Andes Technology Corporation
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*/
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#ifndef _RISCV_ANDES_H
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#define _RISCV_ANDES_H
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#include <sbi/sbi_bitops.h>
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#include <sbi/sbi_scratch.h>
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/* Memory and Miscellaneous Registers */
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#define CSR_MCACHE_CTL 0x7ca
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#define CSR_MCCTLCOMMAND 0x7cc
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/* Configuration Control & Status Registers */
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#define CSR_MICM_CFG 0xfc0
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#define CSR_MDCM_CFG 0xfc1
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#define CSR_MMSC_CFG 0xfc2
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/* Machine Trap Related Registers */
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#define CSR_MSLIDELEG 0x7d5
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/* Counter Related Registers */
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#define CSR_MCOUNTERWEN 0x7ce
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#define CSR_MCOUNTERINTEN 0x7cf
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#define CSR_MCOUNTERMASK_M 0x7d1
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#define CSR_MCOUNTERMASK_S 0x7d2
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#define CSR_MCOUNTERMASK_U 0x7d3
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#define CSR_MCOUNTEROVF 0x7d4
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/* PMA Related Registers */
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#define CSR_PMACFG0 0xbc0
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#define CSR_PMAADDR0 0xbd0
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#define MICM_CFG_ISZ_OFFSET 6
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#define MICM_CFG_ISZ_MASK (7 << MICM_CFG_ISZ_OFFSET)
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#define MDCM_CFG_DSZ_OFFSET 6
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#define MDCM_CFG_DSZ_MASK (7 << MDCM_CFG_DSZ_OFFSET)
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#define MMSC_CFG_CCTLCSR_OFFSET 16
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#define MMSC_CFG_CCTLCSR_MASK (1 << MMSC_CFG_CCTLCSR_OFFSET)
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#define MMSC_CFG_PPMA_OFFSET 30
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#define MMSC_CFG_PPMA_MASK (1 << MMSC_CFG_PPMA_OFFSET)
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#define MMSC_IOCP_OFFSET 47
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#define MMSC_IOCP_MASK (1ULL << MMSC_IOCP_OFFSET)
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#define MCACHE_CTL_IC_EN_MASK BIT(0)
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#define MCACHE_CTL_DC_EN_MASK BIT(1)
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#define MCACHE_CTL_CCTL_SUEN_OFFSET 8
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#define MCACHE_CTL_CCTL_SUEN_MASK (1 << MCACHE_CTL_CCTL_SUEN_OFFSET)
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#define MCACHE_CTL_DC_COHEN_MASK BIT(19)
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#define MCACHE_CTL_DC_COHSTA_MASK BIT(20)
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/* Performance monitor */
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#define MMSC_CFG_PMNDS_MASK (1 << 15)
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#define MIP_PMOVI (1 << 18)
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/* Cache control commands */
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#define MCCTLCOMMAND_L1D_WBINVAL_ALL 6
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/* AE350 platform specific sleep types */
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#define SBI_SUSP_AE350_LIGHT_SLEEP SBI_SUSP_PLATFORM_SLEEP_START
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#ifndef __ASSEMBLER__
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#define is_andes(series) \
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({ \
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char value = csr_read(CSR_MARCHID) & 0xff; \
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(series) == (value >> 4) * 10 + (value & 0x0f); \
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})
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#define has_andes_pmu() \
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({ \
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(((csr_read(CSR_MMSC_CFG) & \
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MMSC_CFG_PMNDS_MASK) \
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&& misa_extension('S')) ? true : false); \
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})
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#endif /* __ASSEMBLER__ */
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void ae350_enable_coherency_warmboot(void);
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/*
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* On Andes 4X-series CPUs, disabling the L1 data cache causes the CPU to fetch
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* data directly from RAM. However, L1 cache flushes write data back to the
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* Last Level Cache (LLC). This discrepancy can lead to return address
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* corruption on the stack. To prevent this, the following functions must
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* be inlined.
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*/
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static inline void ae350_disable_coherency(void)
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{
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/*
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* To disable cache coherency of a core in AE350 platform, follow below steps:
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*
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* 1) Disable I/D-Cache
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* 2) Write back and invalidate D-Cache
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* 3) Disable D-Cache coherency
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* 4) Wait for D-Cache disengaged from the coherence management
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*/
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csr_clear(CSR_MCACHE_CTL, MCACHE_CTL_IC_EN_MASK | MCACHE_CTL_DC_EN_MASK);
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csr_write(CSR_MCCTLCOMMAND, MCCTLCOMMAND_L1D_WBINVAL_ALL);
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csr_clear(CSR_MCACHE_CTL, MCACHE_CTL_DC_COHEN_MASK);
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while (csr_read(CSR_MCACHE_CTL) & MCACHE_CTL_DC_COHSTA_MASK)
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;
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}
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static inline void ae350_enable_coherency(void)
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{
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/*
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* To enable cache coherency of a core in AE350 platform, follow below steps:
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*
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* 1) Enable D-Cache coherency
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* 2) Wait for D-Cache engaging in the coherence management
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* 3) Enable I/D-Cache
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*/
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csr_set(CSR_MCACHE_CTL, MCACHE_CTL_DC_COHEN_MASK);
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/*
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* mcache_ctl.DC_COHEN is hardwired to 0 if there is no coherence
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* manager. In such situation, just enable the I/D-Cache to prevent
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* permanently being stuck in the while loop.
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*/
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if (csr_read(CSR_MCACHE_CTL) & MCACHE_CTL_DC_COHEN_MASK)
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while (!(csr_read(CSR_MCACHE_CTL) & MCACHE_CTL_DC_COHSTA_MASK))
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;
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csr_set(CSR_MCACHE_CTL, MCACHE_CTL_IC_EN_MASK | MCACHE_CTL_DC_EN_MASK);
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}
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#endif /* _RISCV_ANDES_H */
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