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Bo Gan
7bff4e529e
During warm reset, my EIC770X/Hifive Premier P550 can sometimes
encounter memory corruption issue crashing Linux boot. Currently the
issue is mitigated by having a sbi_printf before writing to the reset
register. I analyzed the issue further since then. From the SoC
datasheet[1], it's recommended to implement power-down flow as:
a. Designate a primary core, and let it broadcast requests to other
cores to execute a CEASE insn. Primary core also notifies an
"Externel Agent" to start monitoring.
b. Primary core waits for other cores to CEASE before it CEASEs.
c. "External Agent" waits for primary core to CEASE before resets
the Core Complex.
It's possible that EIC770X can trigger undefined behavior if the core
complex is reset while the harts are actively running. The sbi_printf
in the reset handler effectively hides the problem by delaying the
reset -- by the time sbi_printf finishes, all other harts will have
already landed in the loop in sbi_hsm_hart_wait(), which parks the hart.
Without the sbi_printf, I confirmed that other harts haven't reached
sbi_hsm_hart_wait yet before current hart resets the SoC. (by debugging)
To safely reset, and inspired by the datasheet, the warm reset logic
in eic770x.c now use the current hart as both primary core and the
"External Agent", and other harts as secondary cores. It leverages
the HSM framework and a new eic770x_hsm device to CEASE other harts,
and wait for them to CEASE before resets the SoC. with the sbi_printf
before reset removed, and this logic in place, stress test shows that
the memory corruption issue no longer occurs.
The new eic770x_hsm device is only used for the reset-CEASE logic at
the moment, and may be extended to a fully functional HSM device in
the future.
[1] https://github.com/eswincomputing/EIC7700X-SoC-Technical-Reference-Manual
Fixes: e5797e0688 ("platform: generic: eswin: add EIC7700")
Signed-off-by: Bo Gan <ganboing@gmail.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
Link: https://lore.kernel.org/r/20260605075708.96-3-ganboing@gmail.com
Signed-off-by: Anup Patel <anup@brainfault.org>
121 lines
2.9 KiB
C
121 lines
2.9 KiB
C
/*
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* SPDX-License-Identifier: BSD-2-Clause
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*
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* Copyright (c) 2025 Bo Gan <ganboing@gmail.com>
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*
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*/
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#include <sbi/riscv_io.h>
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#include <sbi/sbi_string.h>
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#include <sbi/sbi_system.h>
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#include <sbi/sbi_hart.h>
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#include <sbi/sbi_ecall_interface.h>
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#include <sbi_utils/serial/uart8250.h>
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#include <sbi_utils/hsm/fdt_hsm_sifive_inst.h>
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#include <eswin/eic770x.h>
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#include <eswin/hfp.h>
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/* HFP -> HiFive Premier P550 */
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#define HFP_MCU_UART_PORT 2
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#define HFP_MCU_UART_BAUDRATE 115200
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static unsigned long eic770x_sysclk_rate(void)
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{
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/* syscfg clock is a mux of 24Mhz xtal clock and spll0_fout3/divisor */
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uint32_t syscfg_clk = readl_relaxed((void*)EIC770X_SYSCRG_SYSCLK);
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if (EIC770X_SYSCLK_SEL(syscfg_clk))
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return EIC770X_XTAL_CLK_RATE;
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return EIC770X_SPLL0_OUT3_RATE / EIC770X_SYSCLK_DIV(syscfg_clk);
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}
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static void eic770x_enable_uart_clk(unsigned port)
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{
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uint32_t lsp_clk_en = readl_relaxed((void*)EIC770X_SYSCRG_LSPCLK0);
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lsp_clk_en |= EIC770X_UART_CLK_BIT(port);
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writel(lsp_clk_en, (void*)EIC770X_SYSCRG_LSPCLK0);
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}
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static void hfp_send_bmc_msg(uint8_t type, uint8_t cmd,
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const uint8_t *data, uint8_t len)
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{
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unsigned long sysclk_rate;
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struct uart8250_device uart_dev;
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union {
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struct hfp_bmc_message msg;
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char as_char[sizeof(struct hfp_bmc_message)];
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} xmit = {{
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.header_magic = MAGIC_HEADER,
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.type = type,
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.cmd = cmd,
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.data_len = len,
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.tail_magic = MAGIC_TAIL,
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}};
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/**
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* Re-initialize UART.
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* S-mode OS may have changed the clock frequency of syscfg clock
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* which is the clock of all low speed peripherals, including UARTs.
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* S-mode OS may also have disabled the UART2 clock via clock gate.
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* (lsp_clk_en0 bit 17-21 controls UART0-4). Thus, we re-calculate
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* the clock rate, enable UART clock, and re-initialize UART.
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*/
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sysclk_rate = eic770x_sysclk_rate();
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eic770x_enable_uart_clk(HFP_MCU_UART_PORT);
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uart8250_device_init(&uart_dev,
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EIC770X_UART(HFP_MCU_UART_PORT),
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sysclk_rate,
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HFP_MCU_UART_BAUDRATE,
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EIC770X_UART_REG_SHIFT,
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EIC770X_UART_REG_WIDTH,
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0, 0);
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sbi_memcpy(&xmit.msg.data, data, len);
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hfp_bmc_checksum_msg(&xmit.msg);
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for (unsigned int i = 0; i < sizeof(xmit.as_char); i++)
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uart8250_device_putc(&uart_dev, xmit.as_char[i]);
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}
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static int hfp_system_reset_check(u32 type, u32 reason)
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{
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switch (type) {
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case SBI_SRST_RESET_TYPE_COLD_REBOOT:
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case SBI_SRST_RESET_TYPE_SHUTDOWN:
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return 255;
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default:
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return 0;
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}
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}
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static void hfp_system_reset(u32 type, u32 reason)
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{
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eic770x_cease_other_harts();
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switch (type) {
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case SBI_SRST_RESET_TYPE_SHUTDOWN:
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hfp_send_bmc_msg(HFP_MSG_NOTIFY, HFP_CMD_POWER_OFF,
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NULL, 0);
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break;
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case SBI_SRST_RESET_TYPE_COLD_REBOOT:
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hfp_send_bmc_msg(HFP_MSG_NOTIFY, HFP_CMD_RESTART,
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NULL, 0);
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break;
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}
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sifive_cease();
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}
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static struct sbi_system_reset_device hfp_reset = {
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.name = "hfp_reset",
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.system_reset_check = hfp_system_reset_check,
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.system_reset = hfp_system_reset,
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};
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const struct eic770x_board_override hfp_override = {
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.reset_dev = &hfp_reset,
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};
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