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https://github.com/riscv-software-src/opensbi.git
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bdec423074
Reserve memory regions for CPU clusters according to P8700 cluster memory layout. There's a set of components in the CPU cluster according to [1] [1] https://mips.com/wp-content/uploads/2025/11/P8700-F_Programmers_Reference_Manual-TM.pdf Signed-off-by: Vladimir Kondratiev <vladimir.kondratiev@mobileye.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20260223-for-upstream-eyeq7h-v3-15-621d004d1a21@mobileye.com Signed-off-by: Anup Patel <anup@brainfault.org>
151 lines
3.5 KiB
C
151 lines
3.5 KiB
C
/*
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* SPDX-License-Identifier: BSD-2-Clause
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*
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* Copyright (c) 2025 MIPS
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*
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*/
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#include <platform_override.h>
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#include <sbi/riscv_barrier.h>
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#include <sbi/riscv_io.h>
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#include <sbi/sbi_domain.h>
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#include <sbi/sbi_error.h>
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#include <sbi/sbi_hsm.h>
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#include <sbi/sbi_timer.h>
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#include <sbi_utils/fdt/fdt_helper.h>
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#include <mips/p8700.h>
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#include <mips/mips-cm.h>
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/* Use in nascent init - not have DTB yet */
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#define DRAM_ADDRESS 0x80000000
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#define DRAM_SIZE 0x80000000
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#define DRAM_PMP_ADDR ((DRAM_ADDRESS >> 2) | ((DRAM_SIZE - 1) >> 3))
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static const struct sbi_hsm_device mips_hsm = {
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.name = "mips_hsm",
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.hart_start = mips_p8700_hart_start,
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.hart_stop = mips_p8700_hart_stop,
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};
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static int boston_final_init(bool cold_boot)
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{
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if (cold_boot)
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sbi_hsm_set_device(&mips_hsm);
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return generic_final_init(cold_boot);
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}
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static int boston_early_init(bool cold_boot)
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{
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int rc;
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rc = generic_early_init(cold_boot);
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if (rc)
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return rc;
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if (!cold_boot)
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return 0;
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rc = mips_p8700_add_memranges();
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return rc;
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}
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static int boston_nascent_init(void)
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{
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u64 hartid = current_hartid();
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unsigned long cm_base = p8700_cm_info->gcr_base[0];
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int i;
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/* Coherence enable for every core */
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if (cpu_hart(hartid) == 0) {
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cm_base += (cpu_core(hartid) << CM_BASE_CORE_SHIFT);
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__raw_writeq(GCR_CORE_COH_EN_EN,
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(void *)(cm_base + GCR_OFF_LOCAL +
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GCR_CORE_COH_EN));
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mb();
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}
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/* Set up pmp for DRAM */
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csr_write(CSR_PMPADDR14, DRAM_PMP_ADDR);
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/* All from 0x0 */
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csr_write(CSR_PMPADDR15, 0x1fffffffffffffff);
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csr_write(CSR_PMPCFG2, ((PMP_A_NAPOT|PMP_R|PMP_W|PMP_X)<<56)|
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((PMP_A_NAPOT|PMP_R|PMP_W|PMP_X)<<48));
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/* Set cacheable for pmp6, uncacheable for pmp7 */
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csr_write(CSR_MIPSPMACFG2, ((u64)CCA_CACHE_DISABLE << 56)|
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((u64)CCA_CACHE_ENABLE << 48));
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/* Reset pmpcfg0 */
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csr_write(CSR_PMPCFG0, 0);
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/* Reset pmacfg0 */
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csr_write(CSR_MIPSPMACFG0, 0);
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mb();
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/* Per cluster set up */
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if (cpu_core(hartid) == 0 && cpu_hart(hartid) == 0) {
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/* Enable L2 prefetch */
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__raw_writel(0xfffff110,
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(void *)(cm_base + L2_PFT_CONTROL_OFFSET));
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__raw_writel(0x15ff,
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(void *)(cm_base + L2_PFT_CONTROL_B_OFFSET));
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}
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/* Per core set up */
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if (cpu_hart(hartid) == 0) {
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/* Enable load pair, store pair, and HTW */
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csr_clear(CSR_MIPSCONFIG7, (1<<12)|(1<<13)|(1<<7));
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/* Disable noRFO, misaligned load/store */
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csr_set(CSR_MIPSCONFIG7, (1<<25)|(1<<9));
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/* Enable L1-D$ Prefetch */
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csr_write(CSR_MIPSCONFIG11, 0xff);
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for (i = 0; i < 8; i++) {
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csr_set(CSR_MIPSCONFIG8, 4 + 0x100 * i);
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csr_set(CSR_MIPSCONFIG9, 8);
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mb();
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RISCV_FENCE_I;
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}
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}
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/* Per hart set up */
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/* Enable AMO and RDTIME illegal instruction exceptions. */
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csr_set(CSR_MIPSCONFIG6, (1<<2)|(1<<1));
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return 0;
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}
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static int boston_platform_init(const void *fdt, int nodeoff, const struct fdt_match *match)
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{
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int rc = mips_p8700_platform_init(fdt, nodeoff, match);
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if (rc)
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return rc;
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generic_platform_ops.early_init = boston_early_init;
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generic_platform_ops.final_init = boston_final_init;
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generic_platform_ops.nascent_init = boston_nascent_init;
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generic_platform_ops.pmp_set = mips_p8700_pmp_set;
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return 0;
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}
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static unsigned long boston_gcr_base[] = {
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0x16100000,
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};
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static struct p8700_cm_info boston_cm_info = {
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.num_cm = array_size(boston_gcr_base),
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.gcr_base = boston_gcr_base,
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};
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static const struct fdt_match boston_match[] = {
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{ .compatible = "mips,p8700", .data = &boston_cm_info },
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{ },
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};
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const struct fdt_driver mips_p8700_boston = {
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.match_table = boston_match,
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.init = boston_platform_init,
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};
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