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https://github.com/riscv-software-src/opensbi.git
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8e9966c1a7
Corrected the typos of some documents in the 'docs' folder. Signed-off-by: zhangdongdong <zhangdongdong@eswincomputing.com> Reviewed-by: Anup Patel <anup@brainfault.org>
197 lines
4.5 KiB
Markdown
197 lines
4.5 KiB
Markdown
T-HEAD C9xx Series Processors
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=============================
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The **C9xx** series processors are high-performance RISC-V architecture
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multi-core processors with AI vector acceleration engine.
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For more details, refer [T-HEAD.CN](https://www.t-head.cn/)
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To build the platform-specific library and firmware images, provide the
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*PLATFORM=generic* parameter to the top level `make` command.
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Platform Options
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----------------
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The *T-HEAD C9xx* does not have any platform-specific compile options
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because it uses generic platform.
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```
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CROSS_COMPILE=riscv64-linux-gnu- PLATFORM=generic /usr/bin/make
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```
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The *T-HEAD C9xx* DTB provided to OpenSBI generic firmwares will usually have
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"riscv,clint0", "riscv,plic0", "thead,reset-sample" compatible strings.
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DTS Example1: (Single core, eg: Allwinner D1 - c906)
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----------------------------------------------------
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```
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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timebase-frequency = <3000000>;
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cpu@0 {
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device_type = "cpu";
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reg = <0>;
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status = "okay";
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compatible = "riscv";
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riscv,isa = "rv64imafdcv";
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mmu-type = "riscv,sv39";
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cpu0_intc: interrupt-controller {
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#interrupt-cells = <1>;
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compatible = "riscv,cpu-intc";
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interrupt-controller;
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};
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};
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};
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soc {
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#address-cells = <2>;
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#size-cells = <2>;
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compatible = "simple-bus";
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ranges;
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clint0: clint@14000000 {
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compatible = "allwinner,sun20i-d1-clint";
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interrupts-extended = <
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&cpu0_intc 3 &cpu0_intc 7
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>;
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reg = <0x0 0x14000000 0x0 0x04000000>;
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};
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intc: interrupt-controller@10000000 {
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#interrupt-cells = <1>;
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compatible = "allwinner,sun20i-d1-plic",
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"thead,c900-plic";
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interrupt-controller;
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interrupts-extended = <
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&cpu0_intc 0xffffffff &cpu0_intc 9
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>;
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reg = <0x0 0x10000000 0x0 0x04000000>;
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reg-names = "control";
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riscv,max-priority = <7>;
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riscv,ndev = <200>;
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};
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}
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```
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DTS Example2: (Multi cores with soc reset-regs)
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-----------------------------------------------
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```
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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timebase-frequency = <3000000>;
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cpu@0 {
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device_type = "cpu";
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reg = <0>;
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status = "okay";
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compatible = "riscv";
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riscv,isa = "rv64imafdc";
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mmu-type = "riscv,sv39";
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cpu0_intc: interrupt-controller {
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#interrupt-cells = <1>;
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compatible = "riscv,cpu-intc";
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interrupt-controller;
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};
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};
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cpu@1 {
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device_type = "cpu";
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reg = <1>;
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status = "fail";
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compatible = "riscv";
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riscv,isa = "rv64imafdc";
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mmu-type = "riscv,sv39";
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cpu1_intc: interrupt-controller {
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#interrupt-cells = <1>;
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compatible = "riscv,cpu-intc";
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interrupt-controller;
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};
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};
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cpu@2 {
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device_type = "cpu";
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reg = <2>;
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status = "fail";
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compatible = "riscv";
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riscv,isa = "rv64imafdc";
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mmu-type = "riscv,sv39";
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cpu2_intc: interrupt-controller {
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#interrupt-cells = <1>;
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compatible = "riscv,cpu-intc";
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interrupt-controller;
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};
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};
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cpu@3 {
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device_type = "cpu";
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reg = <3>;
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status = "fail";
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compatible = "riscv";
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riscv,isa = "rv64imafdc";
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mmu-type = "riscv,sv39";
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cpu3_intc: interrupt-controller {
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#interrupt-cells = <1>;
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compatible = "riscv,cpu-intc";
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interrupt-controller;
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};
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};
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};
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soc {
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#address-cells = <2>;
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#size-cells = <2>;
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compatible = "simple-bus";
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ranges;
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reset: reset-sample {
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compatible = "thead,reset-sample";
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entry-reg = <0xff 0xff019050>;
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entry-cnt = <4>;
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control-reg = <0xff 0xff015004>;
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control-val = <0x1c>;
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csr-copy = <0x7f3 0x7c0 0x7c1 0x7c2 0x7c3 0x7c5 0x7cc>;
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};
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clint0: clint@ffdc000000 {
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compatible = "riscv,clint0";
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interrupts-extended = <
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&cpu0_intc 3 &cpu0_intc 7
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&cpu1_intc 3 &cpu1_intc 7
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&cpu2_intc 3 &cpu2_intc 7
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&cpu3_intc 3 &cpu3_intc 7
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&cpu4_intc 3 &cpu4_intc 7
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>;
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reg = <0xff 0xdc000000 0x0 0x04000000>;
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};
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intc: interrupt-controller@ffd8000000 {
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#interrupt-cells = <1>;
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compatible = "thead,c900-plic";
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interrupt-controller;
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interrupts-extended = <
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&cpu0_intc 0xffffffff &cpu0_intc 9
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&cpu1_intc 0xffffffff &cpu1_intc 9
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&cpu2_intc 0xffffffff &cpu2_intc 9
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&cpu3_intc 0xffffffff &cpu3_intc 9
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>;
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reg = <0xff 0xd8000000 0x0 0x04000000>;
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reg-names = "control";
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riscv,max-priority = <7>;
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riscv,ndev = <80>;
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};
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}
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```
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DTS Example2: (Multi cores with old reset csrs)
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-----------------------------------------------
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```
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reset: reset-sample {
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compatible = "thead,reset-sample";
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using-csr-reset;
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csr-copy = <0x7c0 0x7c1 0x7c2 0x7c3 0x7c5 0x7cc
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0x3b0 0x3b1 0x3b2 0x3b3
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0x3b4 0x3b5 0x3b6 0x3b7
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0x3a0>;
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};
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```
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