mirror of
https://github.com/riscv-software-src/opensbi.git
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Benoît Monin
50558221cf
Add the Metanoia MT2824 as a generic platform. This SoC contains two AX45MP cores from Andes Technology and uses Andes PMU and vendor-specific extensions. Originally-by: Jun Chang <jun.chang@metanoia-comm.com> Signed-off-by: Benoît Monin <benoit.monin@bootlin.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20260724-mt5824-v3-1-9a7d17d69974@bootlin.com Signed-off-by: Anup Patel <anup@brainfault.org>
148 lines
3.7 KiB
Markdown
148 lines
3.7 KiB
Markdown
Metanoia MT2824 SoC Platform
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============================
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The Metanoia MT2824 is a highly integrated 5G System-on-Chip designed
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for O-RAN radio units and small cells. It features two Andes AX45MP
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RISC-V cores. More details about the SoC and its reference platform
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named MT5824 can be found at the following [link][0].
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To build platform specific library and firmwares, provide the
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*PLATFORM=generic* parameter to the top level make command.
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[0]: https://metanoia-comm.com/products/5g/mt5824/
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Platform Options
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----------------
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The Metanoia MT2824 platform does not have any platform-specific options.
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Building Metanoia MT2824 Platform
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---------------------------------
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```
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make PLATFORM=generic
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```
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DTS Example: (Metanoia MT2824)
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------------------------------
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```
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compatible = "metanoia,mt2824";
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cpus: cpus {
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#address-cells = <0x01>;
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#size-cells = <0x00>;
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timebase-frequency = <20000000>;
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cpu0: cpu@0 {
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device_type = "cpu";
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reg = <0x00>;
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status = "okay";
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compatible = "andestech,ax45mp", "riscv";
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riscv,isa-base = "rv64i";
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riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
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"zicntr", "zicsr", "zifencei",
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"zihpm", "xandespmu";
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mmu-type = "riscv,sv39";
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clock-frequency = <900000000>;
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i-cache-size = <0x8000>;
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i-cache-sets = <0x100>;
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i-cache-line-size = <0x40>;
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i-cache-block-size = <0x40>;
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d-cache-size = <0x8000>;
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d-cache-sets = <0x80>;
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d-cache-line-size = <0x40>;
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d-cache-block-size = <0x40>;
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next-level-cache = <0x01>;
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cpu0intc: interrupt-controller {
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#interrupt-cells = <0x01>;
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interrupt-controller;
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compatible = "andestech,cpu-intc", "riscv,cpu-intc";
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};
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};
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cpu1: cpu@1 {
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device_type = "cpu";
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reg = <0x01>;
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status = "okay";
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compatible = "andestech,ax45mp", "riscv";
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riscv,isa-base = "rv64i";
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riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
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"zicntr", "zicsr", "zifencei",
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"zihpm", "xandespmu";
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mmu-type = "riscv,sv39";
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clock-frequency = <900000000>;
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i-cache-size = <0x8000>;
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i-cache-sets = <0x100>;
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i-cache-line-size = <0x40>;
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i-cache-block-size = <0x40>;
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d-cache-size = <0x8000>;
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d-cache-sets = <0x80>;
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d-cache-line-size = <0x40>;
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d-cache-block-size = <0x40>;
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next-level-cache = <0x01>;
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cpu1intc: interrupt-controller {
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#interrupt-cells = <0x01>;
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interrupt-controller;
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compatible = "andestech,cpu-intc", "riscv,cpu-intc";
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};
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};
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};
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l2c: l2-cache@a000000 {
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compatible = "andestech,ax45mp-cache", "cache";
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reg = <0x00 0xa000000 0x00 0x40000>;
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cache-line-size = <64>;
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cache-level = <2>;
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cache-size = <0x40000>;
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cache-sets = <1024>;
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cache-unified;
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interrupts = <1 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-parent = <&plic>;
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};
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soc: soc {
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#address-cells = <0x02>;
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#size-cells = <0x02>;
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compatible = "simple-bus";
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interrupt-parent = <&plic>;
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ranges;
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plic: interrupt-controller@c000000 {
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compatible = "metanoia,mt2824-plic", "andestech,nceplic100";
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reg = <0x0 0x0c000000 0x0 0x400000>;
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interrupts-extended =
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<&cpu0intc 0x0b>,
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<&cpu0intc 0x09>,
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<&cpu1intc 0x0b>,
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<&cpu1intc 0x09>;
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interrupt-controller;
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#address-cells = <0x00>;
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#interrupt-cells = <0x02>;
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riscv,ndev = <0x47>;
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};
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plicsw: interrupt-controller@c800000 {
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compatible = "metanoia,mt2824-plicsw", "andestech,plicsw";
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reg = <0x00 0x0c800000 0x00 0x400000>;
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interrupts-extended =
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<&cpu0intc IRQ_TYPE_EDGE_BOTH>,
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<&cpu1intc IRQ_TYPE_EDGE_BOTH>;
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};
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plmt0@c400000 {
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compatible = "metanoia,mt2824-plmt", "andestech,plmt0";
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reg = <0x0 0x0c400000 0x0 0x00400000>;
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interrupts-extended =
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<&cpu0intc 0x07>,
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<&cpu1intc 0x07>;
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};
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reboot: reboot@10000004 {
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compatible = "metanoia,mt2824-reboot";
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reg = <0x0 0x10000004 0x0 0x08>;
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};
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};
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```
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