mirror of
https://github.com/riscv-software-src/opensbi.git
synced 2026-09-08 18:21:29 +01:00
David E. Garcia Porras
27d9545384
The tinfo probe only discovers trigger types; WARL fields tied off
inside an implemented trigger CSR (e.g. an mcontrol6 trigger without
load/store address match) are not discoverable. sbi_alloc_trigger()
also selects the first free trigger slot irrespective of the requested
trigger type or configuration. Unsupported configurations are thus
silently dropped by the hardware while SBI reports success, where SBI
v3.0 sections 19.4 / 19.5 require SBI_ERR_NOT_SUPPORTED.
Add an optional platform device, struct sbi_dbtr_device, with a
trigger_supported(idx, tdata1, tdata2, tdata3) callback reporting
whether the trigger slot selected by idx (the tselect value) supports
a given configuration. Use it, together with the probed per-slot
type_mask, to:
- allocate only trigger slots supporting the requested configuration
(new dbtr_find_free_slot() helper)
- reject unsupportable install/update requests with
SBI_ERR_NOT_SUPPORTED
- count only supporting slots in sbi_dbtr_num_trig() (SBI v3.0
section 19.1)
The install path now dry-runs the allocation of the whole batch before
programming any trigger, so a partially-installed batch is never left
behind. Without a registered device, only the type matching applies (unchanged behavior).
Fixes: 97f234f15c ("lib: sbi: Introduce the SBI debug triggers extension support")
Signed-off-by: David E. Garcia Porras <david.garcia@aheadcomputing.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
Link: https://lore.kernel.org/r/20260727183041.258377-2-david.garcia@aheadcomputing.com
Signed-off-by: Anup Patel <anup@brainfault.org>
135 lines
3.6 KiB
C
135 lines
3.6 KiB
C
/*
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* SPDX-License-Identifier: BSD-2-Clause
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*
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* Copyright (c) 2023 Ventana Micro Systems, Inc.
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*
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* Authors:
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* Himanshu Chauhan <hchauhan@ventanamicro.com>
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*/
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#ifndef __SBI_DBTR_H__
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#define __SBI_DBTR_H__
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#include <sbi/riscv_dbtr.h>
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#include <sbi/sbi_types.h>
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struct sbi_domain;
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enum {
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RV_DBTR_DECLARE_BIT(TS, MAPPED, 0), /* trigger mapped to hw trigger */
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RV_DBTR_DECLARE_BIT(TS, U, 1),
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RV_DBTR_DECLARE_BIT(TS, S, 2),
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RV_DBTR_DECLARE_BIT(TS, VU, 3),
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RV_DBTR_DECLARE_BIT(TS, VS, 4),
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RV_DBTR_DECLARE_BIT(TS, HAVE_TRIG, 5), /* H/w dbtr details available */
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RV_DBTR_DECLARE_BIT(TS, HW_IDX, 8), /* Hardware index of trigger */
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};
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enum {
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RV_DBTR_DECLARE_BIT_MASK(TS, MAPPED, 1),
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RV_DBTR_DECLARE_BIT_MASK(TS, U, 1),
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RV_DBTR_DECLARE_BIT_MASK(TS, S, 1),
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RV_DBTR_DECLARE_BIT_MASK(TS, VU, 1),
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RV_DBTR_DECLARE_BIT_MASK(TS, VS, 1),
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RV_DBTR_DECLARE_BIT_MASK(TS, HAVE_TRIG, 1),
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RV_DBTR_DECLARE_BIT_MASK(TS, HW_IDX, (__riscv_xlen-9)),
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};
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#if __riscv_xlen == 64
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#define SBI_DBTR_SHMEM_INVALID_ADDR 0xFFFFFFFFFFFFFFFFUL
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#elif __riscv_xlen == 32
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#define SBI_DBTR_SHMEM_INVALID_ADDR 0xFFFFFFFFUL
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#else
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#error "Unexpected __riscv_xlen"
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#endif
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struct sbi_dbtr_shmem {
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unsigned long phys_lo;
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unsigned long phys_hi;
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};
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struct sbi_dbtr_trigger {
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unsigned long index;
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unsigned long type_mask;
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unsigned long state;
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unsigned long tdata1;
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unsigned long tdata2;
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unsigned long tdata3;
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};
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struct sbi_dbtr_data_msg {
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unsigned long tstate;
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unsigned long tdata1;
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unsigned long tdata2;
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unsigned long tdata3;
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};
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struct sbi_dbtr_id_msg {
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unsigned long idx;
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};
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struct sbi_dbtr_hart_triggers_state {
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struct sbi_dbtr_trigger triggers[RV_MAX_TRIGGERS];
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struct sbi_dbtr_shmem shmem;
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u32 total_trigs;
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u32 available_trigs;
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u32 hartid;
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u32 probed;
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};
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/** Platform specific debug trigger operations */
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struct sbi_dbtr_device {
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char name[32];
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bool (*trigger_supported)(unsigned long idx, unsigned long tdata1,
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unsigned long tdata2, unsigned long tdata3);
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};
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const struct sbi_dbtr_device *sbi_dbtr_get_device(void);
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void sbi_dbtr_set_device(const struct sbi_dbtr_device *dev);
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#define TDATA1_GET_TYPE(_t1) \
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EXTRACT_FIELD(_t1, RV_DBTR_BIT_MASK(TDATA1, TYPE))
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/* Set the hardware index of trigger in logical trigger state */
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#define SET_TRIG_HW_INDEX(_state, _idx) \
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do { \
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_state &= ~RV_DBTR_BIT_MASK(TS, HW_IDX); \
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_state |= (((unsigned long)_idx \
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<< RV_DBTR_BIT(TS, HW_IDX)) \
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& RV_DBTR_BIT_MASK(TS, HW_IDX)); \
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}while (0);
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/** SBI shared mem messages layout */
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union sbi_dbtr_shmem_entry {
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struct sbi_dbtr_data_msg data;
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struct sbi_dbtr_id_msg id;
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};
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#define SBI_DBTR_SHMEM_ALIGN_MASK ((__riscv_xlen / 8) - 1)
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/** Initialize debug triggers */
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int sbi_dbtr_init(struct sbi_scratch *scratch, bool coldboot);
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/** SBI DBTR extension functions */
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int sbi_dbtr_supported(void);
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int sbi_dbtr_setup_shmem(const struct sbi_domain *dom, unsigned long smode,
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unsigned long shmem_phys_lo,
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unsigned long shmem_phys_hi);
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int sbi_dbtr_num_trig(unsigned long trig_tdata1, unsigned long *out);
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int sbi_dbtr_read_trig(unsigned long smode,
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unsigned long trig_idx_base, unsigned long trig_count);
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int sbi_dbtr_install_trig(unsigned long smode,
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unsigned long trig_count, unsigned long *out);
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int sbi_dbtr_uninstall_trig(unsigned long trig_idx_base,
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unsigned long trig_idx_mask);
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int sbi_dbtr_enable_trig(unsigned long trig_idx_base,
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unsigned long trig_idx_mask);
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int sbi_dbtr_update_trig(unsigned long smode,
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unsigned long trig_count);
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int sbi_dbtr_disable_trig(unsigned long trig_idx_base,
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unsigned long trig_idx_mask);
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int sbi_dbtr_get_total_triggers(void);
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#endif
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