mirror of
https://github.com/riscv-software-src/opensbi.git
synced 2026-05-23 14:21:32 +01:00
Dave Patel
21461156da
Eager context switch: Add support for saving and restoring RISC-V vector extension state in OpenSBI. This introduces a per-hart vector context structure and helper routines to perform full context save and restore. The vector context includes vcsr CSRs along with storage for all 32 vector registers. The register state is saved and restored using byte-wise vector load/store instructions (vs8r/vl8r). The implementation follows an eager context switching model where the entire vector state is saved and restored on every context switch. This provides a simple and deterministic mechanism without requiring lazy trap-based management. Signed-off-by: Dave Patel <dave.patel@riscstar.com> Signed-off-by: Anup Patel <anup.patel@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260518083023.997323-2-anup.patel@oss.qualcomm.com Signed-off-by: Anup Patel <anup@brainfault.org>
95 lines
2.0 KiB
C
95 lines
2.0 KiB
C
/*
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* SPDX-License-Identifier: BSD-2-Clause
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*
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* Copyright (c) 2026 RISCstar Solutions.
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*
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* Authors:
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* Dave Patel <dave.patel@riscstar.com>
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*/
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#include <sbi/riscv_encoding.h>
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#include <sbi/riscv_asm.h>
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#include <sbi/sbi_vector.h>
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#include <sbi/sbi_types.h>
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#include <sbi/sbi_hart.h>
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#include <sbi/sbi_error.h>
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size_t sbi_vector_context_size(void)
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{
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return sizeof(struct sbi_vector_context) + (32 * csr_read(CSR_VLENB));
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}
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void sbi_vector_save(struct sbi_vector_context *dst)
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{
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unsigned long vlenb, mstatus_orig;
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if (!dst)
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return;
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/* Step 1. Save original mstatus and Enable VS */
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mstatus_orig = csr_read_set(CSR_MSTATUS, MSTATUS_VS);
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vlenb = csr_read(CSR_VLENB);
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/* Step 2: Save CSRs */
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dst->vcsr = csr_read(vcsr);
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dst->vstart = csr_read(vstart);
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/* Step 3: Save vector registers */
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#define SAVE_VREG(i) \
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({ \
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asm volatile( \
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" .option push\n\t" \
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" .option arch, +v\n\t" \
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" vs8r.v v" #i ", (%0)\n\t" \
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" .option pop\n\t" \
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:: "r"(dst->vregs + (i) * vlenb) : "memory"); \
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}) \
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SAVE_VREG(0);
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SAVE_VREG(8);
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SAVE_VREG(16);
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SAVE_VREG(24);
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#undef SAVE_VREG
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/* Step 4. Restore original mstatus LAST */
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csr_write(CSR_MSTATUS, mstatus_orig);
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}
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void sbi_vector_restore(const struct sbi_vector_context *src)
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{
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unsigned long vlenb, mstatus_orig;
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if (!src)
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return;
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/* Step 1. Save original mstatus and Enable VS */
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mstatus_orig = csr_read_set(CSR_MSTATUS, MSTATUS_VS);
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vlenb = csr_read(CSR_VLENB);
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/* Step 2: Restore vector registers */
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#define RESTORE_VREG(i) \
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({ \
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asm volatile( \
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" .option push\n\t" \
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" .option arch, +v\n\t" \
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" vl8r.v v" #i ", (%0)\n\t" \
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" .option pop\n\t" \
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:: "r"(src->vregs + (i) * vlenb) : "memory"); \
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}) \
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RESTORE_VREG(0);
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RESTORE_VREG(8);
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RESTORE_VREG(16);
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RESTORE_VREG(24);
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#undef RESTORE_VREG
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/* Step 3: Restore CSR's last */
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/* Restore CSRs first */
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csr_write(vcsr, src->vcsr);
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csr_write(vstart, src->vstart);
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/* Step 4. Restore original mstatus LAST */
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csr_write(CSR_MSTATUS, mstatus_orig);
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}
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