Ben Zong-You Xie 4c5d9d9f93 lib: utils/andes: add the SMU and LLC registers to the root domain ...

When a hart implements Smepmp, S-mode and U-mode cannot reach either
device unless its region is shared explicitly. Suspend and resume then
take an access violation as soon as the supervisor touches the SMU or
the LLC.

Share both regions, and take their sizes from the DT nodes rather than
ignoring them.

Signed-off-by: Ben Zong-You Xie <ben717@andestech.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
Link: https://lore.kernel.org/r/20260728081041.2724668-3-ben717@andestech.com
Signed-off-by: Anup Patel <anup@brainfault.org>

2026-09-01 10:46:23 +05:30

..

cache.c

lib: utils/cache: add cache enable function

2026-02-11 12:11:06 +05:30

fdt_andes_llcache.c

lib: utils/andes: add the SMU and LLC registers to the root domain

2026-09-01 10:46:23 +05:30

fdt_cache_drivers.carray

lib: utils: Add FDT cache library

2025-10-28 11:27:10 +05:30

fdt_cache.c

lib: utils/cache: Handle last-level cache correctly in fdt_cache_add()

2025-12-08 09:51:53 +05:30

fdt_cmo_helper.c

lib: utils/cache: add cache enable function

2026-02-11 12:11:06 +05:30

fdt_sifive_ccache.c

utils: cache: Add SiFive ccache controller

2025-10-28 11:27:51 +05:30

fdt_sifive_ec.c

lib: utils/cache: Add SiFive Extensible Cache (EC) driver

2025-12-08 10:01:20 +05:30

fdt_sifive_pl2.c

lib: utils/cache: Add SiFive PL2 controller

2025-12-08 10:01:05 +05:30

Kconfig

lib: utils/cache: add Andes last level cache controller

2026-02-11 12:13:01 +05:30

objects.mk

lib: utils/cache: add Andes last level cache controller

2026-02-11 12:13:01 +05:30