Ben Zong-You Xie
4c5d9d9f93
lib: utils/andes: add the SMU and LLC registers to the root domain
...
When a hart implements Smepmp, S-mode and U-mode cannot reach either
device unless its region is shared explicitly. Suspend and resume then
take an access violation as soon as the supervisor touches the SMU or
the LLC.
Share both regions, and take their sizes from the DT nodes rather than
ignoring them.
Signed-off-by: Ben Zong-You Xie <ben717@andestech.com >
Reviewed-by: Anup Patel <anup@brainfault.org >
Link: https://lore.kernel.org/r/20260728081041.2724668-3-ben717@andestech.com
Signed-off-by: Anup Patel <anup@brainfault.org >
2026-09-01 10:46:23 +05:30
Ben Zong-You Xie
344428d832
lib: utils/cache: fix andes_llcache_enable() return value
...
The driver returned 1 on success where callers expect 0, so the suspend
to RAM aborted right after disabling the LLC and before flushing it.
Fixes: 82b0961821ben717@andestech.com >
Reviewed-by: Anup Patel <anup@brainfault.org >
Link: https://lore.kernel.org/r/20260728081041.2724668-2-ben717@andestech.com
Signed-off-by: Anup Patel <anup@brainfault.org >
2026-09-01 10:46:23 +05:30
Ben Zong-You Xie
82b0961821
lib: utils/cache: add Andes last level cache controller
...
Introduce a FDT-based driver for the Andes Last Level Cache (LLC)
controller to support cache maintenance operations.
Signed-off-by: Ben Zong-You Xie <ben717@andestech.com >
Link: https://lore.kernel.org/r/20251229071914.1451587-5-ben717@andestech.com
Signed-off-by: Anup Patel <anup@brainfault.org >
2026-02-11 12:13:01 +05:30
Ben Zong-You Xie
6d26b43c47
lib: utils/cache: add cache enable function
...
Add functions to enable/disable the cache.
Signed-off-by: Ben Zong-You Xie <ben717@andestech.com >
Link: https://lore.kernel.org/r/20251229071914.1451587-4-ben717@andestech.com
Signed-off-by: Anup Patel <anup@brainfault.org >
2026-02-11 12:11:06 +05:30
Nick Hu
f71bb323f4
lib: utils/cache: Add SiFive Extensible Cache (EC) driver
...
Add support for SiFive Extensible Cache (EC) controller with multi-slice
architecture. The driver implements cache maintenance operations through
MMIO register interface.
Co-developed-by: Vincent Chen <vincent.chen@sifive.com >
Signed-off-by: Vincent Chen <vincent.chen@sifive.com >
Co-developed-by: Samuel Holland <samuel.holland@sifive.com >
Signed-off-by: Samuel Holland <samuel.holland@sifive.com >
Co-developed-by: Yong-Xuan Wang <yongxuan.wang@sifive.com >
Signed-off-by: Yong-Xuan Wang <yongxuan.wang@sifive.com >
Signed-off-by: Nick Hu <nick.hu@sifive.com >
Reviewed-by: Anup Patel <anup@brainfault.org >
Link: https://lore.kernel.org/r/20251114-sifive-cache-drivers-v1-3-8423a721924c@sifive.com
Signed-off-by: Anup Patel <anup@brainfault.org >
2025-12-08 10:01:20 +05:30
Nick Hu
ec51e91eaa
lib: utils/cache: Add SiFive PL2 controller
...
SiFive Private L2(PL2) cache is a private cache owned by each hart. Add
this driver to support private cache flush operations via the MMIO
registers.
Co-developed-by: Eric Lin <eric.lin@sifive.com >
Signed-off-by: Eric Lin <eric.lin@sifive.com >
Co-developed-by: Zong Li <zong.li@sifive.com >
Signed-off-by: Zong Li <zong.li@sifive.com >
Co-developed-by: Vincent Chen <vincent.chen@sifive.com >
Signed-off-by: Vincent Chen <vincent.chen@sifive.com >
Co-developed-by: Samuel Holland <samuel.holland@sifive.com >
Signed-off-by: Samuel Holland <samuel.holland@sifive.com >
Signed-off-by: Nick Hu <nick.hu@sifive.com >
Reviewed-by: Anup Patel <anup@brainfault.org >
Link: https://lore.kernel.org/r/20251114-sifive-cache-drivers-v1-2-8423a721924c@sifive.com
Signed-off-by: Anup Patel <anup@brainfault.org >
2025-12-08 10:01:05 +05:30
Nick Hu
35aece218a
lib: utils/cache: Handle last-level cache correctly in fdt_cache_add()
...
The fdt_cache_add() helper attempts to retrieve the next-level cache and
returns SBI_ENOENT when there is none. Since this condition only indicates
that the current cache is the last-level cache, the helper should not
treat it as an error.
Signed-off-by: Nick Hu <nick.hu@sifive.com >
Reviewed-by: Anup Patel <anup@brainfault.org >
Link: https://lore.kernel.org/r/20251114-sifive-cache-drivers-v1-1-8423a721924c@sifive.com
Signed-off-by: Anup Patel <anup@brainfault.org >
2025-12-08 09:51:53 +05:30
Nick Hu
ce4dc7649e
lib: utils/cache: Add fdt cmo helpers
...
Add the helpers to build up the cache hierarchy via FDT and provide some
cmo functions for the user who want to flush the entire cache.
Signed-off-by: Nick Hu <nick.hu@sifive.com >
Reviewed-by: Samuel Holland <samuel.holland@sifive.com >
Reviewed-by: Anup Patel <anup@brainfault.org >
Link: https://lore.kernel.org/r/20251020-cache-upstream-v7-4-69a132447d8a@sifive.com
Signed-off-by: Anup Patel <anup@brainfault.org >
2025-10-28 11:27:53 +05:30
Vincent Chen
8ea972838c
utils: cache: Add SiFive ccache controller
...
SiFive Composable cache is a L3 share cache of the core complex. Add this
driver to support the share cache maintenance operations via the MMIO
registers.
Co-developed-by: Samuel Holland <samuel.holland@sifive.com >
Signed-off-by: Samuel Holland <samuel.holland@sifive.com >
Signed-off-by: Vincent Chen <vincent.chen@sifive.com >
Co-developed-by: Nick Hu <nick.hu@sifive.com >
Signed-off-by: Nick Hu <nick.hu@sifive.com >
Reviewed-by: Samuel Holland <samuel.holland@sifive.com >
Reviewed-by: Anup Patel <anup@brainfault.org >
Link: https://lore.kernel.org/r/20251020-cache-upstream-v7-3-69a132447d8a@sifive.com
Signed-off-by: Anup Patel <anup@brainfault.org >
2025-10-28 11:27:51 +05:30
Nick Hu
d6b684ec86
lib: utils: Add FDT cache library
...
Add the FDT cache library so we can build up the cache topology via the
'next-level-cache' DT property.
Co-developed-by: Vincent Chen <vincent.chen@sifive.com >
Signed-off-by: Vincent Chen <vincent.chen@sifive.com >
Co-developed-by: Andy Chiu <andy.chiu@sifive.com >
Signed-off-by: Andy Chiu <andy.chiu@sifive.com >
Signed-off-by: Nick Hu <nick.hu@sifive.com >
Reviewed-by: Samuel Holland <samuel.holland@sifive.com >
Reviewed-by: Anup Patel <anup@brainfault.org >
Link: https://lore.kernel.org/r/20251020-cache-upstream-v7-2-69a132447d8a@sifive.com
Signed-off-by: Anup Patel <anup@brainfault.org >
2025-10-28 11:27:10 +05:30
Nick Hu
1207c7568f
lib: utils: Add cache flush library
...
The current RISC-V CMO only defines how to flush a cache block. However,
certain use cases, such as power management, may require flushing the
entire cache. Therefore, a framework is being introduced to allow vendors
to flush the entire cache using their own methods.
Signed-off-by: Nick Hu <nick.hu@sifive.com >
Reviewed-by: Samuel Holland <samuel.holland@sifive.com >
Reviewed-by: Anup Patel <anup@brainfault.org >
Link: https://lore.kernel.org/r/20251020-cache-upstream-v7-1-69a132447d8a@sifive.com
Signed-off-by: Anup Patel <anup@brainfault.org >
2025-10-28 10:39:59 +05:30
Ben Zong-You Xie