Xiang Wang 05602e2bf4 firmware: Add a barrier instruction for wait for boot hart ...

Multi-core communication via memory requires the addition of a barrier
instructions to ensure cache coherency.

Signed-off-by: Xiang Wang <wxjstz@126.com>

2019-03-05 09:09:40 +05:30

..

payloads

firmware: Use CSR_<FOO> instead of <foo> for csr*

2019-02-14 09:31:18 +05:30

external_deps.mk

all: Update copyright header in all files

2019-01-24 14:07:47 +05:30

fw_base.ldS

all: Update copyright header in all files

2019-01-24 14:07:47 +05:30

fw_base.S

firmware: Add a barrier instruction for wait for boot hart

2019-03-05 09:09:40 +05:30

fw_jump.elf.ldS

all: Update copyright header in all files

2019-01-24 14:07:47 +05:30

fw_jump.S

all: Update copyright header in all files

2019-01-24 14:07:47 +05:30

fw_payload.elf.ldS

all: Update copyright header in all files

2019-01-24 14:07:47 +05:30

fw_payload.S

firmware: Ensure the payloads are 4 bit alligned

2019-02-15 09:56:47 +05:30

objects.mk

firwmare: don't expand macros in FW_PAYLOAD_PATH

2019-02-06 10:39:17 +05:30