include: Bump-up version to 0.8

This patch updates OpenSBI version to 0.8 as part of
release preparation.

Signed-off-by: Anup Patel <anup.patel@wdc.com>

Makefile

@@ -29,16 +29,17 @@ endif
 ifeq ($(build_dir),$(CURDIR))
 $(error Build directory is same as source directory.)
 endif
+install_root_dir_default=$(CURDIR)/install
 ifdef I
- install_dir=$(shell $(READLINK) -f $(I))
+ install_root_dir=$(shell $(READLINK) -f $(I))
 else
- install_dir=$(CURDIR)/install
+ install_root_dir=$(install_root_dir_default)/usr
 endif
-ifeq ($(install_dir),$(CURDIR))
-$(error Install directory is same as source directory.)
+ifeq ($(install_root_dir),$(CURDIR))
+$(error Install root directory is same as source directory.)
 endif
-ifeq ($(install_dir),$(build_dir))
-$(error Install directory is same as build directory.)
+ifeq ($(install_root_dir),$(build_dir))
+$(error Install root directory is same as build directory.)
 endif
 ifdef PLATFORM_DIR
   platform_dir_path=$(shell $(READLINK) -f $(PLATFORM_DIR))
@@ -129,7 +130,6 @@ libsbi-objs-path-y=$(foreach obj,$(libsbi-objs-y),$(build_dir)/lib/sbi/$(obj))
 libsbiutils-objs-path-y=$(foreach obj,$(libsbiutils-objs-y),$(build_dir)/lib/utils/$(obj))
 ifdef PLATFORM
 platform-objs-path-y=$(foreach obj,$(platform-objs-y),$(platform_build_dir)/$(obj))
-platform-dtb-path-y=$(foreach obj,$(platform-dtb-y),$(platform_build_dir)/$(obj))
 firmware-bins-path-y=$(foreach bin,$(firmware-bins-y),$(platform_build_dir)/firmware/$(bin))
 endif
 firmware-elfs-path-y=$(firmware-bins-path-y:.bin=.elf)
@@ -156,6 +156,33 @@ ifndef PLATFORM_RISCV_CODE_MODEL
   PLATFORM_RISCV_CODE_MODEL = medany
 endif
 
+# Setup install directories
+ifdef INSTALL_INCLUDE_PATH
+	install_include_path=$(INSTALL_INCLUDE_PATH)
+else
+	install_include_path=include
+endif
+ifdef INSTALL_LIB_PATH
+	install_lib_path=$(INSTALL_LIB_PATH)
+else
+	ifneq ($(origin INSTALL_LIB_SUBDIR), undefined)
+		install_lib_subdir=$(INSTALL_LIB_SUBDIR)
+	else
+		install_lib_subdir=$(PLATFORM_RISCV_ABI)
+	endif
+	install_lib_path=lib$(subst 32,,$(PLATFORM_RISCV_XLEN))/$(install_lib_subdir)
+endif
+ifdef INSTALL_FIRMWARE_PATH
+	install_firmware_path=$(INSTALL_FIRMWARE_PATH)
+else
+	install_firmware_path=share/opensbi/$(PLATFORM_RISCV_ABI)
+endif
+ifdef INSTALL_DOCS_PATH
+	install_docs_path=$(INSTALL_DOCS_PATH)
+else
+	install_docs_path=share/opensbi/docs
+endif
+
 # Setup compilation commands flags
 GENFLAGS	=	-I$(platform_src_dir)/include
 GENFLAGS	+=	-I$(include_dir)
@@ -199,7 +226,7 @@ MERGEFLAGS	+=	-r
 MERGEFLAGS	+=	-b elf$(PLATFORM_RISCV_XLEN)-littleriscv
 MERGEFLAGS	+=	-m elf$(PLATFORM_RISCV_XLEN)lriscv
 
-DTCFLAGS	=	-O dtb
+DTSCPPFLAGS	=	$(CPPFLAGS) -nostdinc -nostdlib -fno-builtin -D__DTS__ -x assembler-with-cpp
 
 # Setup functions for compilation
 define dynamic_flags
@@ -215,12 +242,12 @@ copy_file =  $(CMD_PREFIX)mkdir -p `dirname $(1)`; \
 	     echo " COPY      $(subst $(build_dir)/,,$(1))"; \
 	     cp -f $(2) $(1)
 inst_file =  $(CMD_PREFIX)mkdir -p `dirname $(1)`; \
-	     echo " INSTALL   $(subst $(install_dir)/,,$(1))"; \
+	     echo " INSTALL   $(subst $(install_root_dir)/,,$(1))"; \
 	     cp -f $(2) $(1)
 inst_file_list = $(CMD_PREFIX)if [ ! -z "$(4)" ]; then \
 	     mkdir -p $(1)/$(3); \
 	     for file in $(4) ; do \
-	     rel_file=`echo $$file | sed -e 's@$(2)/$(3)/@@'`; \
+	     rel_file=`echo $$file | sed -e 's@$(2)/$(subst $(install_firmware_path),platform,$(3))@@'`; \
 	     dest_file=$(1)"/"$(3)"/"`echo $$rel_file`; \
 	     dest_dir=`dirname $$dest_file`; \
 	     echo " INSTALL   "$(3)"/"`echo $$rel_file`; \
@@ -229,7 +256,7 @@ inst_file_list = $(CMD_PREFIX)if [ ! -z "$(4)" ]; then \
 	     done \
 	     fi
 inst_header_dir =  $(CMD_PREFIX)mkdir -p $(1); \
-	     echo " INSTALL   $(subst $(install_dir)/,,$(1))"; \
+	     echo " INSTALL   $(subst $(install_root_dir)/,,$(1))"; \
 	     cp -rf $(2) $(1)
 compile_cpp = $(CMD_PREFIX)mkdir -p `dirname $(1)`; \
 	     echo " CPP       $(subst $(build_dir)/,,$(1))"; \
@@ -261,13 +288,18 @@ compile_objcopy = $(CMD_PREFIX)mkdir -p `dirname $(1)`; \
 	     $(OBJCOPY) -S -O binary $(2) $(1)
 compile_dts = $(CMD_PREFIX)mkdir -p `dirname $(1)`; \
 	     echo " DTC       $(subst $(build_dir)/,,$(1))"; \
-	     $(DTC) $(DTCFLAGS) -o $(1) $(2)
+	     $(CPP) $(DTSCPPFLAGS) $(2) | $(DTC) -O dtb -i `dirname $(2)` -o $(1)
+compile_d2c = $(CMD_PREFIX)mkdir -p `dirname $(1)`; \
+	     echo " D2C       $(subst $(build_dir)/,,$(1))"; \
+	     $(src_dir)/scripts/d2c.sh -i $(4) -a $(3) -p $(2) > $(1)
+compile_gen_dep = $(CMD_PREFIX)mkdir -p `dirname $(1)`; \
+	     echo " GEN-DEP   $(subst $(build_dir)/,,$(1))"; \
+	     echo "$(1:.dep=$(2)): $(3)" >> $(1)
 
 targets-y  = $(build_dir)/lib/libsbi.a
 targets-y  += $(build_dir)/lib/libsbiutils.a
 ifdef PLATFORM
 targets-y += $(platform_build_dir)/lib/libplatsbi.a
-targets-y += $(platform-dtb-path-y)
 endif
 targets-y += $(firmware-bins-path-y)
 
@@ -314,12 +346,26 @@ $(platform_build_dir)/%.dep: $(platform_src_dir)/%.c
 $(platform_build_dir)/%.o: $(platform_src_dir)/%.c
 	$(call compile_cc,$@,$<)
 
+$(platform_build_dir)/%.o: $(platform_build_dir)/%.c
+	$(call compile_cc,$@,$<)
+
 $(platform_build_dir)/%.dep: $(platform_src_dir)/%.S
 	$(call compile_as_dep,$@,$<)
 
 $(platform_build_dir)/%.o: $(platform_src_dir)/%.S
 	$(call compile_as,$@,$<)
 
+$(platform_build_dir)/%.dep: $(platform_src_dir)/%.dts
+	$(call compile_gen_dep,$@,.dtb,$<)
+	$(call compile_gen_dep,$@,.c,$(@:.dep=.dtb))
+	$(call compile_gen_dep,$@,.o,$(@:.dep=.c))
+
+$(platform_build_dir)/%.c: $(platform_build_dir)/%.dtb
+	$(call compile_d2c,$@,$(platform-varprefix-$(subst .dtb,.o,$(subst /,-,$(subst $(platform_build_dir)/,,$<)))),16,$<)
+
+$(platform_build_dir)/%.dtb: $(platform_src_dir)/%.dts
+	$(call compile_dts,$@,$<)
+
 $(platform_build_dir)/%.dep: $(src_dir)/%.c
 	$(call compile_cc_dep,$@,$<)
 
@@ -332,9 +378,6 @@ $(platform_build_dir)/%.dep: $(src_dir)/%.S
 $(platform_build_dir)/%.o: $(src_dir)/%.S
 	$(call compile_as,$@,$<)
 
-$(build_dir)/%.dtb: $(src_dir)/%.dts
-	$(call compile_dts,$@,$<)
-
 # Rule for "make docs"
 $(build_dir)/docs/latex/refman.pdf: $(build_dir)/docs/latex/refman.tex
 	$(CMD_PREFIX)mkdir -p $(build_dir)/docs
@@ -385,26 +428,26 @@ install: $(install_targets-y)
 
 .PHONY: install_libsbi
 install_libsbi: $(build_dir)/lib/libsbi.a
-	$(call inst_header_dir,$(install_dir)/include,$(include_dir)/sbi)
-	$(call inst_file,$(install_dir)/lib/libsbi.a,$(build_dir)/lib/libsbi.a)
+	$(call inst_header_dir,$(install_root_dir)/$(install_include_path),$(include_dir)/sbi)
+	$(call inst_file,$(install_root_dir)/$(install_lib_path)/libsbi.a,$(build_dir)/lib/libsbi.a)
 
 .PHONY: install_libsbiutils
 install_libsbiutils: $(build_dir)/lib/libsbiutils.a
-	$(call inst_header_dir,$(install_dir)/include,$(include_dir)/sbi_utils)
-	$(call inst_file,$(install_dir)/lib/libsbiutils.a,$(build_dir)/lib/libsbiutils.a)
+	$(call inst_header_dir,$(install_root_dir)/$(install_include_path),$(include_dir)/sbi_utils)
+	$(call inst_file,$(install_root_dir)/$(install_lib_path)/libsbiutils.a,$(build_dir)/lib/libsbiutils.a)
 
 .PHONY: install_libplatsbi
 install_libplatsbi: $(platform_build_dir)/lib/libplatsbi.a $(build_dir)/lib/libsbi.a $(build_dir)/lib/libsbiutils.a
-	$(call inst_file,$(install_dir)/platform/$(platform_subdir)/lib/libplatsbi.a,$(platform_build_dir)/lib/libplatsbi.a)
+	$(call inst_file,$(install_root_dir)/$(install_lib_path)/opensbi/$(platform_subdir)/lib/libplatsbi.a,$(platform_build_dir)/lib/libplatsbi.a)
 
 .PHONY: install_firmwares
 install_firmwares: $(platform_build_dir)/lib/libplatsbi.a $(build_dir)/lib/libsbi.a $(build_dir)/lib/libsbiutils.a $(firmware-bins-path-y)
-	$(call inst_file_list,$(install_dir),$(build_dir),platform/$(platform_subdir)/firmware,$(firmware-elfs-path-y))
-	$(call inst_file_list,$(install_dir),$(build_dir),platform/$(platform_subdir)/firmware,$(firmware-bins-path-y))
+	$(call inst_file_list,$(install_root_dir),$(build_dir),$(install_firmware_path)/$(platform_subdir)/firmware,$(firmware-elfs-path-y))
+	$(call inst_file_list,$(install_root_dir),$(build_dir),$(install_firmware_path)/$(platform_subdir)/firmware,$(firmware-bins-path-y))
 
 .PHONY: install_docs
 install_docs: $(build_dir)/docs/latex/refman.pdf
-	$(call inst_file,$(install_dir)/docs/refman.pdf,$(build_dir)/docs/latex/refman.pdf)
+	$(call inst_file,$(install_root_dir)/$(install_docs_path)/refman.pdf,$(build_dir)/docs/latex/refman.pdf)
 
 # Rule for "make clean"
 .PHONY: clean
@@ -429,7 +472,7 @@ ifeq ($(build_dir),$(CURDIR)/build)
 	$(if $(V), @echo " RM        $(build_dir)")
 	$(CMD_PREFIX)rm -rf $(build_dir)
 endif
-ifeq ($(install_dir),$(CURDIR)/install)
-	$(if $(V), @echo " RM        $(install_dir)")
-	$(CMD_PREFIX)rm -rf $(install_dir)
+ifeq ($(install_root_dir),$(install_root_dir_default)/usr)
+	$(if $(V), @echo " RM        $(install_root_dir_default)")
+	$(CMD_PREFIX)rm -rf $(install_root_dir_default)
 endif

README.md

@@ -1,9 +1,41 @@
-Copyright (c) 2019 Western Digital Corporation or its affiliates
-and other contributors.
-
 RISC-V Open Source Supervisor Binary Interface (OpenSBI)
 ========================================================
 
+Copyright and License
+---------------------
+
+The OpenSBI project is copyright (c) 2019 Western Digital Corporation
+or its affiliates and other contributors.
+
+It is distributed under the terms of the BSD 2-clause license
+("Simplified BSD License" or "FreeBSD License", SPDX: *BSD-2-Clause*).
+A copy of this license with OpenSBI copyright can be found in the file
+[COPYING.BSD].
+
+All source files in OpenSBI contain the 2-Clause BSD license SPDX short
+identifier in place of the full license text.
+
+```
+SPDX-License-Identifier:    BSD-2-Clause
+```
+
+This enables machine processing of license information based on the SPDX
+License Identifiers that are available on the [SPDX] web site.
+
+OpenSBI source code also contains code reused from other projects as listed
+below. The original license text of these projects is included in the source
+files where the reused code is present.
+
+* The libfdt source code is disjunctively dual licensed
+  (GPL-2.0+ OR BSD-2-Clause). Some of this project code is used in OpenSBI
+  under the terms of the BSD 2-Clause license. Any contributions to this
+  code must be made under the terms of both licenses.
+
+See also the [third party notices] file for more information.
+
+Introduction
+------------
+
 The **RISC-V Supervisor Binary Interface (SBI)** is the recommended interface
 between:
 
@@ -39,6 +71,27 @@ OpenSBI also provides several runtime firmware examples built using the platform
 *riscv-pk* bootloader (aka BBL) and enable the use of well-known bootloaders
 such as [U-Boot] (https://git.denx.de/u-boot.git).
 
+Supported SBI version
+---------------------
+Currently, OpenSBI fully supports SBI specification *v0.2*. OpenSBI also
+supports Hart State Management (HSM) SBI extension starting from OpenSBI v0.7.
+HSM extension allows S-mode software to boot all the harts a defined order
+rather than legacy method of random booting of harts. As a result, many
+required features such as CPU hotplug, kexec/kdump can also be supported easily
+in S-mode. HSM extension in OpenSBI is implemented in a non-backward compatible
+manner to reduce the maintenance burden and avoid confusion. That's why, any
+S-mode software using OpenSBI will not be able to boot more than 1 hart if HSM
+extension is not supported in S-mode.
+
+Linux kernel already supports SBI v0.2 and HSM SBI extension starting from
+**v5.7-rc1**. If you are using an Linux kernel older than **5.7-rc1** or any
+other S-mode software without HSM SBI extension, you should stick to OpenSBI
+v0.6 to boot all the harts. For a UMP systems, it doesn't matter.
+
+N.B. Any S-mode boot loader (i.e. U-Boot) doesn't need to support HSM extension,
+as it doesn't need to boot all the harts. The operating system should be
+capable enough to bring up all other non-booting harts using HSM extension.
+
 Required Toolchain
 ------------------
 
@@ -94,7 +147,7 @@ line, the platform-specific static library *libplatsbi.a* and firmware examples
 are built for the platform *<platform_subdir>* present in the directory
 *platform* in the OpenSBI top directory. For example, to compile the platform
 library and the firmware examples for the QEMU RISC-V *virt* machine,
-*<platform_subdir>* should be *qemu/virt*.
+*<platform_subdir>* should be *generic*.
 
 To build *libsbi.a*, *libplatsbi.a* and the firmware for one of the supported
 platforms, run:
@@ -150,35 +203,6 @@ export PLATFORM_RISCV_XLEN=32
 
 will generate 32-bit OpenSBI images. And vice vesa.
 
-License
--------
-
-OpenSBI is distributed under the terms of the BSD 2-clause license
-("Simplified BSD License" or "FreeBSD License", SPDX: *BSD-2-Clause*).
-A copy of this license with OpenSBI copyright can be found in the file
-[COPYING.BSD].
-
-All source files in OpenSBI contain the 2-Clause BSD license SPDX short
-identifier in place of the full license text.
-
-```
-SPDX-License-Identifier:    BSD-2-Clause
-```
-
-This enables machine processing of license information based on the SPDX
-License Identifiers that are available on the [SPDX] web site.
-
-OpenSBI source code also contains code reused from other projects as listed
-below. The original license text of these projects is included in the source
-files where the reused code is present.
-
-* The libfdt source code is disjunctively dual licensed
-  (GPL-2.0+ OR BSD-2-Clause). Some of this project code is used in OpenSBI
-  under the terms of the BSD 2-Clause license. Any contributions to this
-  code must be made under the terms of both licenses.
-
-See also the [third party notices] file for more information.
-
 Contributing to OpenSBI
 -----------------------
 
@@ -197,6 +221,7 @@ Detailed documentation of various aspects of OpenSBI can be found under the
 
 * [Contribution Guideline]: Guideline for contributing code to OpenSBI project
 * [Library Usage]: API documentation of OpenSBI static library *libsbi.a*
+* [Platform Requirements]: Requirements for using OpenSBI on a platform
 * [Platform Support Guide]: Guideline for implementing support for new platforms
 * [Platform Documentation]: Documentation of the platforms currently supported.
 * [Firmware Documentation]: Documentation for the different types of firmware
@@ -249,6 +274,7 @@ make I=<install_directory> install_docs
 [Contribution Guideline]: docs/contributing.md
 [Contributors List]: CONTRIBUTORS.md
 [Library Usage]: docs/library_usage.md
+[Platform Requirements]: docs/platform_requirements.md
 [Platform Support Guide]: docs/platform_guide.md
 [Platform Documentation]: docs/platform/platform.md
 [Firmware Documentation]: docs/firmware/fw.md

docs/doxygen.cfg

@@ -793,6 +793,7 @@ WARN_LOGFILE           =
 INPUT                  = @@SRC_DIR@@/README.md \
                          @@SRC_DIR@@/docs/contributing.md \
                          @@SRC_DIR@@/docs/platform_guide.md \
+                         @@SRC_DIR@@/docs/platform_requirements.md \
                          @@SRC_DIR@@/docs/library_usage.md \
                          @@SRC_DIR@@/docs/firmware \
                          @@SRC_DIR@@/docs/platform \
@@ -948,7 +949,7 @@ FILTER_SOURCE_PATTERNS =
 # (index.html). This can be useful if you have a project on for instance GitHub
 # and want to reuse the introduction page also for the doxygen output.
 
-USE_MDFILE_AS_MAINPAGE = 
+USE_MDFILE_AS_MAINPAGE = README.md
 
 #---------------------------------------------------------------------------
 # Configuration options related to source browsing
@@ -1444,7 +1445,7 @@ DISABLE_INDEX          = NO
 # The default value is: NO.
 # This tag requires that the tag GENERATE_HTML is set to YES.
 
-GENERATE_TREEVIEW      = NO
+GENERATE_TREEVIEW      = YES
 
 # The ENUM_VALUES_PER_LINE tag can be used to set the number of enum values that
 # doxygen will group on one line in the generated HTML documentation.

docs/firmware/fw_dynamic.md

@@ -1,4 +1,4 @@
-OpenSBI Firmware with Dynamic Information *FW_DYNAMIC*
+OpenSBI Firmware with Dynamic Information (FW_DYNAMIC)
 ======================================================
 
 OpenSBI **firmware with dynamic info (FW_DYNAMIC)** is a firmware which gets

docs/firmware/fw_jump.md

@@ -1,4 +1,4 @@
-OpenSBI Firmware with Jump Address *FW_JUMP*
+OpenSBI Firmware with Jump Address (FW_JUMP)
 ============================================
 
 OpenSBI **firmware with Jump Address (FW_JUMP)** is a firmware which only

docs/firmware/fw_payload.md

@@ -1,4 +1,4 @@
-OpenSBI Firmware with Payload *FW_PAYLOAD*
+OpenSBI Firmware with Payload (FW_PAYLOAD)
 ==========================================
 
 OpenSBI **firmware with Payload (FW_PAYLOAD)** is a firmware which directly
@@ -57,17 +57,8 @@ file. The parameters currently defined are as follows:
 
 * **FW_PAYLOAD_FDT_PATH** - Path to an external flattened device tree binary
   file to be embedded in the *.text* section of the final firmware. If this
-  option is not provided and no internal device tree file is specified by the
-  platform (c.f. *FW_PAYLOAD_FDT*), then the firmware will expect the FDT to
-  be passed as an argument by the prior booting stage.
-
-* **FW_PAYLOAD_FDT** - Path to an internal flattened device tree binary file
-  defined by the platform code. The file name must match the DTB file name
-  specified in the platform *objects.mk* file with the *platform-dtb-y* entry.
-  This option results in *FW_PAYLOAD_FDT_PATH* to be automatically set.
-  Specifying *FW_PAYLOAD_FDT_PATH* on the `make` command line disables
-  *FW_PAYLOAD_FDT* and the command line specified device tree binary file is
-  used for building the final firmware.
+  option is not provided then the firmware will expect the FDT to be passed
+  as an argument by the prior booting stage.
 
 * **FW_PAYLOAD_FDT_ADDR** - Address where the FDT passed by the prior booting
   stage or specified by the *FW_PAYLOAD_FDT_PATH* parameter and embedded in
@@ -83,7 +74,4 @@ The *[qemu/virt]* platforms illustrate how to configure and use a *FW_PAYLOAD*
 firmware. Detailed information regarding these platforms can be found in the
 platform documentation files.
 
-The *kendryte/k210* platform also enables a build of a *FW_PAYLOAD* using an
-internally defined device tree file (*FW_PAYLOAD_FDT*).
-
 [qemu/virt]: ../platform/qemu_virt.md

docs/firmware/payload_uboot.md

@@ -7,34 +7,9 @@ environment. In the context of OpenSBI, U-Boot can be specified as a payload to
 the OpenSBI firmware, becoming the boot stage following the OpenSBI firmware
 execution.
 
-The current stable upstream code of U-Boot does not yet include all patches
-necessary to fully support OpenSBI. To use U-Boot as an OpenSBI payload, the
-following out-of-tree patch series must be applied to the upstream U-Boot source
-code:
-
-HiFive Unleashed support for U-Boot
-
-https://lists.denx.de/pipermail/u-boot/2019-February/358058.html
-
-This patch series enables a single CPU to execute U-Boot. As a result, the next
-stage boot code such as a Linux kernel can also only execute on a single CPU.
-U-Boot SMP support for RISC-V can be enabled with the following additional
-patches:
-
-https://lists.denx.de/pipermail/u-boot/2019-February/358393.html
-
 Building and Generating U-Boot images
 =====================================
 Please refer to the U-Boot build documentation for detailed instructions on
-how to build U-Boot images.
+how to build U-Boot image and boot high level operating systems from U-Boot
+prompt.
 
-Once U-Boot images are built, the Linux kernel image needs to be converted
-into a format that U-Boot understands:
-
-```
-<uboot-dir>/tools/mkimage -A riscv -O linux -T kernel -C none -a 0x80200000 -e 0x80200000 -n Linux -d \
-		<linux_build_directory>arch/riscv/boot/Image \
-		<linux_build_directory>/arch/riscv/boot/uImage
-```
-
-Copy the uImage to your tftpboot server path if network boot is required.

docs/platform/fpga-ariane.md

@@ -13,7 +13,7 @@ The FPGA SoC currently contains the following peripherals:
 - Bootrom containing zero stage bootloader and device tree.
 
 To build platform specific library and firmwares, provide the
-*PLATFORM=ariane-fpga* parameter to the top level `make` command.
+*PLATFORM=fpga/ariane* parameter to the top level `make` command.
 
 Platform Options
 ----------------
@@ -26,7 +26,7 @@ Building Ariane FPGA Platform
 **Linux Kernel Payload**
 
 ```
-make PLATFORM=ariane-fpga FW_PAYLOAD_PATH=<linux_build_directory>/arch/riscv/boot/Image
+make PLATFORM=fpga/ariane FW_PAYLOAD_PATH=<linux_build_directory>/arch/riscv/boot/Image
 ```
 
 Booting Ariane FPGA Platform

docs/platform/fpga-openpiton.md

@@ -0,0 +1,33 @@
+OpenPiton FPGA SoC Platform
+========================
+OpenPiton is the world's first open source, general purpose, multithreaded
+manycore processor. It is a tiled manycore framework scalable from one to
+1/2 billion cores. Currently, OpenPiton supports the 64bit Ariane RISC-V
+processor from ETH Zurich. To this end, Ariane has been equipped with a
+different L1 cache subsystem that follows a write-through protocol and that has
+support for cache invalidations and atomics.
+
+To build platform specific library and firmwares, provide the
+*PLATFORM=fpga/openpiton* parameter to the top level `make` command.
+
+Platform Options
+----------------
+
+The *OpenPiton* platform does not have any platform-specific options.
+
+Building Ariane FPGA Platform
+-----------------------------
+
+**Linux Kernel Payload**
+
+```
+make PLATFORM=fpga/openpiton FW_PAYLOAD_PATH=<linux_build_directory>/arch/riscv/boot/Image
+```
+
+Booting Ariane FPGA Platform
+----------------------------
+
+**Linux Kernel Payload**
+
+As Linux kernel image is embedded in the OpenSBI firmware binary, Ariane will
+directly boot into Linux directly after powered on.

docs/platform/generic.md

@@ -0,0 +1,54 @@
+Generic Platform
+================
+
+The **Generic** platform is a flattened device tree (FDT) based platform
+where all platform specific functionality is provided based on FDT passed
+by previous booting stage. The **Generic** platform allows us to use same
+OpenSBI firmware binaries on various emulators, simulators, FPGAs, and
+boards.
+
+By default, the generic FDT platform makes following assumptions:
+
+1. platform FW_TEXT_START is 0x80000000
+2. platform features are default
+3. platform stack size is default
+4. platform has no quirks or work-arounds
+
+The above assumptions (except 1) can be overridden by adding special platform
+callbacks which will be called based on FDT root node compatible string.
+
+Users of the generic FDT platform will have to ensure that:
+
+1. Various FDT based drivers under lib/utils directory are upto date
+   based on their platform requirements
+2. The FDT passed by previous booting stage has DT compatible strings and
+   DT properties in sync with the FDT based drivers under lib/utils directory
+3. The FDT must have "stdout-path" DT property in the "/chosen" DT node when
+   a platform has multiple serial ports or consoles
+4. On multi-HART platform, the FDT must have a DT node for IPI device and
+   lib/utils/ipi directory must have corresponding FDT based IPI driver
+5. The FDT must have a DT node for timer device and lib/utils/timer directory
+   must have corresponding FDT based timer driver
+
+To build the platform-specific library and firmware images, provide the
+*PLATFORM=generic* parameter to the top level `make` command.
+
+For custom FW_TEXT_START, we can build the platform-specific library and
+firmware images by passing *PLATFORM=generic FW_TEXT_START=<custom_text_start>*
+parameter to the top level `make` command.
+
+Platform Options
+----------------
+
+The *Generic* platform does not have any platform-specific options.
+
+RISC-V Platforms Using Generic Platform
+---------------------------------------
+
+* **QEMU RISC-V Virt Machine** (*[qemu_virt.md]*)
+* **Spike** (*[spike.md]*)
+* **Shakti C-class SoC Platform** (*[shakti_cclass.md]*)
+
+[qemu_virt.md]: qemu_virt.md
+[spike.md]: spike.md
+[shakti_cclass.md]: shakti_cclass.md

docs/platform/nuclei_ux600.md

@@ -0,0 +1,22 @@
+
+Nuclei UX600 Platform
+=====================
+
+The **Nuclei UX600** is a 64-bit RISC-V Core which is capable of running Linux.
+
+> Nuclei UX600: single core, pipeline as single-issue and 6~9 variable stages, in-order dispatch and out-of-order write-back, running up to >1.2GHz
+
+To build the platform-specific library and firmware images, provide the
+*PLATFORM=nuclei/ux600* parameter to the top level `make` command.
+
+Platform Options
+----------------
+
+The *Nuclei UX600* platform does not have any platform-specific options.
+
+Building Nuclei UX600 Platform
+------------------------------
+
+```
+make PLATFORM=nuclei/ux600 clean all
+```

docs/platform/platform.md

@@ -3,6 +3,11 @@ OpenSBI Supported Platforms
 
 OpenSBI currently supports the following virtual and hardware platforms:
 
+* **Generic**: Flattened device tree (FDT) based platform where platform
+  specific functionality is provided based on the FDT passed by previous
+  booting stage. More details on this platform can be found in the file
+  *[generic.md]*.
+
 * **QEMU RISC-V Virt Machine**: Platform support for the QEMU *virt* virtual
   RISC-V machine. This virtual machine is intended for RISC-V software
   development and tests. More details on this platform can be found in the
@@ -17,13 +22,25 @@ OpenSBI currently supports the following virtual and hardware platforms:
   boards such as the Kendryte KD233 or the Sipeed MAIX Dock.
 
 * **Ariane FPGA SoC**: Platform support for the Ariane FPGA SoC used on
-  Genesys 2 board.
+  Genesys 2 board. More details on this platform can be found in the file
+  *[fpga-ariane.md]*.
 
-* **Andes AE350 SoC**: Platform support for the Andes's SoC (AE350).
+* **Andes AE350 SoC**: Platform support for the Andes's SoC (AE350). More
+  details on this platform can be found in the file *[andes-ae350.md]*.
 
-* **T-HEAD C910**: Platform support for the T-HEAD C910 Processor.
+* **T-HEAD C910**: Platform support for the T-HEAD C910 Processor. More
+  details on this platform can be found in the file *[thead-c910.md]*.
 
-* **Spike**: Platform support for the Spike emulator.
+* **Spike**: Platform support for the Spike emulator. More
+  details on this platform can be found in the file *[spike.md]*.
+
+* **OpenPiton FPGA SoC**: Platform support OpenPiton research platform based
+  on ariane core. More details on this platform can be found in the file
+  *[fpga_openpiton.md]*.
+
+* **Shakti C-class SoC Platform**: Platform support for Shakti C-class
+  processor based SOCs. More details on this platform can be found in the
+  file *[shakti_cclass.md]*.
 
 The code for these supported platforms can be used as example to implement
 support for other platforms. The *platform/template* directory also provides
@@ -31,9 +48,12 @@ template files for implementing support for a new platform. The *object.mk*,
 *config.mk* and *platform.c* template files provides enough comments to
 facilitate the implementation.
 
+[generic.md]: generic.md
 [qemu_virt.md]: qemu_virt.md
 [sifive_fu540.md]: sifive_fu540.md
-[ariane-fpga.md]: ariane-fpga.md
-[andes_ae350.md]: andes-ae350.md
+[fpga-ariane.md]: fpga-ariane.md
+[andes-ae350.md]: andes-ae350.md
 [thead-c910.md]: thead-c910.md
 [spike.md]: spike.md
+[fpga_openpiton.md]: fpga_openpiton.md
+[shakti_cclass.md]: shakti_cclass.md

docs/platform/qemu_virt.md

@@ -7,7 +7,7 @@ software development and testing. It is also referred to as
 storage, and other types of IO.
 
 To build the platform-specific library and firmware images, provide the
-*PLATFORM=qemu/virt* parameter to the top level `make` command.
+*PLATFORM=generic* parameter to the top level `make` command.
 
 Platform Options
 ----------------
@@ -22,13 +22,13 @@ Execution on QEMU RISC-V 64-bit
 
 Build:
 ```
-make PLATFORM=qemu/virt
+make PLATFORM=generic
 ```
 
 Run:
 ```
 qemu-system-riscv64 -M virt -m 256M -nographic \
-	-kernel build/platform/qemu/virt/firmware/fw_payload.elf
+	-kernel build/platform/generic/firmware/fw_payload.bin
 ```
 
 **U-Boot Payload**
@@ -38,19 +38,19 @@ the `qemu-riscv64_smode_defconfig` configuration.
 
 Build:
 ```
-make PLATFORM=qemu/virt FW_PAYLOAD_PATH=<uboot_build_directory>/u-boot.bin
+make PLATFORM=generic FW_PAYLOAD_PATH=<uboot_build_directory>/u-boot.bin
 ```
 
 Run:
 ```
 qemu-system-riscv64 -M virt -m 256M -nographic \
-	-kernel build/platform/qemu/virt/firmware/fw_payload.elf
+	-kernel build/platform/generic/firmware/fw_payload.elf
 ```
 or
 ```
 qemu-system-riscv64 -M virt -m 256M -nographic \
-	-kernel build/platform/qemu/virt/firmware/fw_jump.elf \
-	-device loader,file=<uboot_build_directory>/u-boot.bin,addr=0x80200000
+	-bios build/platform/generic/firmware/fw_jump.bin \
+	-kernel <uboot_build_directory>/u-boot.bin
 ```
 
 **Linux Kernel Payload**
@@ -60,13 +60,13 @@ Note: We assume that the Linux kernel is compiled using
 
 Build:
 ```
-make PLATFORM=qemu/virt FW_PAYLOAD_PATH=<linux_build_directory>/arch/riscv/boot/Image
+make PLATFORM=generic FW_PAYLOAD_PATH=<linux_build_directory>/arch/riscv/boot/Image
 ```
 
 Run:
 ```
 qemu-system-riscv64 -M virt -m 256M -nographic \
-	-kernel build/platform/qemu/virt/firmware/fw_payload.elf \
+	-kernel build/platform/generic/firmware/fw_payload.elf \
 	-drive file=<path_to_linux_rootfs>,format=raw,id=hd0 \
 	-device virtio-blk-device,drive=hd0 \
 	-append "root=/dev/vda rw console=ttyS0"
@@ -74,8 +74,8 @@ qemu-system-riscv64 -M virt -m 256M -nographic \
 or
 ```
 qemu-system-riscv64 -M virt -m 256M -nographic \
-	-kernel build/platform/qemu/virt/firmware/fw_jump.elf \
-	-device loader,file=<linux_build_directory>/arch/riscv/boot/Image,addr=0x80200000 \
+	-bios build/platform/generic/firmware/fw_jump.bin \
+	-kernel <linux_build_directory>/arch/riscv/boot/Image \
 	-drive file=<path_to_linux_rootfs>,format=raw,id=hd0 \
 	-device virtio-blk-device,drive=hd0 \
 	-append "root=/dev/vda rw console=ttyS0"
@@ -89,13 +89,13 @@ Execution on QEMU RISC-V 32-bit
 
 Build:
 ```
-make PLATFORM=qemu/virt
+make PLATFORM=generic PLATFORM_RISCV_XLEN=32
 ```
 
 Run:
 ```
 qemu-system-riscv32 -M virt -m 256M -nographic \
-	-kernel build/platform/qemu/virt/firmware/fw_payload.elf
+	-kernel build/platform/generic/firmware/fw_payload.bin
 ```
 
 **U-Boot Payload**
@@ -105,37 +105,35 @@ the `qemu-riscv32_smode_defconfig` configuration.
 
 Build:
 ```
-make PLATFORM=qemu/virt FW_PAYLOAD_PATH=<uboot_build_directory>/u-boot.bin
+make PLATFORM=generic PLATFORM_RISCV_XLEN=32 FW_PAYLOAD_PATH=<uboot_build_directory>/u-boot.bin
 ```
 
 Run:
 ```
 qemu-system-riscv32 -M virt -m 256M -nographic \
-	-kernel build/platform/qemu/virt/firmware/fw_payload.elf
+	-kernel build/platform/generic/firmware/fw_payload.elf
 ```
 or
 ```
 qemu-system-riscv32 -M virt -m 256M -nographic \
-	-kernel build/platform/qemu/virt/firmware/fw_jump.elf \
-	-device loader,file=<uboot_build_directory>/u-boot.bin,addr=0x80400000
+	-bios build/platform/generic/firmware/fw_jump.bin \
+	-kernel <uboot_build_directory>/u-boot.bin
 ```
 
 **Linux Kernel Payload**
 
 Note: We assume that the Linux kernel is compiled using
-*arch/riscv/configs/rv32_defconfig* (kernel 5.1 and newer)
-respectively using *arch/riscv/configs/defconfig* plus setting
-CONFIG_ARCH_RV32I=y (kernel 5.0 and older).
+*arch/riscv/configs/rv32_defconfig*.
 
 Build:
 ```
-make PLATFORM=qemu/virt FW_PAYLOAD_PATH=<linux_build_directory>/arch/riscv/boot/Image
+make PLATFORM=generic PLATFORM_RISCV_XLEN=32 FW_PAYLOAD_PATH=<linux_build_directory>/arch/riscv/boot/Image
 ```
 
 Run:
 ```
 qemu-system-riscv32 -M virt -m 256M -nographic \
-	-kernel build/platform/qemu/virt/firmware/fw_payload.elf \
+	-kernel build/platform/generic/firmware/fw_payload.elf \
 	-drive file=<path_to_linux_rootfs>,format=raw,id=hd0 \
 	-device virtio-blk-device,drive=hd0 \
 	-append "root=/dev/vda rw console=ttyS0"
@@ -143,8 +141,8 @@ qemu-system-riscv32 -M virt -m 256M -nographic \
 or
 ```
 qemu-system-riscv32 -M virt -m 256M -nographic \
-	-kernel build/platform/qemu/virt/firmware/fw_jump.elf \
-	-device loader,file=<linux_build_directory>/arch/riscv/boot/Image,addr=0x80400000 \
+	-bios build/platform/generic/firmware/fw_jump.bin \
+	-kernel <linux_build_directory>/arch/riscv/boot/Image \
 	-drive file=<path_to_linux_rootfs>,format=raw,id=hd0 \
 	-device virtio-blk-device,drive=hd0 \
 	-append "root=/dev/vda rw console=ttyS0"

docs/platform/shakti_cclass.md

@@ -0,0 +1,33 @@
+Shakti C-class SoC Platform
+===========================
+C-Class is a member of the SHAKTI family of processors from
+Indian Institute of Technology - Madras (IIT-M).
+
+It is an extremely configurable and commercial-grade 5-stage
+in-order core supporting the standard RV64GCSUN ISA extensions.
+
+For more details, refer:
+* https://gitlab.com/shaktiproject/cores/c-class/blob/master/README.md
+* https://c-class.readthedocs.io/en/latest
+* https://shakti.org.in
+
+Platform Options
+----------------
+
+The *Shakti C-class SoC* platform does not have any platform-specific
+options.
+
+Building Shakti C-class Platform
+--------------------------------
+
+**Linux Kernel Payload**
+
+```
+make PLATFORM=generic FW_PAYLOAD_PATH=<linux_build_directory>/arch/riscv/boot/Image FW_PAYLOAD_FDT_PATH=<shakti.dtb path>
+```
+
+**Test Payload**
+
+```
+make PLATFORM=generic FW_PAYLOAD_FDT_PATH=<shakti.dtb path>
+```

docs/platform/sifive_fu540.md

@@ -13,16 +13,8 @@ To build platform specific library and firmwares, provide the
 Platform Options
 ----------------
 
-As hart0 in the FU540 doesn't have an MMU, only harts 1-4 boot by default.
-A hart mask i.e. *FU540_ENABLED_HART_MASK* compile time option is provided
-to select any other hart for booting. Please keep in mind that this is not
-a generic option and it can only be specified for FU540 platform in the
-following way:
-
-```
-make PLATFORM=sifive/fu540 FW_PAYLOAD_PATH=Image FU540_ENABLED_HART_MASK=0x02
-```
-This will let the board boot only hart1 instead of default 1-4.
+The *SiFive FU540 SoC* platform does not have any platform-specific
+options.
 
 Building SiFive Fu540 Platform
 ------------------------------
@@ -57,29 +49,6 @@ The detailed U-Boot booting guide is avaialble at [U-Boot].
 make PLATFORM=sifive/fu540 FW_PAYLOAD_PATH=<u-boot_build_dir>/u-boot-dtb.bin
 ```
 
-**U-Boot & Linux Kernel as a single payload**
-
-A single monolithic image containing both U-Boot & Linux can also be used if
-network boot setup is not available.
-
-1. Create a temporary image with u-boot-dtb.bin as the first payload. The
-command-line example here assumes that U-Boot was compiled using
-sifive_fu540_defconfig configuration.
-```
-dd if=~/workspace/u-boot-riscv/u-boot-dtb.bin of=/tmp/temp.bin bs=1M
-```
-2. Append the Linux Kernel image.
-```
-dd if=<linux_build_directory>/arch/riscv/boot/Image of=/tmp/temp.bin bs=1M seek=4
-```
-3. Compile OpenSBI with temp.bin (generated in step 2) as payload.
-```
-make PLATFORM=sifive/fu540 FW_PAYLOAD_PATH=/tmp/temp.bin
-or
-(For U-Boot which follows Linux v5.2 (or higher) DT bindings)
-make PLATFORM=sifive/fu540 FW_PAYLOAD_PATH=/tmp/temp.bin
-```
-
 Flashing the OpenSBI firmware binary to storage media:
 ------------------------------------------------------
 The first stage boot loader ([FSBL]) expects the storage media to have a GPT

docs/platform/spike.md

@@ -9,7 +9,7 @@ on **Spike** simulator and QEMU Spike machine.
 For more details, refer [Spike on GitHub](https://github.com/riscv/riscv-isa-sim)
 
 To build the platform-specific library and firmware images, provide the
-*PLATFORM=spike* parameter to the top level `make` command.
+*PLATFORM=generic* parameter to the top level `make` command.
 
 Platform Options
 ----------------
@@ -23,12 +23,12 @@ Execution on Spike Simulator
 
 Build:
 ```
-make PLATFORM=spike
+make PLATFORM=generic
 ```
 
 Run:
 ```
-spike build/platform/spike/firmware/fw_payload.elf
+spike build/platform/generic/firmware/fw_payload.elf
 ```
 
 **Linux Kernel Payload**
@@ -38,12 +38,12 @@ Note: We assume that the Linux kernel is compiled using
 
 Build:
 ```
-make PLATFORM=spike FW_PAYLOAD_PATH=<linux_build_directory>/arch/riscv/boot/Image
+make PLATFORM=generic FW_PAYLOAD_PATH=<linux_build_directory>/arch/riscv/boot/Image
 ```
 
 Run:
 ```
-spike --initrd <path_to_cpio_ramdisk> build/platform/spike/firmware/fw_payload.elf
+spike --initrd <path_to_cpio_ramdisk> build/platform/generic/firmware/fw_payload.elf
 ```
 
 Execution on QEMU RISC-V 64-bit
@@ -53,13 +53,13 @@ Execution on QEMU RISC-V 64-bit
 
 Build:
 ```
-make PLATFORM=spike
+make PLATFORM=generic
 ```
 
 Run:
 ```
 qemu-system-riscv64 -M spike -m 256M -nographic \
-	-kernel build/platform/spike/firmware/fw_payload.elf
+	-kernel build/platform/generic/firmware/fw_payload.elf
 ```
 
 **Linux Kernel Payload**
@@ -69,20 +69,20 @@ Note: We assume that the Linux kernel is compiled using
 
 Build:
 ```
-make PLATFORM=spike FW_PAYLOAD_PATH=<linux_build_directory>/arch/riscv/boot/Image
+make PLATFORM=generic FW_PAYLOAD_PATH=<linux_build_directory>/arch/riscv/boot/Image
 ```
 
 Run:
 ```
 qemu-system-riscv64 -M spike -m 256M -nographic \
-	-kernel build/platform/spike/firmware/fw_payload.elf \
+	-kernel build/platform/generic/firmware/fw_payload.elf \
 	-initrd <path_to_cpio_ramdisk> \
 	-append "root=/dev/ram rw console=hvc0 earlycon=sbi"
 ```
 or
 ```
 qemu-system-riscv64 -M spike -m 256M -nographic \
-	-bios build/platform/spike/firmware/fw_jump.elf \
+	-bios build/platform/generic/firmware/fw_jump.elf \
 	-kernel <linux_build_directory>/arch/riscv/boot/Image \
 	-initrd <path_to_cpio_ramdisk> \
 	-append "root=/dev/ram rw console=hvc0 earlycon=sbi"

docs/platform_requirements.md

@@ -0,0 +1,44 @@
+OpenSBI Platform Requirements
+=============================
+
+The RISC-V platform requirements for OpenSBI can change over time
+with advances in RISC-V specifications and ecosystem.
+
+To handle this, we have two types of RISC-V platform requirements:
+
+1. **Base platform requirements** which apply to all OpenSBI releases
+2. **Release specific platform requirements** which apply to a OpenSBI
+   release and later releases
+
+Currently, we don't have any **Release specific platform requirements**
+but such platform requirements will be added in future.
+
+Base Platform Requirements
+--------------------------
+
+The base RISC-V platform requirements for OpenSBI are as follows:
+
+1. At least rv32ima or rv64ima required on all HARTs
+2. At least one HART should have S-mode support because:
+
+     * SBI calls are meant for RISC-V S-mode (Supervisor mode)
+     * OpenSBI implements SBI calls for S-mode software
+
+3. The MTVEC CSR on all HARTs must support direct mode
+4. The PMP CSRs are optional. If PMP CSRs are not implemented then
+   OpenSBI cannot protect M-mode firmware and secured memory regions
+5. The TIME CSR is optional. If TIME CSR is not implemented in
+   hardware then a 64-bit MMIO counter is required to track time
+   and emulate TIME CSR
+6. Hardware support for injecting M-mode software interrupts on
+   a multi-HART platform
+
+The RISC-V extensions not covered by rv32ima or rv64ima are optional
+for OpenSBI. Although, OpenSBI will detect and handle some of these
+optional RISC-V extensions at runtime.
+
+The optional RISC-V extensions handled by OpenSBI at runtime are:
+
+* D-extension: Double precision floating point
+* F-extension: Single precision floating point
+* H-extension: Hypervisor

firmware/fw_base.S

@@ -160,11 +160,48 @@ _relocate_done:
 	li	ra, 0
 	call	_reset_regs
 
+	/* Zero-out BSS */
+	la	s4, _bss_start
+	la	s5, _bss_end
+_bss_zero:
+	REG_S	zero, (s4)
+	add	s4, s4, __SIZEOF_POINTER__
+	blt	s4, s5, _bss_zero
+
+	/* Setup temporary trap handler */
+	la	s4, _start_hang
+	csrw	CSR_MTVEC, s4
+
+	/* Setup temporary stack */
+	la	s4, _fw_end
+	li	s5, (SBI_SCRATCH_SIZE * 2)
+	add	sp, s4, s5
+
 	/* Allow main firmware to save info */
 	MOV_5R	s0, a0, s1, a1, s2, a2, s3, a3, s4, a4
 	call	fw_save_info
 	MOV_5R	a0, s0, a1, s1, a2, s2, a3, s3, a4, s4
 
+	/* Override previous arg1 */
+	MOV_3R	s0, a0, s1, a1, s2, a2
+	call	fw_prev_arg1
+	add	t1, a0, zero
+	MOV_3R	a0, s0, a1, s1, a2, s2
+	beqz	t1, _prev_arg1_override_done
+	add	a1, t1, zero
+_prev_arg1_override_done:
+
+	/*
+	 * Initialize platform
+	 * Note: The a0 to a4 registers passed to the
+	 * firmware are parameters to this function.
+	 */
+	MOV_5R	s0, a0, s1, a1, s2, a2, s3, a3, s4, a4
+	call	fw_platform_init
+	add	t0, a0, zero
+	MOV_5R	a0, s0, a1, s1, a2, s2, a3, s3, a4, s4
+	add	a1, t0, zero
+
 	/* Preload HART details
 	 * s7 -> HART Count
 	 * s8 -> HART Stack Size
@@ -233,35 +270,16 @@ _scratch_init:
 	/* Store firmware options in scratch space */
 	MOV_3R	s0, a0, s1, a1, s2, a2
 #ifdef FW_OPTIONS
-	li	a4, FW_OPTIONS
+	li	a0, FW_OPTIONS
 #else
-	add	a4, zero, zero
-#endif
 	call	fw_options
-	or	a4, a4, a0
-	REG_S	a4, SBI_SCRATCH_OPTIONS_OFFSET(tp)
+#endif
+	REG_S	a0, SBI_SCRATCH_OPTIONS_OFFSET(tp)
 	MOV_3R	a0, s0, a1, s1, a2, s2
 	/* Move to next scratch space */
 	add	t1, t1, t2
 	blt	t1, s7, _scratch_init
 
-	/* Zero-out BSS */
-	la	a4, _bss_start
-	la	a5, _bss_end
-_bss_zero:
-	REG_S	zero, (a4)
-	add	a4, a4, __SIZEOF_POINTER__
-	blt	a4, a5, _bss_zero
-
-	/* Override pervious arg1 */
-	MOV_3R	s0, a0, s1, a1, s2, a2
-	call	fw_prev_arg1
-	add	t1, a0, zero
-	MOV_3R	a0, s0, a1, s1, a2, s2
-	beqz	t1, _prev_arg1_override_done
-	add	a1, t1, zero
-_prev_arg1_override_done:
-
 	/*
 	 * Relocate Flatened Device Tree (FDT)
 	 * source FDT address = previous arg1
@@ -331,7 +349,7 @@ _fdt_reloc_done:
 	fence	rw, rw
 	j	_start_warm
 
-	/* waitting for boot hart done (_boot_status == 2) */
+	/* waiting for boot hart to be done (_boot_status == 2) */
 _wait_for_boot_hart:
 	li	t0, BOOT_STATUS_BOOT_HART_DONE
 	la	t1, _boot_status
@@ -351,6 +369,7 @@ _start_warm:
 	csrw	CSR_MIE, zero
 	csrw	CSR_MIP, zero
 
+	/* Find HART count and HART stack size */
 	la	a4, platform
 #if __riscv_xlen == 64
 	lwu	s7, SBI_PLATFORM_HART_COUNT_OFFSET(a4)
@@ -359,12 +378,29 @@ _start_warm:
 	lw	s7, SBI_PLATFORM_HART_COUNT_OFFSET(a4)
 	lw	s8, SBI_PLATFORM_HART_STACK_SIZE_OFFSET(a4)
 #endif
+	REG_L	s9, SBI_PLATFORM_HART_INDEX2ID_OFFSET(a4)
 
-	/* HART ID should be within expected limit */
+	/* Find HART id */
 	csrr	s6, CSR_MHARTID
-	bge	s6, s7, _start_hang
 
-	/* find the scratch space for this hart */
+	/* Find HART index */
+	beqz	s9, 3f
+	li	a4, 0
+1:
+#if __riscv_xlen == 64
+	lwu	a5, (s9)
+#else
+	lw	a5, (s9)
+#endif
+	beq	a5, s6, 2f
+	add	s9, s9, 4
+	add	a4, a4, 1
+	blt	a4, s7, 1b
+	li	a4, -1
+2:	add	s6, a4, zero
+3:	bge	s6, s7, _start_hang
+
+	/* Find the scratch space based on HART index */
 	la	tp, _fw_end
 	mul	a5, s7, s8
 	add	tp, tp, a5
@@ -382,9 +418,6 @@ _start_warm:
 	/* Setup trap handler */
 	la	a4, _trap_handler
 	csrw	CSR_MTVEC, a4
-	/* Make sure that mtvec is updated */
-1:	csrr	a5, CSR_MTVEC
-	bne	a4, a5, 1b
 
 	/* Initialize SBI runtime */
 	csrr	a0, CSR_MSCRATCH
@@ -409,35 +442,27 @@ _link_end:
 	.align 3
 	.globl _hartid_to_scratch
 _hartid_to_scratch:
-	add	sp, sp, -(3 * __SIZEOF_POINTER__)
-	REG_S	s0, (sp)
-	REG_S	s1, (__SIZEOF_POINTER__)(sp)
-	REG_S	s2, (__SIZEOF_POINTER__ * 2)(sp)
 	/*
 	 * a0 -> HART ID (passed by caller)
-	 * s0 -> HART Stack Size
-	 * s1 -> HART Stack End
-	 * s2 -> Temporary
+	 * a1 -> HART Index (passed by caller)
+	 * t0 -> HART Stack Size
+	 * t1 -> HART Stack End
+	 * t2 -> Temporary
 	 */
-	la	s2, platform
+	la	t2, platform
 #if __riscv_xlen == 64
-	lwu	s0, SBI_PLATFORM_HART_STACK_SIZE_OFFSET(s2)
-	lwu	s2, SBI_PLATFORM_HART_COUNT_OFFSET(s2)
+	lwu	t0, SBI_PLATFORM_HART_STACK_SIZE_OFFSET(t2)
+	lwu	t2, SBI_PLATFORM_HART_COUNT_OFFSET(t2)
 #else
-	lw	s0, SBI_PLATFORM_HART_STACK_SIZE_OFFSET(s2)
-	lw	s2, SBI_PLATFORM_HART_COUNT_OFFSET(s2)
+	lw	t0, SBI_PLATFORM_HART_STACK_SIZE_OFFSET(t2)
+	lw	t2, SBI_PLATFORM_HART_COUNT_OFFSET(t2)
 #endif
-	mul	s2, s2, s0
-	la	s1, _fw_end
-	add	s1, s1, s2
-	mul	s2, s0, a0
-	sub	s1, s1, s2
-	li	s2, SBI_SCRATCH_SIZE
-	sub	a0, s1, s2
-	REG_L	s0, (sp)
-	REG_L	s1, (__SIZEOF_POINTER__)(sp)
-	REG_L	s2, (__SIZEOF_POINTER__ * 2)(sp)
-	add	sp, sp, (3 * __SIZEOF_POINTER__)
+	sub	t2, t2, a1
+	mul	t2, t2, t0
+	la	t1, _fw_end
+	add	t1, t1, t2
+	li	t2, SBI_SCRATCH_SIZE
+	sub	a0, t1, t2
 	ret
 
 	.section .entry, "ax", %progbits
@@ -447,6 +472,14 @@ _start_hang:
 	wfi
 	j	_start_hang
 
+	.section .entry, "ax", %progbits
+	.align 3
+	.globl fw_platform_init
+	.weak fw_platform_init
+fw_platform_init:
+	add	a0, a1, zero
+	ret
+
 	.section .entry, "ax", %progbits
 	.align 3
 	.globl _trap_handler
@@ -546,7 +579,6 @@ _skip_mstatush_save:
 
 	/* Call C routine */
 	add	a0, sp, zero
-	csrr	a1, CSR_MSCRATCH
 	call	sbi_trap_handler
 
 	/* Restore all general regisers except SP and T0 */

firmware/objects.mk

@@ -41,11 +41,6 @@ ifdef FW_PAYLOAD_ALIGN
 firmware-genflags-$(FW_PAYLOAD) += -DFW_PAYLOAD_ALIGN=$(FW_PAYLOAD_ALIGN)
 endif
 
-ifndef FW_PAYLOAD_FDT_PATH
-ifdef FW_PAYLOAD_FDT
-FW_PAYLOAD_FDT_PATH=$(platform_build_dir)/$(FW_PAYLOAD_FDT)
-endif
-endif
 ifdef FW_PAYLOAD_FDT_PATH
 firmware-genflags-$(FW_PAYLOAD) += -DFW_PAYLOAD_FDT_PATH=\"$(FW_PAYLOAD_FDT_PATH)\"
 endif

include/sbi/riscv_asm.h

@@ -28,9 +28,9 @@
 #error "Unexpected __riscv_xlen"
 #endif
 
-#define PAGE_SHIFT      (12)
-#define PAGE_SIZE       (_AC(1, UL) << PAGE_SHIFT)
-#define PAGE_MASK       (~(PAGE_SIZE - 1))
+#define PAGE_SHIFT	(12)
+#define PAGE_SIZE	(_AC(1, UL) << PAGE_SHIFT)
+#define PAGE_MASK	(~(PAGE_SIZE - 1))
 
 #define REG_L		__REG_SEL(ld, lw)
 #define REG_S		__REG_SEL(sd, sw)
@@ -38,7 +38,6 @@
 #define LGREG		__REG_SEL(3, 2)
 
 #if __SIZEOF_POINTER__ == 8
-#define BITS_PER_LONG		64
 #ifdef __ASSEMBLY__
 #define RISCV_PTR		.dword
 #define RISCV_SZPTR		8
@@ -49,7 +48,6 @@
 #define RISCV_LGPTR		"3"
 #endif
 #elif __SIZEOF_POINTER__ == 4
-#define BITS_PER_LONG		32
 #ifdef __ASSEMBLY__
 #define RISCV_PTR		.word
 #define RISCV_SZPTR		4
@@ -159,6 +157,8 @@ void csr_write_num(int csr_num, unsigned long val);
 		__asm__ __volatile__("wfi" ::: "memory"); \
 	} while (0)
 
+/* Get current HART id */
+#define current_hartid()	((unsigned int)csr_read(CSR_MHARTID))
 
 /* determine CPU extension, return non-zero support */
 int misa_extension_imp(char ext);
@@ -173,25 +173,14 @@ int misa_extension_imp(char ext);
 /* Get MXL field of misa, return -1 on error */
 int misa_xlen(void);
 
-static inline void misa_string(char *out, unsigned int out_sz)
-{
-	unsigned long i;
-
-	for (i = 0; i < 26; i++) {
-		if (misa_extension_imp('A' + i)) {
-			*out = 'A' + i;
-			out++;
-		}
-	}
-	*out = '\0';
-	out++;
-}
+/* Get RISC-V ISA string representation */
+void misa_string(int xlen, char *out, unsigned int out_sz);
 
 int pmp_set(unsigned int n, unsigned long prot, unsigned long addr,
 	    unsigned long log2len);
 
 int pmp_get(unsigned int n, unsigned long *prot_out, unsigned long *addr_out,
-	    unsigned long *log2len_out);
+	    unsigned long *size);
 
 #endif /* !__ASSEMBLY__ */
 

include/sbi/riscv_atomic.h

@@ -29,9 +29,9 @@ long atomic_add_return(atomic_t *atom, long value);
 
 long atomic_sub_return(atomic_t *atom, long value);
 
-long arch_atomic_cmpxchg(atomic_t *atom, long oldval, long newval);
+long atomic_cmpxchg(atomic_t *atom, long oldval, long newval);
 
-long arch_atomic_xchg(atomic_t *atom, long newval);
+long atomic_xchg(atomic_t *atom, long newval);
 
 unsigned int atomic_raw_xchg_uint(volatile unsigned int *ptr,
 				  unsigned int newval);

include/sbi/riscv_encoding.h

@@ -25,6 +25,7 @@
 #define MSTATUS_MPP			(_UL(3) << MSTATUS_MPP_SHIFT)
 #define MSTATUS_FS			_UL(0x00006000)
 #define MSTATUS_XS			_UL(0x00018000)
+#define MSTATUS_VS			_UL(0x01800000)
 #define MSTATUS_MPRV			_UL(0x00020000)
 #define MSTATUS_SUM			_UL(0x00040000)
 #define MSTATUS_MXR			_UL(0x00080000)
@@ -53,18 +54,27 @@
 #define SSTATUS_SPP			MSTATUS_SPP
 #define SSTATUS_FS			MSTATUS_FS
 #define SSTATUS_XS			MSTATUS_XS
+#define SSTATUS_VS			MSTATUS_VS
 #define SSTATUS_SUM			MSTATUS_SUM
 #define SSTATUS_MXR			MSTATUS_MXR
 #define SSTATUS32_SD			MSTATUS32_SD
 #define SSTATUS64_UXL			MSTATUS_UXL
 #define SSTATUS64_SD			MSTATUS64_SD
 
+#if __riscv_xlen == 64
+#define HSTATUS_VSXL			_UL(0x300000000)
+#define HSTATUS_VSXL_SHIFT		32
+#endif
 #define HSTATUS_VTSR			_UL(0x00400000)
+#define HSTATUS_VTW			_UL(0x00200000)
 #define HSTATUS_VTVM			_UL(0x00100000)
-#define HSTATUS_SP2V			_UL(0x00000200)
-#define HSTATUS_SP2P			_UL(0x00000100)
+#define HSTATUS_VGEIN			_UL(0x0003f000)
+#define HSTATUS_VGEIN_SHIFT		12
+#define HSTATUS_HU			_UL(0x00000200)
+#define HSTATUS_SPVP			_UL(0x00000100)
 #define HSTATUS_SPV			_UL(0x00000080)
-#define HSTATUS_SPRV			_UL(0x00000001)
+#define HSTATUS_GVA			_UL(0x00000040)
+#define HSTATUS_VSBE			_UL(0x00000020)
 
 #define IRQ_S_SOFT			1
 #define IRQ_VS_SOFT			2
@@ -109,6 +119,21 @@
 #define SATP_MODE_SV57			_UL(10)
 #define SATP_MODE_SV64			_UL(11)
 
+#define HGATP_MODE_OFF			_UL(0)
+#define HGATP_MODE_SV32X4		_UL(1)
+#define HGATP_MODE_SV39X4		_UL(8)
+#define HGATP_MODE_SV48X4		_UL(9)
+
+#define HGATP32_MODE_SHIFT		31
+#define HGATP32_VMID_SHIFT		22
+#define HGATP32_VMID_MASK		_UL(0x1FC00000)
+#define HGATP32_PPN			_UL(0x003FFFFF)
+
+#define HGATP64_MODE_SHIFT		60
+#define HGATP64_VMID_SHIFT		44
+#define HGATP64_VMID_MASK		_ULL(0x03FFF00000000000)
+#define HGATP64_PPN			_ULL(0x00000FFFFFFFFFFF)
+
 #define PMP_R				_UL(0x01)
 #define PMP_W				_UL(0x02)
 #define PMP_X				_UL(0x04)
@@ -121,35 +146,25 @@
 #define PMP_SHIFT			2
 #define PMP_COUNT			16
 
-/* page table entry (PTE) fields */
-#define PTE_V				_UL(0x001) /* Valid */
-#define PTE_R				_UL(0x002) /* Read */
-#define PTE_W				_UL(0x004) /* Write */
-#define PTE_X				_UL(0x008) /* Execute */
-#define PTE_U				_UL(0x010) /* User */
-#define PTE_G				_UL(0x020) /* Global */
-#define PTE_A				_UL(0x040) /* Accessed */
-#define PTE_D				_UL(0x080) /* Dirty */
-#define PTE_SOFT			_UL(0x300) /* Reserved for Software */
-
-#define PTE_PPN_SHIFT			10
-
-#define PTE_TABLE(PTE)			\
-	(((PTE) & (PTE_V | PTE_R | PTE_W | PTE_X)) == PTE_V)
-
 #if __riscv_xlen == 64
 #define MSTATUS_SD			MSTATUS64_SD
 #define SSTATUS_SD			SSTATUS64_SD
-#define RISCV_PGLEVEL_BITS		9
 #define SATP_MODE			SATP64_MODE
+
+#define HGATP_PPN			HGATP64_PPN
+#define HGATP_VMID_SHIFT		HGATP64_VMID_SHIFT
+#define HGATP_VMID_MASK			HGATP64_VMID_MASK
+#define HGATP_MODE_SHIFT		HGATP64_MODE_SHIFT
 #else
 #define MSTATUS_SD			MSTATUS32_SD
 #define SSTATUS_SD			SSTATUS32_SD
-#define RISCV_PGLEVEL_BITS		10
 #define SATP_MODE			SATP32_MODE
+
+#define HGATP_PPN			HGATP32_PPN
+#define HGATP_VMID_SHIFT		HGATP32_VMID_SHIFT
+#define HGATP_VMID_MASK			HGATP32_VMID_MASK
+#define HGATP_MODE_SHIFT		HGATP32_MODE_SHIFT
 #endif
-#define RISCV_PGSHIFT			12
-#define RISCV_PGSIZE			(1 << RISCV_PGSHIFT)
 
 #define CSR_USTATUS			0x0
 #define CSR_FFLAGS			0x1
@@ -417,6 +432,7 @@
 #define CAUSE_STORE_PAGE_FAULT		0xf
 #define CAUSE_FETCH_GUEST_PAGE_FAULT	0x14
 #define CAUSE_LOAD_GUEST_PAGE_FAULT	0x15
+#define CAUSE_VIRTUAL_INST_FAULT	0x16
 #define CAUSE_STORE_GUEST_PAGE_FAULT	0x17
 
 #define INSN_MATCH_LB			0x3

include/sbi/sbi_bitmap.h

@@ -0,0 +1,128 @@
+/*
+ * SPDX-License-Identifier: BSD-2-Clause
+ *
+ * Copyright (c) 2020 Western Digital Corporation or its affiliates.
+ *
+ * Authors:
+ *   Anup Patel <anup.patel@wdc.com>
+ */
+
+#ifndef __SBI_BITMAP_H__
+#define __SBI_BITMAP_H__
+
+#include <sbi/sbi_bitops.h>
+
+#define BITMAP_FIRST_WORD_MASK(start) (~0UL << ((start) % BITS_PER_LONG))
+#define BITMAP_LAST_WORD_MASK(nbits)					\
+(									\
+	((nbits) % BITS_PER_LONG) ?					\
+		((1UL << ((nbits) % BITS_PER_LONG)) - 1) : ~0UL		\
+)
+
+#define small_const_nbits(nbits) \
+	(__builtin_constant_p(nbits) && (nbits) <= BITS_PER_LONG)
+
+#define DECLARE_BITMAP(name, nbits)	unsigned long name[BITS_TO_LONGS(nbits)]
+#define DEFINE_BITMAP(name)		extern unsigned long name[]
+
+static inline unsigned long bitmap_estimate_size(int nbits)
+{
+	return (BITS_TO_LONGS(nbits) * sizeof(unsigned long));
+}
+
+void __bitmap_and(unsigned long *dst, const unsigned long *bitmap1,
+		  const unsigned long *bitmap2, int bits);
+void __bitmap_or(unsigned long *dst, const unsigned long *bitmap1,
+		 const unsigned long *bitmap2, int bits);
+void __bitmap_xor(unsigned long *dst, const unsigned long *bitmap1,
+		  const unsigned long *bitmap2, int bits);
+
+static inline void bitmap_set(unsigned long *bmap, int start, int len)
+{
+	int bit;
+	for (bit = start; bit < (start + len); bit++)
+		bmap[BIT_WORD(bit)] |= (0x1UL << BIT_WORD_OFFSET(bit));
+}
+
+static inline void bitmap_clear(unsigned long *bmap, int start, int len)
+{
+	int bit;
+	for (bit = start; bit < (start + len); bit++)
+		bmap[BIT_WORD(bit)] &= ~(0x1UL << BIT_WORD_OFFSET(bit));
+}
+
+static inline void bitmap_zero(unsigned long *dst, int nbits)
+{
+	if (small_const_nbits(nbits))
+		*dst = 0UL;
+	else {
+		size_t i, len = BITS_TO_LONGS(nbits);
+		for (i = 0; i < len; i++)
+			dst[i] = 0;
+	}
+}
+
+static inline void bitmap_zero_except(unsigned long *dst,
+				      int exception, int nbits)
+{
+	if (small_const_nbits(nbits))
+		*dst = 0UL;
+	else {
+		size_t i, len = BITS_TO_LONGS(nbits);
+		for (i = 0; i < len; i++)
+			dst[i] = 0;
+	}
+	if (exception < nbits)
+		__set_bit(exception, dst);
+}
+
+static inline void bitmap_fill(unsigned long *dst, int nbits)
+{
+	size_t i, nlongs = BITS_TO_LONGS(nbits);
+	if (!small_const_nbits(nbits)) {
+		for (i = 0; i < (nlongs - 1); i++)
+			dst[i] = -1UL;
+	}
+	dst[nlongs - 1] = BITMAP_LAST_WORD_MASK(nbits);
+}
+
+static inline void bitmap_copy(unsigned long *dst,
+			       const unsigned long *src, int nbits)
+{
+	if (small_const_nbits(nbits))
+		*dst = *src;
+	else {
+		size_t i, len = BITS_TO_LONGS(nbits);
+		for (i = 0; i < len; i++)
+			dst[i] = src[i];
+	}
+}
+
+static inline void bitmap_and(unsigned long *dst, const unsigned long *src1,
+			      const unsigned long *src2, int nbits)
+{
+	if (small_const_nbits(nbits))
+		*dst = *src1 & *src2;
+	else
+		__bitmap_and(dst, src1, src2, nbits);
+}
+
+static inline void bitmap_or(unsigned long *dst, const unsigned long *src1,
+			     const unsigned long *src2, int nbits)
+{
+	if (small_const_nbits(nbits))
+		*dst = *src1 | *src2;
+	else
+		__bitmap_or(dst, src1, src2, nbits);
+}
+
+static inline void bitmap_xor(unsigned long *dst, const unsigned long *src1,
+			      const unsigned long *src2, int nbits)
+{
+	if (small_const_nbits(nbits))
+		*dst = *src1 ^ *src2;
+	else
+		__bitmap_xor(dst, src1, src2, nbits);
+}
+
+#endif

include/sbi/sbi_bitops.h

@@ -4,14 +4,37 @@
  * Copyright (c) 2019 Western Digital Corporation or its affiliates.
  *
  * Authors:
- *   Atish Patra<atish.patra@wdc.com>
+ *   Atish Patra <atish.patra@wdc.com>
  */
 
 #ifndef __SBI_BITOPS_H__
 #define __SBI_BITOPS_H__
 
-#include <sbi/sbi_bits.h>
-#include <sbi/riscv_asm.h>
+#include <sbi/sbi_types.h>
+
+#if __SIZEOF_POINTER__ == 8
+#define BITS_PER_LONG		64
+#elif __SIZEOF_POINTER__ == 4
+#define BITS_PER_LONG		32
+#else
+#error "Unexpected __SIZEOF_POINTER__"
+#endif
+
+#define EXTRACT_FIELD(val, which) \
+	(((val) & (which)) / ((which) & ~((which)-1)))
+#define INSERT_FIELD(val, which, fieldval) \
+	(((val) & ~(which)) | ((fieldval) * ((which) & ~((which)-1))))
+
+#define BITS_TO_LONGS(nbits)	(((nbits) + BITS_PER_LONG - 1) / \
+				 BITS_PER_LONG)
+
+#define BIT(nr)			(1UL << (nr))
+#define BIT_MASK(nr)		(1UL << ((nr) % BITS_PER_LONG))
+#define BIT_WORD(bit)		((bit) / BITS_PER_LONG)
+#define BIT_WORD_OFFSET(bit)	((bit) & (BITS_PER_LONG - 1))
+
+#define GENMASK(h, l) \
+	(((~0UL) - (1UL << (l)) + 1) & (~0UL >> (BITS_PER_LONG - 1 - (h))))
 
 /**
  * ffs - Find first bit set
@@ -169,4 +192,133 @@ static inline unsigned long __fls(unsigned long word)
 	return num;
 }
 
+#define for_each_set_bit(bit, addr, size) \
+	for ((bit) = find_first_bit((addr), (size));		\
+	     (bit) < (size);					\
+	     (bit) = find_next_bit((addr), (size), (bit) + 1))
+
+/* same as for_each_set_bit() but use bit as value to start with */
+#define for_each_set_bit_from(bit, addr, size) \
+	for ((bit) = find_next_bit((addr), (size), (bit));	\
+	     (bit) < (size);					\
+	     (bit) = find_next_bit((addr), (size), (bit) + 1))
+
+#define for_each_clear_bit(bit, addr, size) \
+	for ((bit) = find_first_zero_bit((addr), (size));	\
+	     (bit) < (size);					\
+	     (bit) = find_next_zero_bit((addr), (size), (bit) + 1))
+
+/* same as for_each_clear_bit() but use bit as value to start with */
+#define for_each_clear_bit_from(bit, addr, size) \
+	for ((bit) = find_next_zero_bit((addr), (size), (bit));	\
+	     (bit) < (size);					\
+	     (bit) = find_next_zero_bit((addr), (size), (bit) + 1))
+
+unsigned long find_first_bit(const unsigned long *addr,
+			     unsigned long size);
+
+unsigned long find_first_zero_bit(const unsigned long *addr,
+				  unsigned long size);
+
+unsigned long find_last_bit(const unsigned long *addr,
+			    unsigned long size);
+
+unsigned long find_next_bit(const unsigned long *addr,
+			    unsigned long size, unsigned long offset);
+
+unsigned long find_next_zero_bit(const unsigned long *addr,
+				 unsigned long size,
+				 unsigned long offset);
+
+/**
+ * __set_bit - Set a bit in memory
+ * @nr: the bit to set
+ * @addr: the address to start counting from
+ *
+ * This function is non-atomic and may be reordered.
+ */
+static inline void __set_bit(int nr, volatile unsigned long *addr)
+{
+	unsigned long mask = BIT_MASK(nr);
+	unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr);
+
+	*p |= mask;
+}
+
+/**
+ * __clear_bit - Clear a bit in memory
+ * @nr: the bit to clear
+ * @addr: the address to start counting from
+ *
+ * This function is non-atomic and may be reordered.
+ */
+static inline void __clear_bit(int nr, volatile unsigned long *addr)
+{
+	unsigned long mask = BIT_MASK(nr);
+	unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr);
+
+	*p &= ~mask;
+}
+
+/**
+ * __change_bit - Toggle a bit in memory
+ * @nr: the bit to change
+ * @addr: the address to start counting from
+ *
+ * This function is non-atomic and may be reordered.
+ */
+static inline void __change_bit(int nr, volatile unsigned long *addr)
+{
+	unsigned long mask = BIT_MASK(nr);
+	unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr);
+
+	*p ^= mask;
+}
+
+/**
+ * __test_and_set_bit - Set a bit and return its old value
+ * @nr: Bit to set
+ * @addr: Address to count from
+ *
+ * This operation is non-atomic and can be reordered.
+ */
+static inline int __test_and_set_bit(int nr, volatile unsigned long *addr)
+{
+	unsigned long mask = BIT_MASK(nr);
+	unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr);
+	unsigned long old = *p;
+
+	*p = old | mask;
+	return (old & mask) != 0;
+}
+
+/**
+ * __test_and_clear_bit - Clear a bit and return its old value
+ * @nr: Bit to clear
+ * @addr: Address to count from
+ *
+ * This operation is non-atomic and can be reordered.
+ */
+static inline int __test_and_clear_bit(int nr, volatile unsigned long *addr)
+{
+	unsigned long mask = BIT_MASK(nr);
+	unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr);
+	unsigned long old = *p;
+
+	*p = old & ~mask;
+	return (old & mask) != 0;
+}
+
+/**
+ * __test_bit - Determine whether a bit is set
+ * @nr: bit number to test
+ * @addr: Address to start counting from
+ *
+ * This operation is non-atomic and can be reordered.
+ */
+static inline int __test_bit(int nr, const volatile unsigned long *addr)
+{
+	return 1UL & (addr[BIT_WORD(nr)] >> (nr & (BITS_PER_LONG-1)));
+}
+
 #endif

include/sbi/sbi_bits.h

@@ -1,19 +0,0 @@
-/*
- * SPDX-License-Identifier: BSD-2-Clause
- *
- * Copyright (c) 2019 Western Digital Corporation or its affiliates.
- *
- * Authors:
- *   Anup Patel <anup.patel@wdc.com>
- */
-
-#ifndef __SBI_BITS_H__
-#define __SBI_BITS_H__
-
-#define EXTRACT_FIELD(val, which) (((val) & (which)) / ((which) & ~((which)-1)))
-#define INSERT_FIELD(val, which, fieldval) \
-	(((val) & ~(which)) | ((fieldval) * ((which) & ~((which)-1))))
-
-#define BIT_MASK(nr) (1UL << ((nr) % BITS_PER_LONG))
-#define BIT_WORD(nr) ((nr) / BITS_PER_LONG)
-#endif

include/sbi/sbi_console.h

@@ -30,10 +30,9 @@ int __printf(3, 4) sbi_snprintf(char *out, u32 out_sz, const char *format, ...);
 
 int __printf(1, 2) sbi_printf(const char *format, ...);
 
-struct sbi_scratch;
+int __printf(1, 2) sbi_dprintf(const char *format, ...);
 
-int __printf(2, 3) sbi_dprintf(struct sbi_scratch *scratch,
-			       const char *format, ...);
+struct sbi_scratch;
 
 int sbi_console_init(struct sbi_scratch *scratch);
 

include/sbi/sbi_const.h

@@ -10,7 +10,8 @@
 #ifndef __SBI_CONST_H__
 #define __SBI_CONST_H__
 
-/* Some constant macros are used in both assembler and
+/*
+ * Some constant macros are used in both assembler and
  * C code.  Therefore we cannot annotate them always with
  * 'UL' and other type specifiers unilaterally.  We
  * use the following macros to deal with this.
@@ -39,8 +40,8 @@
 #define UL(x)		(_UL(x))
 #define ULL(x)		(_ULL(x))
 
-#define	__STR(s)	#s
-#define	STRINGIFY(s)	__STR(s)
+#define __STR(s)	#s
+#define STRINGIFY(s)	__STR(s)
 
 /* clang-format on */
 

include/sbi/sbi_csr_detect.h

@@ -0,0 +1,50 @@
+/*
+ * SPDX-License-Identifier: BSD-2-Clause
+ *
+ * Copyright (c) 2020 Western Digital Corporation or its affiliates.
+ *
+ * Authors:
+ *   Atish Patra <atish.patra@wdc.com>
+ */
+
+#ifndef __SBI_CSR_DETECT__H
+#define __SBI_CSR_DETECT__H
+
+#include <sbi/riscv_encoding.h>
+#include <sbi/sbi_hart.h>
+
+#define csr_read_allowed(csr_num, trap)					\
+	({								\
+	register ulong tinfo asm("a3") = (ulong)trap;			\
+	register ulong ttmp asm("a4");					\
+	register ulong mtvec = sbi_hart_expected_trap_addr();		\
+	register ulong ret = 0;						\
+	asm volatile(							\
+		"add %[ttmp], %[tinfo], zero\n"				\
+		"csrrw %[mtvec], " STR(CSR_MTVEC) ", %[mtvec]\n"	\
+		"csrr %[ret], %[csr]\n"					\
+		"csrw " STR(CSR_MTVEC) ", %[mtvec]"			\
+	    : [mtvec] "+&r"(mtvec), [tinfo] "+&r"(tinfo),		\
+	      [ttmp] "+&r"(ttmp), [ret] "=&r" (ret)			\
+	    : [csr] "i" (csr_num)					\
+	    : "memory");						\
+	ret;								\
+	})								\
+
+#define csr_write_allowed(csr_num, trap, value)				\
+	({								\
+	register ulong tinfo asm("a3") = (ulong)trap;			\
+	register ulong ttmp asm("a4");					\
+	register ulong mtvec = sbi_hart_expected_trap_addr();		\
+	asm volatile(							\
+		"add %[ttmp], %[tinfo], zero\n"				\
+		"csrrw %[mtvec], " STR(CSR_MTVEC) ", %[mtvec]\n"	\
+		"csrw %[csr], %[val]\n"					\
+		"csrw " STR(CSR_MTVEC) ", %[mtvec]"			\
+	    : [mtvec] "+&r"(mtvec),					\
+	      [tinfo] "+&r"(tinfo), [ttmp] "+&r"(ttmp)			\
+	    : [csr] "i" (csr_num), [val] "r" (value)			\
+	    : "memory");						\
+	})								\
+
+#endif

include/sbi/sbi_ecall.h

@@ -19,16 +19,13 @@
 
 struct sbi_trap_regs;
 struct sbi_trap_info;
-struct sbi_scratch;
 
 struct sbi_ecall_extension {
 	struct sbi_dlist head;
 	unsigned long extid_start;
 	unsigned long extid_end;
-	int (* probe)(struct sbi_scratch *scratch,
-		      unsigned long extid, unsigned long *out_val);
-	int (* handle)(struct sbi_scratch *scratch,
-		       unsigned long extid, unsigned long funcid,
+	int (* probe)(unsigned long extid, unsigned long *out_val);
+	int (* handle)(unsigned long extid, unsigned long funcid,
 		       unsigned long *args, unsigned long *out_val,
 		       struct sbi_trap_info *out_trap);
 };
@@ -39,19 +36,23 @@ extern struct sbi_ecall_extension ecall_time;
 extern struct sbi_ecall_extension ecall_rfence;
 extern struct sbi_ecall_extension ecall_ipi;
 extern struct sbi_ecall_extension ecall_vendor;
+extern struct sbi_ecall_extension ecall_hsm;
 
 u16 sbi_ecall_version_major(void);
 
 u16 sbi_ecall_version_minor(void);
 
+unsigned long sbi_ecall_get_impid(void);
+
+void sbi_ecall_set_impid(unsigned long impid);
+
 struct sbi_ecall_extension *sbi_ecall_find_extension(unsigned long extid);
 
 int sbi_ecall_register_extension(struct sbi_ecall_extension *ext);
 
 void sbi_ecall_unregister_extension(struct sbi_ecall_extension *ext);
 
-int sbi_ecall_handler(u32 hartid, ulong mcause, struct sbi_trap_regs *regs,
-		      struct sbi_scratch *scratch);
+int sbi_ecall_handler(struct sbi_trap_regs *regs);
 
 int sbi_ecall_init(void);
 

include/sbi/sbi_ecall_interface.h

@@ -13,7 +13,7 @@
 /* clang-format off */
 
 /* SBI Extension IDs */
-#define	SBI_EXT_0_1_SET_TIMER			0x0
+#define SBI_EXT_0_1_SET_TIMER			0x0
 #define SBI_EXT_0_1_CONSOLE_PUTCHAR		0x1
 #define SBI_EXT_0_1_CONSOLE_GETCHAR		0x2
 #define SBI_EXT_0_1_CLEAR_IPI			0x3
@@ -26,15 +26,16 @@
 #define SBI_EXT_TIME				0x54494D45
 #define SBI_EXT_IPI				0x735049
 #define SBI_EXT_RFENCE				0x52464E43
+#define SBI_EXT_HSM				0x48534D
 
 /* SBI function IDs for BASE extension*/
 #define SBI_EXT_BASE_GET_SPEC_VERSION		0x0
 #define SBI_EXT_BASE_GET_IMP_ID			0x1
-#define	SBI_EXT_BASE_GET_IMP_VERSION		0x2
-#define	SBI_EXT_BASE_PROBE_EXT			0x3
-#define	SBI_EXT_BASE_GET_MVENDORID		0x4
-#define	SBI_EXT_BASE_GET_MARCHID		0x5
-#define	SBI_EXT_BASE_GET_MIMPID			0x6
+#define SBI_EXT_BASE_GET_IMP_VERSION		0x2
+#define SBI_EXT_BASE_PROBE_EXT			0x3
+#define SBI_EXT_BASE_GET_MVENDORID		0x4
+#define SBI_EXT_BASE_GET_MARCHID		0x5
+#define SBI_EXT_BASE_GET_MIMPID			0x6
 
 /* SBI function IDs for TIME extension*/
 #define SBI_EXT_TIME_SET_TIMER			0x0
@@ -43,7 +44,7 @@
 #define SBI_EXT_IPI_SEND_IPI			0x0
 
 /* SBI function IDs for RFENCE extension*/
-#define	SBI_EXT_RFENCE_REMOTE_FENCE_I		0x0
+#define SBI_EXT_RFENCE_REMOTE_FENCE_I		0x0
 #define SBI_EXT_RFENCE_REMOTE_SFENCE_VMA	0x1
 #define SBI_EXT_RFENCE_REMOTE_SFENCE_VMA_ASID	0x2
 #define SBI_EXT_RFENCE_REMOTE_HFENCE_GVMA	0x3
@@ -51,11 +52,35 @@
 #define SBI_EXT_RFENCE_REMOTE_HFENCE_VVMA	0x5
 #define SBI_EXT_RFENCE_REMOTE_HFENCE_VVMA_ASID	0x6
 
-#define SBI_SPEC_VERSION_MAJOR_OFFSET	24
-#define SBI_SPEC_VERSION_MAJOR_MASK	0x7f
-#define SBI_SPEC_VERSION_MINOR_MASK	0xffffff
-#define SBI_EXT_VENDOR_START		0x09000000
-#define SBI_EXT_VENDOR_END		0x09FFFFFF
+/* SBI function IDs for HSM extension */
+#define SBI_EXT_HSM_HART_START			0x0
+#define SBI_EXT_HSM_HART_STOP			0x1
+#define SBI_EXT_HSM_HART_GET_STATUS		0x2
+
+#define SBI_HSM_HART_STATUS_STARTED		0x0
+#define SBI_HSM_HART_STATUS_STOPPED		0x1
+#define SBI_HSM_HART_STATUS_START_PENDING	0x2
+#define SBI_HSM_HART_STATUS_STOP_PENDING	0x3
+
+#define SBI_SPEC_VERSION_MAJOR_OFFSET		24
+#define SBI_SPEC_VERSION_MAJOR_MASK		0x7f
+#define SBI_SPEC_VERSION_MINOR_MASK		0xffffff
+#define SBI_EXT_VENDOR_START			0x09000000
+#define SBI_EXT_VENDOR_END			0x09FFFFFF
+#define SBI_EXT_FIRMWARE_START			0x0A000000
+#define SBI_EXT_FIRMWARE_END			0x0AFFFFFF
+
+/* SBI return error codes */
+#define SBI_SUCCESS				0
+#define SBI_ERR_FAILED				-1
+#define SBI_ERR_NOT_SUPPORTED			-2
+#define SBI_ERR_INVALID_PARAM			-3
+#define SBI_ERR_DENIED				-4
+#define SBI_ERR_INVALID_ADDRESS			-5
+#define SBI_ERR_ALREADY_AVAILABLE		-6
+
+#define SBI_LAST_ERR				SBI_ERR_ALREADY_AVAILABLE
+
 /* clang-format on */
 
 #endif

include/sbi/sbi_emulate_csr.h

@@ -13,12 +13,11 @@
 #include <sbi/sbi_types.h>
 
 struct sbi_trap_regs;
-struct sbi_scratch;
 
-int sbi_emulate_csr_read(int csr_num, u32 hartid, struct sbi_trap_regs *regs,
-			 struct sbi_scratch *scratch, ulong *csr_val);
+int sbi_emulate_csr_read(int csr_num, struct sbi_trap_regs *regs,
+			 ulong *csr_val);
 
-int sbi_emulate_csr_write(int csr_num, u32 hartid, struct sbi_trap_regs *regs,
-			  struct sbi_scratch *scratch, ulong csr_val);
+int sbi_emulate_csr_write(int csr_num, struct sbi_trap_regs *regs,
+			  ulong csr_val);
 
 #endif

include/sbi/sbi_error.h

@@ -10,24 +10,28 @@
 #ifndef __SBI_ERROR_H__
 #define __SBI_ERROR_H__
 
+#include <sbi/sbi_ecall_interface.h>
+
 /* clang-format off */
 
-#define SBI_OK		0
-#define SBI_EFAIL	-1
-#define SBI_ENOTSUPP	-2
-#define SBI_EINVAL	-3
-#define SBI_DENIED	-4
-#define SBI_INVALID_ADDR -5
-#define SBI_ENODEV	-6
-#define SBI_ENOSYS	-7
-#define SBI_ETIMEDOUT	-8
-#define SBI_EIO		-9
-#define SBI_EILL	-10
-#define SBI_ENOSPC	-11
-#define SBI_ENOMEM	-12
-#define SBI_ETRAP	-13
-#define SBI_EUNKNOWN	-14
-#define SBI_ENOENT	-15
+#define SBI_OK			0
+#define SBI_EFAIL		SBI_ERR_FAILED
+#define SBI_ENOTSUPP		SBI_ERR_NOT_SUPPORTED
+#define SBI_EINVAL		SBI_ERR_INVALID_PARAM
+#define SBI_EDENIED		SBI_ERR_DENIED
+#define SBI_EINVALID_ADDR	SBI_ERR_INVALID_ADDRESS
+#define SBI_EALREADY		SBI_ERR_ALREADY_AVAILABLE
+
+#define SBI_ENODEV		-1000
+#define SBI_ENOSYS		-1001
+#define SBI_ETIMEDOUT		-1002
+#define SBI_EIO			-1003
+#define SBI_EILL		-1004
+#define SBI_ENOSPC		-1005
+#define SBI_ENOMEM		-1006
+#define SBI_ETRAP		-1007
+#define SBI_EUNKNOWN		-1008
+#define SBI_ENOENT		-1009
 
 /* clang-format on */
 

include/sbi/sbi_hart.h

@@ -12,16 +12,42 @@
 
 #include <sbi/sbi_types.h>
 
+/** Possible feature flags of a hart */
+enum sbi_hart_features {
+	/** Hart has PMP support */
+	SBI_HART_HAS_PMP = (1 << 0),
+	/** Hart has S-mode counter enable */
+	SBI_HART_HAS_SCOUNTEREN = (1 << 1),
+	/** Hart has M-mode counter enable */
+	SBI_HART_HAS_MCOUNTEREN = (1 << 2),
+	/** HART has timer csr implementation in hardware */
+	SBI_HART_HAS_TIME = (1 << 3),
+
+	/** Last index of Hart features*/
+	SBI_HART_HAS_LAST_FEATURE = SBI_HART_HAS_TIME,
+};
+
 struct sbi_scratch;
 
 int sbi_hart_init(struct sbi_scratch *scratch, u32 hartid, bool cold_boot);
 
-void *sbi_hart_get_trap_info(struct sbi_scratch *scratch);
-
-void sbi_hart_set_trap_info(struct sbi_scratch *scratch, void *data);
+extern void (*sbi_hart_expected_trap)(void);
+static inline ulong sbi_hart_expected_trap_addr(void)
+{
+	return (ulong)sbi_hart_expected_trap;
+}
 
 void sbi_hart_delegation_dump(struct sbi_scratch *scratch);
+unsigned int sbi_hart_pmp_count(struct sbi_scratch *scratch);
+int sbi_hart_pmp_get(struct sbi_scratch *scratch, unsigned int n,
+		     unsigned long *prot_out, unsigned long *addr_out,
+		     unsigned long *size);
 void sbi_hart_pmp_dump(struct sbi_scratch *scratch);
+int  sbi_hart_pmp_check_addr(struct sbi_scratch *scratch, unsigned long daddr,
+			     unsigned long attr);
+bool sbi_hart_has_feature(struct sbi_scratch *scratch, unsigned long feature);
+void sbi_hart_get_features_str(struct sbi_scratch *scratch,
+			       char *features_str, int nfstr);
 
 void __attribute__((noreturn)) sbi_hart_hang(void);
 
@@ -30,19 +56,4 @@ sbi_hart_switch_mode(unsigned long arg0, unsigned long arg1,
 		     unsigned long next_addr, unsigned long next_mode,
 		     bool next_virt);
 
-void sbi_hart_mark_available(u32 hartid);
-
-ulong sbi_hart_available_mask(void);
-
-void sbi_hart_unmark_available(u32 hartid);
-
-struct sbi_scratch *sbi_hart_id_to_scratch(struct sbi_scratch *scratch,
-					   u32 hartid);
-
-void sbi_hart_wait_for_coldboot(struct sbi_scratch *scratch, u32 hartid);
-
-void sbi_hart_wake_coldboot_harts(struct sbi_scratch *scratch, u32 hartid);
-
-u32 sbi_current_hartid(void);
-
 #endif

include/sbi/sbi_hartmask.h

@@ -0,0 +1,141 @@
+/*
+ * SPDX-License-Identifier: BSD-2-Clause
+ *
+ * Copyright (c) 2020 Western Digital Corporation or its affiliates.
+ *
+ * Authors:
+ *   Anup Patel <anup.patel@wdc.com>
+ */
+
+#ifndef __SBI_HARTMASK_H__
+#define __SBI_HARTMASK_H__
+
+#include <sbi/sbi_bitmap.h>
+
+/**
+ * Maximum number of bits in a hartmask
+ *
+ * The hartmask is indexed using physical HART id so this define
+ * also represents the maximum number of HART ids generic OpenSBI
+ * can handle.
+ */
+#define SBI_HARTMASK_MAX_BITS		128
+
+/** Representation of hartmask */
+struct sbi_hartmask {
+	DECLARE_BITMAP(bits, SBI_HARTMASK_MAX_BITS);
+};
+
+/** Initialize hartmask to zero */
+#define SBI_HARTMASK_INIT(__m)		\
+	bitmap_zero(((__m)->bits), SBI_HARTMASK_MAX_BITS)
+
+/** Initialize hartmask to zero except a particular HART id */
+#define SBI_HARTMASK_INIT_EXCEPT(__m, __h)	\
+	bitmap_zero_except(((__m)->bits), (__h), SBI_HARTMASK_MAX_BITS)
+
+/**
+ * Get underlying bitmap of hartmask
+ * @param m the hartmask pointer
+ */
+#define sbi_hartmask_bits(__m)		((__m)->bits)
+
+/**
+ * Set a HART in hartmask
+ * @param h HART id to set
+ * @param m the hartmask pointer
+ */
+static inline void sbi_hartmask_set_hart(u32 h, struct sbi_hartmask *m)
+{
+	if (h < SBI_HARTMASK_MAX_BITS)
+		__set_bit(h, m->bits);
+}
+
+/**
+ * Clear a HART in hartmask
+ * @param h HART id to clear
+ * @param m the hartmask pointer
+ */
+static inline void sbi_hartmask_clear_hart(u32 h, struct sbi_hartmask *m)
+{
+	if (h < SBI_HARTMASK_MAX_BITS)
+		__clear_bit(h, m->bits);
+}
+
+/**
+ * Test a HART in hartmask
+ * @param h HART id to test
+ * @param m the hartmask pointer
+ */
+static inline int sbi_hartmask_test_hart(u32 h, struct sbi_hartmask *m)
+{
+	if (h < SBI_HARTMASK_MAX_BITS)
+		return __test_bit(h, m->bits);
+	return 0;
+}
+
+/**
+ * Set all HARTs in a hartmask
+ * @param dstp the hartmask pointer
+ */
+static inline void sbi_hartmask_set_all(struct sbi_hartmask *dstp)
+{
+	bitmap_fill(sbi_hartmask_bits(dstp), SBI_HARTMASK_MAX_BITS);
+}
+
+/**
+ * Clear all HARTs in a hartmask
+ * @param dstp the hartmask pointer
+ */
+static inline void sbi_hartmask_clear_all(struct sbi_hartmask *dstp)
+{
+	bitmap_zero(sbi_hartmask_bits(dstp), SBI_HARTMASK_MAX_BITS);
+}
+
+/**
+ * *dstp = *src1p & *src2p
+ * @param dstp the hartmask result
+ * @param src1p the first input
+ * @param src2p the second input
+ */
+static inline void sbi_hartmask_and(struct sbi_hartmask *dstp,
+				    const struct sbi_hartmask *src1p,
+				    const struct sbi_hartmask *src2p)
+{
+	bitmap_and(sbi_hartmask_bits(dstp), sbi_hartmask_bits(src1p),
+		   sbi_hartmask_bits(src2p), SBI_HARTMASK_MAX_BITS);
+}
+
+/**
+ * *dstp = *src1p | *src2p
+ * @param dstp the hartmask result
+ * @param src1p the first input
+ * @param src2p the second input
+ */
+static inline void sbi_hartmask_or(struct sbi_hartmask *dstp,
+				   const struct sbi_hartmask *src1p,
+				   const struct sbi_hartmask *src2p)
+{
+	bitmap_or(sbi_hartmask_bits(dstp), sbi_hartmask_bits(src1p),
+		  sbi_hartmask_bits(src2p), SBI_HARTMASK_MAX_BITS);
+}
+
+/**
+ * *dstp = *src1p ^ *src2p
+ * @param dstp the hartmask result
+ * @param src1p the first input
+ * @param src2p the second input
+ */
+static inline void sbi_hartmask_xor(struct sbi_hartmask *dstp,
+				    const struct sbi_hartmask *src1p,
+				    const struct sbi_hartmask *src2p)
+{
+	bitmap_xor(sbi_hartmask_bits(dstp), sbi_hartmask_bits(src1p),
+		   sbi_hartmask_bits(src2p), SBI_HARTMASK_MAX_BITS);
+}
+
+/** Iterate over each HART in hartmask */
+#define sbi_hartmask_for_each_hart(__h, __m)	\
+	for_each_set_bit(__h, (__m)->bits, SBI_HARTMASK_MAX_BITS)
+
+#endif

include/sbi/sbi_hfence.h

@@ -10,8 +10,9 @@
 
 #ifndef __SBI_FENCE_H__
 #define __SBI_FENCE_H__
+
 /** Invalidate Stage2 TLBs for given VMID and guest physical address */
-void __sbi_hfence_gvma_vmid_gpa(unsigned long vmid, unsigned long gpa);
+void __sbi_hfence_gvma_vmid_gpa(unsigned long gpa, unsigned long vmid);
 
 /** Invalidate Stage2 TLBs for given VMID */
 void __sbi_hfence_gvma_vmid(unsigned long vmid);
@@ -23,7 +24,7 @@ void __sbi_hfence_gvma_gpa(unsigned long gpa);
 void __sbi_hfence_gvma_all(void);
 
 /** Invalidate unified TLB entries for given asid and guest virtual address */
-void __sbi_hfence_vvma_asid_va(unsigned long asid, unsigned long va);
+void __sbi_hfence_vvma_asid_va(unsigned long va, unsigned long asid);
 
 /** Invalidate unified TLB entries for given ASID for a guest*/
 void __sbi_hfence_vvma_asid(unsigned long asid);
@@ -33,4 +34,5 @@ void __sbi_hfence_vvma_va(unsigned long va);
 
 /** Invalidate all possible Stage2 TLBs */
 void __sbi_hfence_vvma_all(void);
+
 #endif

include/sbi/sbi_hsm.h

@@ -0,0 +1,36 @@
+/*
+ * SPDX-License-Identifier: BSD-2-Clause
+ *
+ * Copyright (c) 2020 Western Digital Corporation or its affiliates.
+ *
+ * Authors:
+ *   Atish Patra <atish.patra@wdc.com>
+ */
+
+#ifndef __SBI_HSM_H__
+#define __SBI_HSM_H__
+
+#include <sbi/sbi_types.h>
+
+/** Hart state values **/
+#define SBI_HART_STOPPED	0
+#define SBI_HART_STOPPING	1
+#define SBI_HART_STARTING	2
+#define SBI_HART_STARTED	3
+#define SBI_HART_UNKNOWN	4
+
+struct sbi_scratch;
+
+int sbi_hsm_init(struct sbi_scratch *scratch, u32 hartid, bool cold_boot);
+void __noreturn sbi_hsm_exit(struct sbi_scratch *scratch);
+
+int sbi_hsm_hart_start(struct sbi_scratch *scratch, u32 hartid,
+		       ulong saddr, ulong priv);
+int sbi_hsm_hart_stop(struct sbi_scratch *scratch, bool exitnow);
+int sbi_hsm_hart_get_state(u32 hartid);
+int sbi_hsm_hart_state_to_status(int state);
+bool sbi_hsm_hart_started(u32 hartid);
+int sbi_hsm_hart_started_mask(ulong hbase, ulong *out_hmask);
+void sbi_hsm_prepare_next_jump(struct sbi_scratch *scratch, u32 hartid);
+
+#endif

include/sbi/sbi_illegal_insn.h

@@ -13,10 +13,7 @@
 #include <sbi/sbi_types.h>
 
 struct sbi_trap_regs;
-struct sbi_scratch;
 
-int sbi_illegal_insn_handler(u32 hartid, ulong mcause, ulong insn,
-			     struct sbi_trap_regs *regs,
-			     struct sbi_scratch *scratch);
+int sbi_illegal_insn_handler(ulong insn, struct sbi_trap_regs *regs);
 
 #endif

include/sbi/sbi_ipi.h

@@ -25,41 +25,43 @@ struct sbi_ipi_event_ops {
 	/** Name of the IPI event operations */
 	char name[32];
 
-	/** Update callback to save/enqueue data for remote HART
-	 *  Note: This is an optional callback and it is called just before
-	 *  triggering IPI to remote HART.
+	/**
+	 * Update callback to save/enqueue data for remote HART
+	 * Note: This is an optional callback and it is called just before
+	 * triggering IPI to remote HART.
 	 */
 	int (* update)(struct sbi_scratch *scratch,
 			struct sbi_scratch *remote_scratch,
 			u32 remote_hartid, void *data);
 
-	/** Sync callback to wait for remote HART
-	 *  Note: This is an optional callback and it is called just after
-	 *  triggering IPI to remote HART.
+	/**
+	 * Sync callback to wait for remote HART
+	 * Note: This is an optional callback and it is called just after
+	 * triggering IPI to remote HART.
 	 */
 	void (* sync)(struct sbi_scratch *scratch);
 
-	/** Process callback to handle IPI event
-	 *  Note: This is a mandatory callback and it is called on the
-	 *  remote HART after IPI is triggered.
+	/**
+	 * Process callback to handle IPI event
+	 * Note: This is a mandatory callback and it is called on the
+	 * remote HART after IPI is triggered.
 	 */
 	void (* process)(struct sbi_scratch *scratch);
 };
 
-int sbi_ipi_send_many(struct sbi_scratch *scratch, ulong hmask,
-		      ulong hbase, u32 event, void *data);
+int sbi_ipi_send_many(ulong hmask, ulong hbase, u32 event, void *data);
 
 int sbi_ipi_event_create(const struct sbi_ipi_event_ops *ops);
 
 void sbi_ipi_event_destroy(u32 event);
 
-int sbi_ipi_send_smode(struct sbi_scratch *scratch, ulong hmask, ulong hbase);
+int sbi_ipi_send_smode(ulong hmask, ulong hbase);
 
-void sbi_ipi_clear_smode(struct sbi_scratch *scratch);
+void sbi_ipi_clear_smode(void);
 
-int sbi_ipi_send_halt(struct sbi_scratch *scratch, ulong hmask, ulong hbase);
+int sbi_ipi_send_halt(ulong hmask, ulong hbase);
 
-void sbi_ipi_process(struct sbi_scratch *scratch);
+void sbi_ipi_process(void);
 
 int sbi_ipi_init(struct sbi_scratch *scratch, bool cold_boot);
 

include/sbi/sbi_math.h

@@ -0,0 +1,15 @@
+/*
+ * SPDX-License-Identifier: BSD-2-Clause
+ *
+ * Copyright (c) 2020 Western Digital Corporation or its affiliates.
+ *
+ * Authors:
+ *   Atish Patra <atish.patra@wdc.com>
+ */
+
+#ifndef __SBI_MATH_H__
+#define __SBI_MATH_H__
+
+unsigned long log2roundup(unsigned long x);
+
+#endif

include/sbi/sbi_misaligned_ldst.h

@@ -13,16 +13,11 @@
 #include <sbi/sbi_types.h>
 
 struct sbi_trap_regs;
-struct sbi_scratch;
 
-int sbi_misaligned_load_handler(u32 hartid, ulong mcause,
-				ulong addr, ulong tval2, ulong tinst,
-				struct sbi_trap_regs *regs,
-				struct sbi_scratch *scratch);
+int sbi_misaligned_load_handler(ulong addr, ulong tval2, ulong tinst,
+				struct sbi_trap_regs *regs);
 
-int sbi_misaligned_store_handler(u32 hartid, ulong mcause,
-				 ulong addr, ulong tval2, ulong tinst,
-				 struct sbi_trap_regs *regs,
-				 struct sbi_scratch *scratch);
+int sbi_misaligned_store_handler(ulong addr, ulong tval2, ulong tinst,
+				 struct sbi_trap_regs *regs);
 
 #endif

include/sbi/sbi_platform.h

@@ -10,9 +10,10 @@
 #ifndef __SBI_PLATFORM_H__
 #define __SBI_PLATFORM_H__
 
-/** OpenSBI 32-bit platform version with:
- *  1. upper 16-bits as major number
- *  2. lower 16-bits as minor number
+/**
+ * OpenSBI 32-bit platform version with:
+ * 1. upper 16-bits as major number
+ * 2. lower 16-bits as minor number
  */
 #define SBI_PLATFORM_VERSION(Major, Minor) ((Major << 16) | Minor)
 
@@ -28,12 +29,12 @@
 #define SBI_PLATFORM_HART_COUNT_OFFSET (0x50)
 /** Offset of hart_stack_size in struct sbi_platform */
 #define SBI_PLATFORM_HART_STACK_SIZE_OFFSET (0x54)
-/** Offset of disabled_hart_mask in struct sbi_platform */
-#define SBI_PLATFORM_DISABLED_HART_OFFSET (0x58)
 /** Offset of platform_ops_addr in struct sbi_platform */
-#define SBI_PLATFORM_OPS_OFFSET (0x60)
+#define SBI_PLATFORM_OPS_OFFSET (0x58)
 /** Offset of firmware_context in struct sbi_platform */
-#define SBI_PLATFORM_FIRMWARE_CONTEXT_OFFSET (0x60 + __SIZEOF_POINTER__)
+#define SBI_PLATFORM_FIRMWARE_CONTEXT_OFFSET (0x58 + __SIZEOF_POINTER__)
+/** Offset of hart_index2id in struct sbi_platform */
+#define SBI_PLATFORM_HART_INDEX2ID_OFFSET (0x58 + (__SIZEOF_POINTER__ * 2))
 
 #define SBI_PLATFORM_TLB_RANGE_FLUSH_LIMIT_DEFAULT		(1UL << 12)
 
@@ -51,21 +52,18 @@ enum sbi_platform_features {
 	SBI_PLATFORM_HAS_TIMER_VALUE = (1 << 0),
 	/** Platform has HART hotplug support */
 	SBI_PLATFORM_HAS_HART_HOTPLUG = (1 << 1),
-	/** Platform has PMP support */
-	SBI_PLATFORM_HAS_PMP = (1 << 2),
-	/** Platform has S-mode counter enable */
-	SBI_PLATFORM_HAS_SCOUNTEREN = (1 << 3),
-	/** Platform has M-mode counter enable */
-	SBI_PLATFORM_HAS_MCOUNTEREN = (1 << 4),
 	/** Platform has fault delegation support */
-	SBI_PLATFORM_HAS_MFAULTS_DELEGATION = (1 << 5),
+	SBI_PLATFORM_HAS_MFAULTS_DELEGATION = (1 << 2),
+	/** Platform has custom secondary hart booting support */
+	SBI_PLATFORM_HAS_HART_SECONDARY_BOOT = (1 << 3),
+
+	/** Last index of Platform features*/
+	SBI_PLATFORM_HAS_LAST_FEATURE = SBI_PLATFORM_HAS_HART_SECONDARY_BOOT,
 };
 
 /** Default feature set for a platform */
 #define SBI_PLATFORM_DEFAULT_FEATURES                                \
-	(SBI_PLATFORM_HAS_TIMER_VALUE | SBI_PLATFORM_HAS_PMP |       \
-	 SBI_PLATFORM_HAS_SCOUNTEREN | SBI_PLATFORM_HAS_MCOUNTEREN | \
-	 SBI_PLATFORM_HAS_MFAULTS_DELEGATION)
+	(SBI_PLATFORM_HAS_TIMER_VALUE | SBI_PLATFORM_HAS_MFAULTS_DELEGATION)
 
 /** Platform functions */
 struct sbi_platform_operations {
@@ -79,12 +77,14 @@ struct sbi_platform_operations {
 	/** Platform final exit */
 	void (*final_exit)(void);
 
-	/** For platforms that do not implement misa, non-standard
+	/**
+	 * For platforms that do not implement misa, non-standard
 	 * methods are needed to determine cpu extension.
 	 */
 	int (*misa_check_extension)(char ext);
 
-	/** For platforms that do not implement misa, non-standard
+	/**
+	 * For platforms that do not implement misa, non-standard
 	 * methods are needed to get MXL field of misa.
 	 */
 	int (*misa_get_xlen)(void);
@@ -133,10 +133,19 @@ struct sbi_platform_operations {
 	/** Exit platform timer for current HART */
 	void (*timer_exit)(void);
 
-	/** Reboot the platform */
-	int (*system_reboot)(u32 type);
-	/** Shutdown or poweroff the platform */
-	int (*system_shutdown)(u32 type);
+	/** Bringup the given hart */
+	int (*hart_start)(u32 hartid, ulong saddr);
+	/**
+	 * Stop the current hart from running. This call doesn't expect to
+	 * return if success.
+	 */
+	int (*hart_stop)(void);
+
+	/** Reset the platform */
+#define SBI_PLATFORM_RESET_SHUTDOWN	0
+#define SBI_PLATFORM_RESET_COLD		1
+#define SBI_PLATFORM_RESET_WARM		2
+	int (*system_reset)(u32 reset_type);
 
 	/** platform specific SBI extension implementation probe function */
 	int (*vendor_ext_check)(long extid);
@@ -147,6 +156,9 @@ struct sbi_platform_operations {
 				   struct sbi_trap_info *out_trap);
 } __packed;
 
+/** Platform default per-HART stack size for exception/interrupt handling */
+#define SBI_PLATFORM_DEFAULT_HART_STACK_SIZE	8192
+
 /** Representation of a platform */
 struct sbi_platform {
 	/**
@@ -169,12 +181,26 @@ struct sbi_platform {
 	u32 hart_count;
 	/** Per-HART stack size for exception/interrupt handling */
 	u32 hart_stack_size;
-	/** Mask representing the set of disabled HARTs */
-	u64 disabled_hart_mask;
 	/** Pointer to sbi platform operations */
 	unsigned long platform_ops_addr;
 	/** Pointer to system firmware specific context */
 	unsigned long firmware_context;
+	/**
+	 * HART index to HART id table
+	 *
+	 * For used HART index <abc>:
+	 *     hart_index2id[<abc>] = some HART id
+	 * For unused HART index <abc>:
+	 *     hart_index2id[<abc>] = -1U
+	 *
+	 * If hart_index2id == NULL then we assume identity mapping
+	 *     hart_index2id[<abc>] = <abc>
+	 *
+	 * We have only two restrictions:
+	 * 1. HART index < sbi_platform hart_count
+	 * 2. HART id < SBI_HARTMASK_MAX_BITS
+	 */
+	const u32 *hart_index2id;
 } __packed;
 
 /** Get pointer to sbi_platform for sbi_scratch pointer */
@@ -193,17 +219,34 @@ struct sbi_platform {
 /** Check whether the platform supports HART hotplug */
 #define sbi_platform_has_hart_hotplug(__p) \
 	((__p)->features & SBI_PLATFORM_HAS_HART_HOTPLUG)
-/** Check whether the platform has PMP support */
-#define sbi_platform_has_pmp(__p) ((__p)->features & SBI_PLATFORM_HAS_PMP)
-/** Check whether the platform supports scounteren CSR */
-#define sbi_platform_has_scounteren(__p) \
-	((__p)->features & SBI_PLATFORM_HAS_SCOUNTEREN)
-/** Check whether the platform supports mcounteren CSR */
-#define sbi_platform_has_mcounteren(__p) \
-	((__p)->features & SBI_PLATFORM_HAS_MCOUNTEREN)
 /** Check whether the platform supports fault delegation */
 #define sbi_platform_has_mfaults_delegation(__p) \
 	((__p)->features & SBI_PLATFORM_HAS_MFAULTS_DELEGATION)
+/** Check whether the platform supports custom secondary hart booting support */
+#define sbi_platform_has_hart_secondary_boot(__p) \
+	((__p)->features & SBI_PLATFORM_HAS_HART_SECONDARY_BOOT)
+
+/**
+ * Get HART index for the given HART
+ *
+ * @param plat pointer to struct sbi_platform
+ * @param hartid HART ID
+ *
+ * @return 0 <= value < hart_count for valid HART otherwise -1U
+ */
+u32 sbi_platform_hart_index(const struct sbi_platform *plat, u32 hartid);
+
+/**
+ * Get the platform features in string format
+ *
+ * @param plat pointer to struct sbi_platform
+ * @param features_str pointer to a char array where the features string will be
+ *		       updated
+ * @param nfstr length of the features_str. The feature string will be truncated
+ *		if nfstr is not long enough.
+ */
+void sbi_platform_get_features_str(const struct sbi_platform *plat,
+				   char *features_str, int nfstr);
 
 /**
  * Get name of the platform
@@ -220,19 +263,18 @@ static inline const char *sbi_platform_name(const struct sbi_platform *plat)
 }
 
 /**
- * Check whether the given HART is disabled
+ * Get the platform features
  *
  * @param plat pointer to struct sbi_platform
- * @param hartid HART ID
  *
- * @return TRUE if HART is disabled and FALSE otherwise
+ * @return the features value currently set for the given platform
  */
-static inline bool sbi_platform_hart_disabled(const struct sbi_platform *plat,
-					      u32 hartid)
+static inline unsigned long sbi_platform_get_features(
+						const struct sbi_platform *plat)
 {
-	if (plat && (plat->disabled_hart_mask & (1 << hartid)))
-		return TRUE;
-	return FALSE;
+	if (plat)
+		return plat->features;
+	return 0;
 }
 
 /**
@@ -279,6 +321,57 @@ static inline u32 sbi_platform_hart_stack_size(const struct sbi_platform *plat)
 	return 0;
 }
 
+/**
+ * Check whether given HART is invalid
+ *
+ * @param plat pointer to struct sbi_platform
+ * @param hartid HART ID
+ *
+ * @return TRUE if HART is invalid and FALSE otherwise
+ */
+static inline bool sbi_platform_hart_invalid(const struct sbi_platform *plat,
+					     u32 hartid)
+{
+	if (!plat)
+		return TRUE;
+	if (plat->hart_count <= sbi_platform_hart_index(plat, hartid))
+		return TRUE;
+	return FALSE;
+}
+
+/**
+ * Bringup a given hart from previous stage. Platform should implement this
+ * operation if they support a custom mechanism to start a hart. Otherwise,
+ * a generic WFI based approach will be used to start/stop a hart in OpenSBI.
+ *
+ * @param plat pointer to struct sbi_platform
+ * @param hartid HART id
+ * @param saddr M-mode start physical address for the HART
+ *
+ * @return 0 if sucessful and negative error code on failure
+ */
+static inline int sbi_platform_hart_start(const struct sbi_platform *plat,
+					  u32 hartid, ulong saddr)
+{
+	if (plat && sbi_platform_ops(plat)->hart_start)
+		return sbi_platform_ops(plat)->hart_start(hartid, saddr);
+	return SBI_ENOTSUPP;
+}
+
+/**
+ * Stop the current hart in OpenSBI.
+ *
+ * @param plat pointer to struct sbi_platform
+ *
+ * @return Negative error code on failure. It doesn't return on success.
+ */
+static inline int sbi_platform_hart_stop(const struct sbi_platform *plat)
+{
+	if (plat && sbi_platform_ops(plat)->hart_stop)
+		return sbi_platform_ops(plat)->hart_stop();
+	return SBI_ENOTSUPP;
+}
+
 /**
  * Early initialization for current HART
  *
@@ -398,8 +491,9 @@ static inline int sbi_platform_pmp_region_info(const struct sbi_platform *plat,
 						ulong *log2size)
 {
 	if (plat && sbi_platform_ops(plat)->pmp_region_info)
-		return sbi_platform_ops(plat)->pmp_region_info(hartid, index, prot, addr,
-                                                                              log2size);
+		return sbi_platform_ops(plat)->pmp_region_info(hartid, index,
+							       prot, addr,
+							       log2size);
 	return 0;
 }
 
@@ -591,34 +685,18 @@ static inline void sbi_platform_timer_exit(const struct sbi_platform *plat)
 }
 
 /**
- * Reboot the platform
+ * Reset the platform
  *
  * @param plat pointer to struct sbi_platform
- * @param type type of reboot
+ * @param reset_type type of reset
  *
  * @return 0 on success and negative error code on failure
  */
-static inline int sbi_platform_system_reboot(const struct sbi_platform *plat,
-					     u32 type)
+static inline int sbi_platform_system_reset(const struct sbi_platform *plat,
+					    u32 reset_type)
 {
-	if (plat && sbi_platform_ops(plat)->system_reboot)
-		return sbi_platform_ops(plat)->system_reboot(type);
-	return 0;
-}
-
-/**
- * Shutdown or poweroff the platform
- *
- * @param plat pointer to struct sbi_platform
- * @param type type of shutdown or poweroff
- *
- * @return 0 on success and negative error code on failure
- */
-static inline int sbi_platform_system_shutdown(const struct sbi_platform *plat,
-					       u32 type)
-{
-	if (plat && sbi_platform_ops(plat)->system_shutdown)
-		return sbi_platform_ops(plat)->system_shutdown(type);
+	if (plat && sbi_platform_ops(plat)->system_reset)
+		return sbi_platform_ops(plat)->system_reset(reset_type);
 	return 0;
 }
 

include/sbi/sbi_scratch.h

@@ -36,8 +36,8 @@
 #define SBI_SCRATCH_OPTIONS_OFFSET		(9 * __SIZEOF_POINTER__)
 /** Offset of extra space in sbi_scratch */
 #define SBI_SCRATCH_EXTRA_SPACE_OFFSET		(10 * __SIZEOF_POINTER__)
-/** Maximum size of sbi_scratch */
-#define SBI_SCRATCH_SIZE			(64 * __SIZEOF_POINTER__)
+/** Maximum size of sbi_scratch (4KB) */
+#define SBI_SCRATCH_SIZE			(0x1000)
 
 /* clang-format on */
 
@@ -85,7 +85,11 @@ enum sbi_scratch_options {
 #define sbi_scratch_thishart_arg1_ptr() \
 	((void *)(sbi_scratch_thishart_ptr()->next_arg1))
 
-/** Allocate from extra space in sbi_scratch
+/** Initialize scatch table and allocator */
+int sbi_scratch_init(struct sbi_scratch *scratch);
+
+/**
+ * Allocate from extra space in sbi_scratch
  *
  * @return zero on failure and non-zero (>= SBI_SCRATCH_EXTRA_SPACE_OFFSET)
  * on success
@@ -102,6 +106,19 @@ void sbi_scratch_free_offset(unsigned long offset);
 #define sbi_scratch_thishart_offset_ptr(offset)	\
 	((void *)sbi_scratch_thishart_ptr() + (offset))
 
+/** HART id to scratch table */
+extern struct sbi_scratch *hartid_to_scratch_table[];
+
+/** Get sbi_scratch from HART id */
+#define sbi_hartid_to_scratch(__hartid) \
+	hartid_to_scratch_table[__hartid]
+
+/** Last HART id having a sbi_scratch pointer */
+extern u32 last_hartid_having_scratch;
+
+/** Get last HART id having a sbi_scratch pointer */
+#define sbi_scratch_last_hartid()	last_hartid_having_scratch
+
 #endif
 
 #endif

include/sbi/sbi_system.h

@@ -12,18 +12,6 @@
 
 #include <sbi/sbi_types.h>
 
-struct sbi_scratch;
-
-int sbi_system_early_init(struct sbi_scratch *scratch, bool cold_boot);
-
-int sbi_system_final_init(struct sbi_scratch *scratch, bool cold_boot);
-
-void sbi_system_early_exit(struct sbi_scratch *scratch);
-
-void sbi_system_final_exit(struct sbi_scratch *scratch);
-
-void __noreturn sbi_system_reboot(struct sbi_scratch *scratch, u32 type);
-
-void __noreturn sbi_system_shutdown(struct sbi_scratch *scratch, u32 type);
+void __noreturn sbi_system_reset(u32 platform_reset_type);
 
 #endif

include/sbi/sbi_timer.h

@@ -14,22 +14,31 @@
 
 struct sbi_scratch;
 
-u64 sbi_timer_value(struct sbi_scratch *scratch);
+/** Get timer value for current HART */
+u64 sbi_timer_value(void);
 
-u64 sbi_timer_virt_value(struct sbi_scratch *scratch);
+/** Get virtualized timer value for current HART */
+u64 sbi_timer_virt_value(void);
 
-u64 sbi_timer_get_delta(struct sbi_scratch *scratch);
+/** Get timer delta value for current HART */
+u64 sbi_timer_get_delta(void);
 
-void sbi_timer_set_delta(struct sbi_scratch *scratch, ulong delta);
+/** Set timer delta value for current HART */
+void sbi_timer_set_delta(ulong delta);
 
-void sbi_timer_set_delta_upper(struct sbi_scratch *scratch, ulong delta_upper);
+/** Set upper 32-bits of timer delta value for current HART */
+void sbi_timer_set_delta_upper(ulong delta_upper);
 
-void sbi_timer_event_start(struct sbi_scratch *scratch, u64 next_event);
+/** Start timer event for current HART */
+void sbi_timer_event_start(u64 next_event);
 
-void sbi_timer_process(struct sbi_scratch *scratch);
+/** Process timer event for current HART */
+void sbi_timer_process(void);
 
+/* Initialize timer */
 int sbi_timer_init(struct sbi_scratch *scratch, bool cold_boot);
 
+/* Exit timer */
 void sbi_timer_exit(struct sbi_scratch *scratch);
 
 #endif

include/sbi/sbi_tlb.h

@@ -12,6 +12,7 @@
 #define __SBI_TLB_H__
 
 #include <sbi/sbi_types.h>
+#include <sbi/sbi_hartmask.h>
 
 /* clang-format off */
 
@@ -37,14 +38,24 @@ struct sbi_tlb_info {
 	unsigned long start;
 	unsigned long size;
 	unsigned long asid;
+	unsigned long vmid;
 	unsigned long type;
-	unsigned long shart_mask;
+	struct sbi_hartmask smask;
 };
 
-#define SBI_TLB_INFO_SIZE			sizeof(struct sbi_tlb_info)
+#define SBI_TLB_INFO_INIT(__p, __start, __size, __asid, __vmid, __type, __src) \
+do { \
+	(__p)->start = (__start); \
+	(__p)->size = (__size); \
+	(__p)->asid = (__asid); \
+	(__p)->vmid = (__vmid); \
+	(__p)->type = (__type); \
+	SBI_HARTMASK_INIT_EXCEPT(&(__p)->smask, (__src)); \
+} while (0)
 
-int sbi_tlb_request(struct sbi_scratch *scratch, ulong hmask,
-		    ulong hbase, struct sbi_tlb_info *tinfo);
+#define SBI_TLB_INFO_SIZE		sizeof(struct sbi_tlb_info)
+
+int sbi_tlb_request(ulong hmask, ulong hbase, struct sbi_tlb_info *tinfo);
 
 int sbi_tlb_init(struct sbi_scratch *scratch, bool cold_boot);
 

include/sbi/sbi_trap.h

@@ -85,6 +85,19 @@
 /** Last member index in sbi_trap_regs */
 #define SBI_TRAP_REGS_last			35
 
+/** Index of epc member in sbi_trap_info */
+#define SBI_TRAP_INFO_epc			0
+/** Index of cause member in sbi_trap_info */
+#define SBI_TRAP_INFO_cause			1
+/** Index of tval member in sbi_trap_info */
+#define SBI_TRAP_INFO_tval			2
+/** Index of tval2 member in sbi_trap_info */
+#define SBI_TRAP_INFO_tval2			3
+/** Index of tinst member in sbi_trap_info */
+#define SBI_TRAP_INFO_tinst			4
+/** Last member index in sbi_trap_info */
+#define SBI_TRAP_INFO_last			5
+
 /* clang-format on */
 
 /** Get offset of member with name 'x' in sbi_trap_regs */
@@ -92,6 +105,11 @@
 /** Size (in bytes) of sbi_trap_regs */
 #define SBI_TRAP_REGS_SIZE SBI_TRAP_REGS_OFFSET(last)
 
+/** Get offset of member with name 'x' in sbi_trap_info */
+#define SBI_TRAP_INFO_OFFSET(x) ((SBI_TRAP_INFO_##x) * __SIZEOF_POINTER__)
+/** Size (in bytes) of sbi_trap_info */
+#define SBI_TRAP_INFO_SIZE SBI_TRAP_INFO_OFFSET(last)
+
 #ifndef __ASSEMBLY__
 
 #include <sbi/sbi_types.h>
@@ -184,14 +202,10 @@ struct sbi_trap_info {
 	unsigned long tinst;
 };
 
-struct sbi_scratch;
-
 int sbi_trap_redirect(struct sbi_trap_regs *regs,
-		      struct sbi_trap_info *trap,
-		      struct sbi_scratch *scratch);
+		      struct sbi_trap_info *trap);
 
-void sbi_trap_handler(struct sbi_trap_regs *regs,
-		      struct sbi_scratch *scratch);
+void sbi_trap_handler(struct sbi_trap_regs *regs);
 
 #endif
 

include/sbi/sbi_types.h

@@ -56,6 +56,8 @@ typedef unsigned long		physical_size_t;
 
 #define TRUE			1
 #define FALSE			0
+#define true			TRUE
+#define false			FALSE
 
 #define NULL			((void *)0)
 
@@ -76,6 +78,8 @@ typedef unsigned long		physical_size_t;
 	const typeof(((type *)0)->member) * __mptr = (ptr);	\
 	(type *)((char *)__mptr - offsetof(type, member)); })
 
+#define array_size(x) 	(sizeof(x) / sizeof((x)[0]))
+
 #define MAX(a, b) ((a) > (b) ? (a) : (b))
 #define MIN(a, b) ((a) < (b) ? (a) : (b))
 #define CLAMP(a, lo, hi) MIN(MAX(a, lo), hi)
@@ -89,7 +93,8 @@ typedef unsigned long		physical_size_t;
 /* clang-format on */
 
 #else
-/* OPENSBI_EXTERNAL_SBI_TYPES could be defined in CFLAGS for using the
+/*
+ * OPENSBI_EXTERNAL_SBI_TYPES could be defined in CFLAGS for using the
  * external definitions of data types and common macros.
  * OPENSBI_EXTERNAL_SBI_TYPES is the file name to external header file,
  * the external build system should address the additional include

include/sbi/sbi_unpriv.h

@@ -17,12 +17,10 @@ struct sbi_trap_info;
 
 #define DECLARE_UNPRIVILEGED_LOAD_FUNCTION(type)           \
 	type sbi_load_##type(const type *addr,             \
-			     struct sbi_scratch *scratch,  \
 			     struct sbi_trap_info *trap);
 
 #define DECLARE_UNPRIVILEGED_STORE_FUNCTION(type)          \
 	void sbi_store_##type(type *addr, type val,        \
-			      struct sbi_scratch *scratch, \
 			      struct sbi_trap_info *trap);
 
 DECLARE_UNPRIVILEGED_LOAD_FUNCTION(u8)
@@ -38,7 +36,6 @@ DECLARE_UNPRIVILEGED_LOAD_FUNCTION(u64)
 DECLARE_UNPRIVILEGED_STORE_FUNCTION(u64)
 DECLARE_UNPRIVILEGED_LOAD_FUNCTION(ulong)
 
-ulong sbi_get_insn(ulong mepc, struct sbi_scratch *scratch,
-		   struct sbi_trap_info *trap);
+ulong sbi_get_insn(ulong mepc, struct sbi_trap_info *trap);
 
 #endif

include/sbi/sbi_version.h

@@ -11,12 +11,12 @@
 #define __SBI_VERSION_H__
 
 #define OPENSBI_VERSION_MAJOR 0
-#define OPENSBI_VERSION_MINOR 6
+#define OPENSBI_VERSION_MINOR 8
 
 /**
- *  OpenSBI 32-bit version with:
- *  1. upper 16-bits as major number
- *  2. lower 16-bits as minor number
+ * OpenSBI 32-bit version with:
+ * 1. upper 16-bits as major number
+ * 2. lower 16-bits as minor number
  */
 #define OPENSBI_VERSION ((OPENSBI_VERSION_MAJOR << 16) | \
 			 (OPENSBI_VERSION_MINOR))

include/sbi_utils/fdt/fdt_fixup.h

@@ -0,0 +1,78 @@
+// SPDX-License-Identifier: BSD-2-Clause
+/*
+ * fdt_fixup.h - Flat Device Tree manipulation helper routines
+ * Implement platform specific DT fixups on top of libfdt. 
+ *
+ * Copyright (C) 2020 Bin Meng <bmeng.cn@gmail.com>
+ */
+
+#ifndef __FDT_FIXUP_H__
+#define __FDT_FIXUP_H__
+
+/**
+ * Fix up the CPU node in the device tree
+ *
+ * This routine updates the "status" property of a CPU node in the device tree
+ * to "disabled" if that hart is in disabled state in OpenSBI.
+ *
+ * It is recommended that platform codes call this helper in their final_init()
+ *
+ * @param fdt: device tree blob
+ */
+void fdt_cpu_fixup(void *fdt);
+
+/**
+ * Fix up the PLIC node in the device tree
+ *
+ * This routine updates the "interrupt-extended" property of the PLIC node in
+ * the device tree to hide the M-mode external interrupt from CPUs.
+ *
+ * It is recommended that platform codes call this helper in their final_init()
+ *
+ * @param fdt: device tree blob
+ * @param compat: PLIC node compatible string
+ */
+void fdt_plic_fixup(void *fdt, const char *compat);
+
+/**
+ * Fix up the reserved memory node in the device tree
+ *
+ * This routine inserts a child node of the reserved memory node in the device
+ * tree that describes the protected memory region done by OpenSBI via PMP.
+ *
+ * It is recommended that platform codes call this helper in their final_init()
+ *
+ * @param fdt: device tree blob
+ * @return zero on success and -ve on failure
+ */
+int fdt_reserved_memory_fixup(void *fdt);
+
+/**
+ * Fix up the reserved memory subnodes in the device tree
+ *
+ * This routine adds the no-map property to the reserved memory subnodes so
+ * that the OS does not map those PMP protected memory regions.
+ *
+ * Platform codes must call this helper in their final_init() after fdt_fixups()
+ * if the OS should not map the PMP protected reserved regions.
+ *
+ * @param fdt: device tree blob
+ * @return zero on success and -ve on failure
+ */
+int fdt_reserved_memory_nomap_fixup(void *fdt);
+
+/**
+ * General device tree fix-up
+ *
+ * This routine do all required device tree fix-ups for a typical platform.
+ * It fixes up the PLIC node and the reserved memory node in the device tree
+ * by calling the corresponding helper routines to accomplish the task.
+ *
+ * It is recommended that platform codes call this helper in their final_init()
+ *
+ * @param fdt: device tree blob
+ */
+void fdt_fixups(void *fdt);
+
+#endif /* __FDT_FIXUP_H__ */
+

include/sbi_utils/fdt/fdt_helper.h

@@ -0,0 +1,68 @@
+// SPDX-License-Identifier: BSD-2-Clause
+/*
+ * fdt_helper.h - Flat Device Tree parsing helper routines
+ * Implement helper routines to parse FDT nodes on top of
+ * libfdt for OpenSBI usage
+ *
+ * Copyright (C) 2020 Bin Meng <bmeng.cn@gmail.com>
+ */
+
+#ifndef __FDT_HELPER_H__
+#define __FDT_HELPER_H__
+
+#include <sbi/sbi_types.h>
+
+struct fdt_match {
+	const char *compatible;
+	void *data;
+};
+
+struct platform_uart_data {
+	unsigned long addr;
+	unsigned long freq;
+	unsigned long baud;
+	unsigned long reg_shift;
+	unsigned long reg_io_width;
+};
+
+const struct fdt_match *fdt_match_node(void *fdt, int nodeoff,
+				       const struct fdt_match *match_table);
+
+int fdt_find_match(void *fdt, int startoff,
+		   const struct fdt_match *match_table,
+		   const struct fdt_match **out_match);
+
+int fdt_get_node_addr_size(void *fdt, int node, unsigned long *addr,
+			   unsigned long *size);
+
+int fdt_parse_hart_id(void *fdt, int cpu_offset, u32 *hartid);
+
+int fdt_parse_max_hart_id(void *fdt, u32 *max_hartid);
+
+int fdt_parse_shakti_uart_node(void *fdt, int nodeoffset,
+			       struct platform_uart_data *uart);
+
+int fdt_parse_sifive_uart_node(void *fdt, int nodeoffset,
+			       struct platform_uart_data *uart);
+
+int fdt_parse_uart8250_node(void *fdt, int nodeoffset,
+			    struct platform_uart_data *uart);
+
+int fdt_parse_uart8250(void *fdt, struct platform_uart_data *uart,
+		       const char *compatible);
+
+struct plic_data;
+
+int fdt_parse_plic_node(void *fdt, int nodeoffset, struct plic_data *plic);
+
+int fdt_parse_plic(void *fdt, struct plic_data *plic, const char *compat);
+
+struct clint_data;
+
+int fdt_parse_clint_node(void *fdt, int nodeoffset, bool for_timer,
+			 struct clint_data *clint);
+
+int fdt_parse_compat_addr(void *fdt, unsigned long *addr,
+			  const char *compatible);
+
+#endif /* __FDT_HELPER_H__ */

include/sbi_utils/ipi/fdt_ipi.h

@@ -0,0 +1,32 @@
+/*
+ * SPDX-License-Identifier: BSD-2-Clause
+ *
+ * Copyright (c) 2020 Western Digital Corporation or its affiliates.
+ *
+ * Authors:
+ *   Anup Patel <anup.patel@wdc.com>
+ */
+
+#ifndef __FDT_IPI_H__
+#define __FDT_IPI_H__
+
+#include <sbi/sbi_types.h>
+
+struct fdt_ipi {
+	const struct fdt_match *match_table;
+	int (*cold_init)(void *fdt, int nodeoff, const struct fdt_match *match);
+	int (*warm_init)(void);
+	void (*exit)(void);
+	void (*send)(u32 target_hart);
+	void (*clear)(u32 target_hart);
+};
+
+void fdt_ipi_send(u32 target_hart);
+
+void fdt_ipi_clear(u32 target_hart);
+
+void fdt_ipi_exit(void);
+
+int fdt_ipi_init(bool cold_boot);
+
+#endif

include/sbi_utils/irqchip/fdt_irqchip.h

@@ -0,0 +1,26 @@
+/*
+ * SPDX-License-Identifier: BSD-2-Clause
+ *
+ * Copyright (c) 2020 Western Digital Corporation or its affiliates.
+ *
+ * Authors:
+ *   Anup Patel <anup.patel@wdc.com>
+ */
+
+#ifndef __FDT_IRQCHIP_H__
+#define __FDT_IRQCHIP_H__
+
+#include <sbi/sbi_types.h>
+
+struct fdt_irqchip {
+	const struct fdt_match *match_table;
+	int (*cold_init)(void *fdt, int nodeoff, const struct fdt_match *match);
+	int (*warm_init)(void);
+	void (*exit)(void);
+};
+
+void fdt_irqchip_exit(void);
+
+int fdt_irqchip_init(bool cold_boot);
+
+#endif

include/sbi_utils/irqchip/plic.h

@@ -12,14 +12,18 @@
 
 #include <sbi/sbi_types.h>
 
-void plic_fdt_fixup(void *fdt, const char *compat);
+struct plic_data {
+	unsigned long addr;
+	unsigned long num_src;
+};
 
-int plic_warm_irqchip_init(u32 target_hart, int m_cntx_id, int s_cntx_id);
+int plic_warm_irqchip_init(struct plic_data *plic,
+			   int m_cntx_id, int s_cntx_id);
 
-int plic_cold_irqchip_init(unsigned long base, u32 num_sources, u32 hart_count);
+int plic_cold_irqchip_init(struct plic_data *plic);
 
-void plic_set_thresh(u32 cntxid, u32 val);
+void plic_set_thresh(struct plic_data *plic, u32 cntxid, u32 val);
 
-void plic_set_ie(u32 cntxid, u32 word_index, u32 val);
+void plic_set_ie(struct plic_data *plic, u32 cntxid, u32 word_index, u32 val);
 
 #endif

include/sbi_utils/reset/fdt_reset.h

@@ -0,0 +1,25 @@
+/*
+ * SPDX-License-Identifier: BSD-2-Clause
+ *
+ * Copyright (c) 2020 Western Digital Corporation or its affiliates.
+ *
+ * Authors:
+ *   Anup Patel <anup.patel@wdc.com>
+ */
+
+#ifndef __FDT_RESET_H__
+#define __FDT_RESET_H__
+
+#include <sbi/sbi_types.h>
+
+struct fdt_reset {
+	const struct fdt_match *match_table;
+	int (*init)(void *fdt, int nodeoff, const struct fdt_match *match);
+	int (*system_reset)(u32 reset_type);
+};
+
+int fdt_system_reset(u32 reset_type);
+
+int fdt_reset_init(void);
+
+#endif

include/sbi_utils/serial/fdt_serial.h

@@ -0,0 +1,28 @@
+/*
+ * SPDX-License-Identifier: BSD-2-Clause
+ *
+ * Copyright (c) 2020 Western Digital Corporation or its affiliates.
+ *
+ * Authors:
+ *   Anup Patel <anup.patel@wdc.com>
+ */
+
+#ifndef __FDT_SERIAL_H__
+#define __FDT_SERIAL_H__
+
+#include <sbi/sbi_types.h>
+
+struct fdt_serial {
+	const struct fdt_match *match_table;
+	int (*init)(void *fdt, int nodeoff, const struct fdt_match *match);
+	void (*putc)(char ch);
+	int (*getc)(void);
+};
+
+void fdt_serial_putc(char ch);
+
+int fdt_serial_getc(void);
+
+int fdt_serial_init(void);
+
+#endif

include/sbi_utils/serial/shakti-uart.h

@@ -0,0 +1,18 @@
+/*
+ * SPDX-License-Identifier: BSD-2-Clause
+ *
+ * Copyright (c) 2020 Vijai Kumar K <vijai@behindbytes.com>
+ */
+
+#ifndef __SERIAL_SHAKTI_UART_H__
+#define __SERIAL_SHAKTI_UART_H__
+
+#include <sbi/sbi_types.h>
+
+void shakti_uart_putc(char ch);
+
+int shakti_uart_getc(void);
+
+int shakti_uart_init(unsigned long base, u32 in_freq, u32 baudrate);
+
+#endif

include/sbi_utils/sys/clint.h

@@ -12,15 +12,30 @@
 
 #include <sbi/sbi_types.h>
 
-void clint_ipi_send(u32 target_hart);
+struct clint_data {
+	/* Public details */
+	unsigned long addr;
+	u32 first_hartid;
+	u32 hart_count;
+	bool has_64bit_mmio;
+	/* Private details (initialized and used by CLINT library)*/
+	u32 *ipi;
+	struct clint_data *time_delta_reference;
+	unsigned long time_delta_computed;
+	u64 time_delta;
+	u64 *time_val;
+	u64 *time_cmp;
+	u64 (*time_rd)(volatile u64 *addr);
+	void (*time_wr)(u64 value, volatile u64 *addr);
+};
 
-void clint_ipi_sync(u32 target_hart);
+void clint_ipi_send(u32 target_hart);
 
 void clint_ipi_clear(u32 target_hart);
 
 int clint_warm_ipi_init(void);
 
-int clint_cold_ipi_init(unsigned long base, u32 hart_count);
+int clint_cold_ipi_init(struct clint_data *clint);
 
 u64 clint_timer_value(void);
 
@@ -30,7 +45,7 @@ void clint_timer_event_start(u64 next_event);
 
 int clint_warm_timer_init(void);
 
-int clint_cold_timer_init(unsigned long base, u32 hart_count,
-			  bool has_64bit_mmio);
+int clint_cold_timer_init(struct clint_data *clint,
+			  struct clint_data *reference);
 
 #endif

include/sbi_utils/sys/htif.h

@@ -14,6 +14,6 @@ void htif_putc(char ch);
 
 int htif_getc(void);
 
-int htif_system_down(u32 type);
+int htif_system_reset(u32 type);
 
 #endif

include/sbi_utils/sys/sifive_test.h

@@ -0,0 +1,19 @@
+/*
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ * Copyright (c) 2020 Western Digital Corporation or its affiliates.
+ *
+ * Authors:
+ *   Anup Patel <anup.patel@wdc.com>
+ */
+
+#ifndef __SYS_SIFIVE_TEST_H__
+#define __SYS_SIFIVE_TEST_H__
+
+#include <sbi/sbi_types.h>
+
+int sifive_test_system_reset(u32 type);
+
+int sifive_test_init(unsigned long base);
+
+#endif

include/sbi_utils/timer/fdt_timer.h

@@ -0,0 +1,35 @@
+/*
+ * SPDX-License-Identifier: BSD-2-Clause
+ *
+ * Copyright (c) 2020 Western Digital Corporation or its affiliates.
+ *
+ * Authors:
+ *   Anup Patel <anup.patel@wdc.com>
+ */
+
+#ifndef __FDT_TIMER_H__
+#define __FDT_TIMER_H__
+
+#include <sbi/sbi_types.h>
+
+struct fdt_timer {
+	const struct fdt_match *match_table;
+	int (*cold_init)(void *fdt, int nodeoff, const struct fdt_match *match);
+	int (*warm_init)(void);
+	void (*exit)(void);
+	u64 (*value)(void);
+	void (*event_stop)(void);
+	void (*event_start)(u64 next_event);
+};
+
+u64 fdt_timer_value(void);
+
+void fdt_timer_event_stop(void);
+
+void fdt_timer_event_start(u64 next_event);
+
+void fdt_timer_exit(void);
+
+int fdt_timer_init(bool cold_boot);
+
+#endif

lib/sbi/objects.mk

@@ -12,24 +12,31 @@ libsbi-objs-y += riscv_atomic.o
 libsbi-objs-y += riscv_hardfp.o
 libsbi-objs-y += riscv_locks.o
 
+libsbi-objs-y += sbi_bitmap.o
+libsbi-objs-y += sbi_bitops.o
 libsbi-objs-y += sbi_console.o
 libsbi-objs-y += sbi_ecall.o
 libsbi-objs-y += sbi_ecall_base.o
+libsbi-objs-y += sbi_ecall_hsm.o
 libsbi-objs-y += sbi_ecall_legacy.o
 libsbi-objs-y += sbi_ecall_replace.o
 libsbi-objs-y += sbi_ecall_vendor.o
 libsbi-objs-y += sbi_emulate_csr.o
 libsbi-objs-y += sbi_fifo.o
-libsbi-objs-y += sbi_hfence.o
 libsbi-objs-y += sbi_hart.o
+libsbi-objs-y += sbi_math.o
+libsbi-objs-y += sbi_hfence.o
+libsbi-objs-y += sbi_hsm.o
 libsbi-objs-y += sbi_illegal_insn.o
 libsbi-objs-y += sbi_init.o
 libsbi-objs-y += sbi_ipi.o
 libsbi-objs-y += sbi_misaligned_ldst.o
+libsbi-objs-y += sbi_platform.o
 libsbi-objs-y += sbi_scratch.o
+libsbi-objs-y += sbi_string.o
 libsbi-objs-y += sbi_system.o
 libsbi-objs-y += sbi_timer.o
 libsbi-objs-y += sbi_tlb.o
 libsbi-objs-y += sbi_trap.o
-libsbi-objs-y += sbi_string.o
 libsbi-objs-y += sbi_unpriv.o
+libsbi-objs-y += sbi_expected_trap.o

lib/sbi/riscv_asm.c

@@ -17,8 +17,13 @@ int misa_extension_imp(char ext)
 {
 	unsigned long misa = csr_read(CSR_MISA);
 
-	if (misa)
-		return misa & (1 << (ext - 'A'));
+	if (misa) {
+		if ('A' <= ext && ext <= 'Z')
+			return misa & (1 << (ext - 'A'));
+		if ('a' <= ext && ext <= 'z')
+			return misa & (1 << (ext - 'a'));
+		return 0;
+	}
 
 	return sbi_platform_misa_extension(sbi_platform_thishart_ptr(), ext);
 }
@@ -44,6 +49,45 @@ int misa_xlen(void)
 	return r ? r : -1;
 }
 
+void misa_string(int xlen, char *out, unsigned int out_sz)
+{
+	unsigned int i, pos = 0;
+	const char valid_isa_order[] = "iemafdqclbjtpvnsuhkorwxyzg";
+
+	if (!out)
+		return;
+
+	if (5 <= (out_sz - pos)) {
+		out[pos++] = 'r';
+		out[pos++] = 'v';
+		switch (xlen) {
+		case 1:
+			out[pos++] = '3';
+			out[pos++] = '2';
+			break;
+		case 2:
+			out[pos++] = '6';
+			out[pos++] = '4';
+			break;
+		case 3:
+			out[pos++] = '1';
+			out[pos++] = '2';
+			out[pos++] = '8';
+			break;
+		default:
+			return;
+		}
+	}
+
+	for (i = 0; i < array_size(valid_isa_order) && (pos < out_sz); i++) {
+		if (misa_extension_imp(valid_isa_order[i]))
+			out[pos++] = valid_isa_order[i];
+	}
+
+	if (pos < out_sz)
+		out[pos++] = '\0';
+}
+
 unsigned long csr_read_num(int csr_num)
 {
 	unsigned long ret = 0;
@@ -207,7 +251,7 @@ int pmp_set(unsigned int n, unsigned long prot, unsigned long addr,
 	if (n >= PMP_COUNT || log2len > __riscv_xlen || log2len < PMP_SHIFT)
 		return SBI_EINVAL;
 
-		/* calculate PMP register and offset */
+	/* calculate PMP register and offset */
 #if __riscv_xlen == 32
 	pmpcfg_csr   = CSR_PMPCFG0 + (n >> 2);
 	pmpcfg_shift = (n & 3) << 3;
@@ -224,7 +268,7 @@ int pmp_set(unsigned int n, unsigned long prot, unsigned long addr,
 
 	/* encode PMP config */
 	prot |= (log2len == PMP_SHIFT) ? PMP_A_NA4 : PMP_A_NAPOT;
-	cfgmask = ~(0xff << pmpcfg_shift);
+	cfgmask = ~(0xffUL << pmpcfg_shift);
 	pmpcfg	= (csr_read_num(pmpcfg_csr) & cfgmask);
 	pmpcfg |= ((prot << pmpcfg_shift) & ~cfgmask);
 
@@ -249,16 +293,16 @@ int pmp_set(unsigned int n, unsigned long prot, unsigned long addr,
 }
 
 int pmp_get(unsigned int n, unsigned long *prot_out, unsigned long *addr_out,
-	    unsigned long *log2len_out)
+	    unsigned long *size)
 {
 	int pmpcfg_csr, pmpcfg_shift, pmpaddr_csr;
 	unsigned long cfgmask, pmpcfg, prot;
 	unsigned long t1, addr, log2len;
 
 	/* check parameters */
-	if (n >= PMP_COUNT || !prot_out || !addr_out || !log2len_out)
+	if (n >= PMP_COUNT || !prot_out || !addr_out || !size)
 		return SBI_EINVAL;
-	*prot_out = *addr_out = *log2len_out = 0;
+	*prot_out = *addr_out = *size = 0;
 
 	/* calculate PMP register and offset */
 #if __riscv_xlen == 32
@@ -276,7 +320,7 @@ int pmp_get(unsigned int n, unsigned long *prot_out, unsigned long *addr_out,
 		return SBI_ENOTSUPP;
 
 	/* decode PMP config */
-	cfgmask = (0xff << pmpcfg_shift);
+	cfgmask = (0xffUL << pmpcfg_shift);
 	pmpcfg	= csr_read_num(pmpcfg_csr) & cfgmask;
 	prot	= pmpcfg >> pmpcfg_shift;
 
@@ -299,7 +343,9 @@ int pmp_get(unsigned int n, unsigned long *prot_out, unsigned long *addr_out,
 	/* return details */
 	*prot_out    = prot;
 	*addr_out    = addr;
-	*log2len_out = log2len;
+
+	if (log2len < __riscv_xlen)
+		*size = (1UL << log2len);
 
 	return 0;
 }

lib/sbi/riscv_atomic.c

@@ -7,11 +7,10 @@
  *   Anup Patel <anup.patel@wdc.com>
  */
 
-#include <sbi/sbi_types.h>
+#include <sbi/sbi_bitops.h>
 #include <sbi/riscv_asm.h>
 #include <sbi/riscv_atomic.h>
 #include <sbi/riscv_barrier.h>
-#include <sbi/sbi_bits.h>
 
 long atomic_read(atomic_t *atom)
 {
@@ -50,7 +49,7 @@ long atomic_sub_return(atomic_t *atom, long value)
 	return ret - value;
 }
 
-#define __axchg(ptr, new, size)						\
+#define __axchg(ptr, new, size)							\
 	({									\
 		__typeof__(ptr) __ptr = (ptr);					\
 		__typeof__(new) __new = (new);					\
@@ -71,12 +70,12 @@ long atomic_sub_return(atomic_t *atom, long value)
 				: "memory");					\
 			break;							\
 		default:							\
-			break;						\
+			break;							\
 		}								\
 		__ret;								\
 	})
 
-#define axchg(ptr, x)							\
+#define axchg(ptr, x)								\
 	({									\
 		__typeof__(*(ptr)) _x_ = (x);					\
 		(__typeof__(*(ptr))) __axchg((ptr), _x_, sizeof(*(ptr)));	\
@@ -91,20 +90,20 @@ long atomic_sub_return(atomic_t *atom, long value)
 		register unsigned int __rc;                               \
 		switch (size) {                                           \
 		case 4:                                                   \
-			__asm__ __volatile__("0:	lr.w %0, %2\n"           \
-					     "	sc.w.rl %1, %z3, %2\n"     \
-					     "	bnez %1, 0b\n"             \
-					     "	fence rw, rw\n"            \
+			__asm__ __volatile__("0:	lr.w %0, %2\n"    \
+					     "	sc.w.rl %1, %z3, %2\n"    \
+					     "	bnez %1, 0b\n"            \
+					     "	fence rw, rw\n"           \
 					     : "=&r"(__ret), "=&r"(__rc), \
 					       "+A"(*__ptr)               \
 					     : "rJ"(__new)                \
 					     : "memory");                 \
 			break;                                            \
 		case 8:                                                   \
-			__asm__ __volatile__("0:	lr.d %0, %2\n"           \
-					     "	sc.d.rl %1, %z3, %2\n"     \
-					     "	bnez %1, 0b\n"             \
-					     "	fence rw, rw\n"            \
+			__asm__ __volatile__("0:	lr.d %0, %2\n"    \
+					     "	sc.d.rl %1, %z3, %2\n"    \
+					     "	bnez %1, 0b\n"            \
+					     "	fence rw, rw\n"           \
 					     : "=&r"(__ret), "=&r"(__rc), \
 					       "+A"(*__ptr)               \
 					     : "rJ"(__new)                \
@@ -131,11 +130,11 @@ long atomic_sub_return(atomic_t *atom, long value)
 		register unsigned int __rc;                               \
 		switch (size) {                                           \
 		case 4:                                                   \
-			__asm__ __volatile__("0:	lr.w %0, %2\n"           \
-					     "	bne  %0, %z3, 1f\n"        \
-					     "	sc.w.rl %1, %z4, %2\n"     \
-					     "	bnez %1, 0b\n"             \
-					     "	fence rw, rw\n"            \
+			__asm__ __volatile__("0:	lr.w %0, %2\n"    \
+					     "	bne  %0, %z3, 1f\n"       \
+					     "	sc.w.rl %1, %z4, %2\n"    \
+					     "	bnez %1, 0b\n"            \
+					     "	fence rw, rw\n"           \
 					     "1:\n"                       \
 					     : "=&r"(__ret), "=&r"(__rc), \
 					       "+A"(*__ptr)               \
@@ -143,11 +142,11 @@ long atomic_sub_return(atomic_t *atom, long value)
 					     : "memory");                 \
 			break;                                            \
 		case 8:                                                   \
-			__asm__ __volatile__("0:	lr.d %0, %2\n"           \
-					     "	bne %0, %z3, 1f\n"         \
-					     "	sc.d.rl %1, %z4, %2\n"     \
-					     "	bnez %1, 0b\n"             \
-					     "	fence rw, rw\n"            \
+			__asm__ __volatile__("0:	lr.d %0, %2\n"    \
+					     "	bne %0, %z3, 1f\n"        \
+					     "	sc.d.rl %1, %z4, %2\n"    \
+					     "	bnez %1, 0b\n"            \
+					     "	fence rw, rw\n"           \
 					     "1:\n"                       \
 					     : "=&r"(__ret), "=&r"(__rc), \
 					       "+A"(*__ptr)               \
@@ -168,7 +167,7 @@ long atomic_sub_return(atomic_t *atom, long value)
 			__cmpxchg((ptr), _o_, _n_, sizeof(*(ptr))); \
 	})
 
-long arch_atomic_cmpxchg(atomic_t *atom, long oldval, long newval)
+long atomic_cmpxchg(atomic_t *atom, long oldval, long newval)
 {
 #ifdef __riscv_atomic
 	return __sync_val_compare_and_swap(&atom->counter, oldval, newval);
@@ -177,7 +176,7 @@ long arch_atomic_cmpxchg(atomic_t *atom, long oldval, long newval)
 #endif
 }
 
-long arch_atomic_xchg(atomic_t *atom, long newval)
+long atomic_xchg(atomic_t *atom, long newval)
 {
 	/* Atomically set new value and return old value. */
 #ifdef __riscv_atomic
@@ -209,12 +208,12 @@ unsigned long atomic_raw_xchg_ulong(volatile unsigned long *ptr,
 #endif
 }
 
-#if (BITS_PER_LONG == 64)
+#if (__SIZEOF_POINTER__ == 8)
 #define __AMO(op) "amo" #op ".d"
-#elif (BITS_PER_LONG == 32)
+#elif (__SIZEOF_POINTER__ == 4)
 #define __AMO(op) "amo" #op ".w"
 #else
-#error "Unexpected BITS_PER_LONG"
+#error "Unexpected __SIZEOF_POINTER__"
 #endif
 
 #define __atomic_op_bit_ord(op, mod, nr, addr, ord)                          \

lib/sbi/sbi_bitmap.c

@@ -0,0 +1,40 @@
+/*
+ * SPDX-License-Identifier: BSD-2-Clause
+ *
+ * Copyright (c) 2020 Western Digital Corporation or its affiliates.
+ *
+ * Authors:
+ *   Anup Patel <anup.patel@wdc.com>
+ */
+
+#include <sbi/sbi_bitmap.h>
+
+void __bitmap_and(unsigned long *dst, const unsigned long *bitmap1,
+		  const unsigned long *bitmap2, int bits)
+{
+	int k;
+	int nr = BITS_TO_LONGS(bits);
+
+	for (k = 0; k < nr; k++)
+		dst[k] = bitmap1[k] & bitmap2[k];
+}
+
+void __bitmap_or(unsigned long *dst, const unsigned long *bitmap1,
+		 const unsigned long *bitmap2, int bits)
+{
+	int k;
+	int nr = BITS_TO_LONGS(bits);
+
+	for (k = 0; k < nr; k++)
+		dst[k] = bitmap1[k] | bitmap2[k];
+}
+
+void __bitmap_xor(unsigned long *dst, const unsigned long *bitmap1,
+		  const unsigned long *bitmap2, int bits)
+{
+	int k;
+	int nr = BITS_TO_LONGS(bits);
+
+	for (k = 0; k < nr; k++)
+		dst[k] = bitmap1[k] ^ bitmap2[k];
+}

lib/sbi/sbi_bitops.c

@@ -0,0 +1,200 @@
+/*
+ * SPDX-License-Identifier: BSD-2-Clause
+ *
+ * Copyright (c) 2020 Western Digital Corporation or its affiliates.
+ *
+ * Authors:
+ *   Atish Patra <atish.patra@wdc.com>
+ *   Anup Patel <anup.patel@wdc.com>
+ */
+
+#include <sbi/sbi_bitops.h>
+
+#define BITOP_WORD(nr)		((nr) / BITS_PER_LONG)
+
+/**
+ * find_first_bit - find the first set bit in a memory region
+ * @addr: The address to start the search at
+ * @size: The maximum size to search
+ *
+ * Returns the bit number of the first set bit.
+ */
+unsigned long find_first_bit(const unsigned long *addr,
+			     unsigned long size)
+{
+	const unsigned long *p = addr;
+	unsigned long result = 0;
+	unsigned long tmp;
+
+	while (size & ~(BITS_PER_LONG-1)) {
+		if ((tmp = *(p++)))
+			goto found;
+		result += BITS_PER_LONG;
+		size -= BITS_PER_LONG;
+	}
+	if (!size)
+		return result;
+
+	tmp = (*p) & (~0UL >> (BITS_PER_LONG - size));
+	if (tmp == 0UL)		/* Are any bits set? */
+		return result + size;	/* Nope. */
+found:
+	return result + __ffs(tmp);
+}
+
+/**
+ * find_first_zero_bit - find the first cleared bit in a memory region
+ * @addr: The address to start the search at
+ * @size: The maximum size to search
+ *
+ * Returns the bit number of the first cleared bit.
+ */
+unsigned long find_first_zero_bit(const unsigned long *addr,
+				  unsigned long size)
+{
+	const unsigned long *p = addr;
+	unsigned long result = 0;
+	unsigned long tmp;
+
+	while (size & ~(BITS_PER_LONG-1)) {
+		if (~(tmp = *(p++)))
+			goto found;
+		result += BITS_PER_LONG;
+		size -= BITS_PER_LONG;
+	}
+	if (!size)
+		return result;
+
+	tmp = (*p) | (~0UL << size);
+	if (tmp == ~0UL)	/* Are any bits zero? */
+		return result + size;	/* Nope. */
+found:
+	return result + ffz(tmp);
+}
+
+/**
+ * find_last_bit - find the last set bit in a memory region
+ * @addr: The address to start the search at
+ * @size: The maximum size to search
+ *
+ * Returns the bit number of the first set bit, or size.
+ */
+unsigned long find_last_bit(const unsigned long *addr,
+			    unsigned long size)
+{
+	unsigned long words;
+	unsigned long tmp;
+
+	/* Start at final word. */
+	words = size / BITS_PER_LONG;
+
+	/* Partial final word? */
+	if (size & (BITS_PER_LONG-1)) {
+		tmp = (addr[words] & (~0UL >> (BITS_PER_LONG
+					 - (size & (BITS_PER_LONG-1)))));
+		if (tmp)
+			goto found;
+	}
+
+	while (words) {
+		tmp = addr[--words];
+		if (tmp) {
+found:
+			return words * BITS_PER_LONG + __fls(tmp);
+		}
+	}
+
+	/* Not found */
+	return size;
+}
+
+/**
+ * find_next_bit - find the next set bit in a memory region
+ * @addr: The address to base the search on
+ * @offset: The bitnumber to start searching at
+ * @size: The bitmap size in bits
+ */
+unsigned long find_next_bit(const unsigned long *addr,
+			    unsigned long size, unsigned long offset)
+{
+	const unsigned long *p = addr + BITOP_WORD(offset);
+	unsigned long result = offset & ~(BITS_PER_LONG-1);
+	unsigned long tmp;
+
+	if (offset >= size)
+		return size;
+	size -= result;
+	offset %= BITS_PER_LONG;
+	if (offset) {
+		tmp = *(p++);
+		tmp &= (~0UL << offset);
+		if (size < BITS_PER_LONG)
+			goto found_first;
+		if (tmp)
+			goto found_middle;
+		size -= BITS_PER_LONG;
+		result += BITS_PER_LONG;
+	}
+	while (size & ~(BITS_PER_LONG-1)) {
+		if ((tmp = *(p++)))
+			goto found_middle;
+		result += BITS_PER_LONG;
+		size -= BITS_PER_LONG;
+	}
+	if (!size)
+		return result;
+	tmp = *p;
+
+found_first:
+	tmp &= (~0UL >> (BITS_PER_LONG - size));
+	if (tmp == 0UL)		/* Are any bits set? */
+		return result + size;	/* Nope. */
+found_middle:
+	return result + __ffs(tmp);
+}
+
+/**
+ * find_next_zero_bit - find the next cleared bit in a memory region
+ * @addr: The address to base the search on
+ * @offset: The bitnumber to start searching at
+ * @size: The bitmap size in bits
+ */
+unsigned long find_next_zero_bit(const unsigned long *addr,
+				 unsigned long size,
+				 unsigned long offset)
+{
+	const unsigned long *p = addr + BITOP_WORD(offset);
+	unsigned long result = offset & ~(BITS_PER_LONG-1);
+	unsigned long tmp;
+
+	if (offset >= size)
+		return size;
+	size -= result;
+	offset %= BITS_PER_LONG;
+	if (offset) {
+		tmp = *(p++);
+		tmp |= ~0UL >> (BITS_PER_LONG - offset);
+		if (size < BITS_PER_LONG)
+			goto found_first;
+		if (~tmp)
+			goto found_middle;
+		size -= BITS_PER_LONG;
+		result += BITS_PER_LONG;
+	}
+	while (size & ~(BITS_PER_LONG-1)) {
+		if (~(tmp = *(p++)))
+			goto found_middle;
+		result += BITS_PER_LONG;
+		size -= BITS_PER_LONG;
+	}
+	if (!size)
+		return result;
+	tmp = *p;
+
+found_first:
+	tmp |= ~0UL << size;
+	if (tmp == ~0UL)	/* Are any bits zero? */
+		return result + size;	/* Nope. */
+found_middle:
+	return result + ffz(tmp);
+}

lib/sbi/sbi_console.c

@@ -7,9 +7,10 @@
  *   Anup Patel <anup.patel@wdc.com>
  */
 
-#include <sbi/sbi_platform.h>
-#include <sbi/sbi_console.h>
 #include <sbi/riscv_locks.h>
+#include <sbi/sbi_console.h>
+#include <sbi/sbi_platform.h>
+#include <sbi/sbi_scratch.h>
 
 static const struct sbi_platform *console_plat = NULL;
 static spinlock_t console_out_lock	       = SPIN_LOCK_INITIALIZER;
@@ -375,10 +376,11 @@ int sbi_printf(const char *format, ...)
 	return retval;
 }
 
-int sbi_dprintf(struct sbi_scratch *scratch, const char *format, ...)
+int sbi_dprintf(const char *format, ...)
 {
 	va_list args;
 	int retval = 0;
+	struct sbi_scratch *scratch = sbi_scratch_thishart_ptr();
 
 	va_start(args, format);
 	if (scratch->options & SBI_SCRATCH_DEBUG_PRINTS)

lib/sbi/sbi_ecall.c

@@ -7,6 +7,7 @@
  *   Anup Patel <anup.patel@wdc.com>
  */
 
+#include <sbi/sbi_console.h>
 #include <sbi/sbi_ecall.h>
 #include <sbi/sbi_ecall_interface.h>
 #include <sbi/sbi_error.h>
@@ -22,6 +23,18 @@ u16 sbi_ecall_version_minor(void)
 	return SBI_ECALL_VERSION_MINOR;
 }
 
+static unsigned long ecall_impid = SBI_OPENSBI_IMPID;
+
+unsigned long sbi_ecall_get_impid(void)
+{
+	return ecall_impid;
+}
+
+void sbi_ecall_set_impid(unsigned long impid)
+{
+	ecall_impid = impid;
+}
+
 static SBI_LIST_HEAD(ecall_exts_list);
 
 struct sbi_ecall_extension *sbi_ecall_find_extension(unsigned long extid)
@@ -40,11 +53,19 @@ struct sbi_ecall_extension *sbi_ecall_find_extension(unsigned long extid)
 
 int sbi_ecall_register_extension(struct sbi_ecall_extension *ext)
 {
+	struct sbi_ecall_extension *t;
+
 	if (!ext || (ext->extid_end < ext->extid_start) || !ext->handle)
 		return SBI_EINVAL;
-	if (sbi_ecall_find_extension(ext->extid_start) ||
-	    sbi_ecall_find_extension(ext->extid_end))
-		return SBI_EINVAL;
+
+	sbi_list_for_each_entry(t, &ecall_exts_list, head) {
+		unsigned long start = t->extid_start;
+		unsigned long end = t->extid_end;
+		if (end < ext->extid_start || ext->extid_end < start)
+			/* no overlap */;
+		else
+			return SBI_EINVAL;
+	}
 
 	SBI_INIT_LIST_HEAD(&ext->head);
 	sbi_list_add_tail(&ext->head, &ecall_exts_list);
@@ -71,8 +92,7 @@ void sbi_ecall_unregister_extension(struct sbi_ecall_extension *ext)
 		sbi_list_del_init(&ext->head);
 }
 
-int sbi_ecall_handler(u32 hartid, ulong mcause, struct sbi_trap_regs *regs,
-		      struct sbi_scratch *scratch)
+int sbi_ecall_handler(struct sbi_trap_regs *regs)
 {
 	int ret = 0;
 	struct sbi_ecall_extension *ext;
@@ -92,7 +112,7 @@ int sbi_ecall_handler(u32 hartid, ulong mcause, struct sbi_trap_regs *regs,
 
 	ext = sbi_ecall_find_extension(extension_id);
 	if (ext && ext->handle) {
-		ret = ext->handle(scratch, extension_id, func_id,
+		ret = ext->handle(extension_id, func_id,
 				  args, &out_val, &trap);
 		if (extension_id >= SBI_EXT_0_1_SET_TIMER &&
 		    extension_id <= SBI_EXT_0_1_SHUTDOWN)
@@ -103,9 +123,17 @@ int sbi_ecall_handler(u32 hartid, ulong mcause, struct sbi_trap_regs *regs,
 
 	if (ret == SBI_ETRAP) {
 		trap.epc = regs->mepc;
-		sbi_trap_redirect(regs, &trap, scratch);
+		sbi_trap_redirect(regs, &trap);
 	} else {
-		/* This function should return non-zero value only in case of
+		if (ret < SBI_LAST_ERR) {
+			sbi_printf("%s: Invalid error %d for ext=0x%lx "
+				   "func=0x%lx\n", __func__, ret,
+				   extension_id, func_id);
+			ret = SBI_ERR_FAILED;
+		}
+
+		/*
+		 * This function should return non-zero value only in case of
 		 * fatal error. However, there is no good way to distinguish
 		 * between a fatal and non-fatal errors yet. That's why we treat
 		 * every return value except ETRAP as non-fatal and just return
@@ -136,6 +164,9 @@ int sbi_ecall_init(void)
 	if (ret)
 		return ret;
 	ret = sbi_ecall_register_extension(&ecall_base);
+	if (ret)
+		return ret;
+	ret = sbi_ecall_register_extension(&ecall_hsm);
 	if (ret)
 		return ret;
 	ret = sbi_ecall_register_extension(&ecall_legacy);

lib/sbi/sbi_ecall_base.c

@@ -14,9 +14,7 @@
 #include <sbi/sbi_version.h>
 #include <sbi/riscv_asm.h>
 
-static int sbi_ecall_base_probe(struct sbi_scratch *scratch,
-				unsigned long extid,
-				unsigned long *out_val)
+static int sbi_ecall_base_probe(unsigned long extid, unsigned long *out_val)
 {
 	struct sbi_ecall_extension *ext;
 
@@ -27,14 +25,13 @@ static int sbi_ecall_base_probe(struct sbi_scratch *scratch,
 	}
 
 	if (ext->probe)
-		return ext->probe(scratch, extid, out_val);
+		return ext->probe(extid, out_val);
 
 	*out_val = 1;
 	return 0;
 }
 
-static int sbi_ecall_base_handler(struct sbi_scratch *scratch,
-				  unsigned long extid, unsigned long funcid,
+static int sbi_ecall_base_handler(unsigned long extid, unsigned long funcid,
 				  unsigned long *args, unsigned long *out_val,
 				  struct sbi_trap_info *out_trap)
 {
@@ -49,7 +46,7 @@ static int sbi_ecall_base_handler(struct sbi_scratch *scratch,
 		*out_val = *out_val | SBI_ECALL_VERSION_MINOR;
 		break;
 	case SBI_EXT_BASE_GET_IMP_ID:
-		*out_val = SBI_OPENSBI_IMPID;
+		*out_val = sbi_ecall_get_impid();
 		break;
 	case SBI_EXT_BASE_GET_IMP_VERSION:
 		*out_val = OPENSBI_VERSION;
@@ -64,7 +61,7 @@ static int sbi_ecall_base_handler(struct sbi_scratch *scratch,
 		*out_val = csr_read(CSR_MIMPID);
 		break;
 	case SBI_EXT_BASE_PROBE_EXT:
-		ret = sbi_ecall_base_probe(scratch, args[0], out_val);
+		ret = sbi_ecall_base_probe(args[0], out_val);
 		break;
 	default:
 		ret = SBI_ENOTSUPP;

lib/sbi/sbi_ecall_hsm.c

@@ -0,0 +1,51 @@
+/*
+ * SPDX-License-Identifier: BSD-2-Clause
+ *
+ * Copyright (c) 2020 Western Digital Corporation or its affiliates.
+ *
+ * Authors:
+ *   Atish Patra <atish.patra@wdc.com>
+ */
+
+#include <sbi/sbi_ecall.h>
+#include <sbi/sbi_ecall_interface.h>
+#include <sbi/sbi_error.h>
+#include <sbi/sbi_version.h>
+#include <sbi/sbi_hsm.h>
+#include <sbi/sbi_scratch.h>
+#include <sbi/riscv_asm.h>
+
+static int sbi_ecall_hsm_handler(unsigned long extid, unsigned long funcid,
+				 unsigned long *args, unsigned long *out_val,
+				 struct sbi_trap_info *out_trap)
+{
+	int ret = 0, hstate;
+	struct sbi_scratch *scratch = sbi_scratch_thishart_ptr();
+
+	switch (funcid) {
+	case SBI_EXT_HSM_HART_START:
+		ret = sbi_hsm_hart_start(scratch, args[0], args[1], args[2]);
+		break;
+	case SBI_EXT_HSM_HART_STOP:
+		ret = sbi_hsm_hart_stop(scratch, TRUE);
+		break;
+	case SBI_EXT_HSM_HART_GET_STATUS:
+		hstate = sbi_hsm_hart_get_state(args[0]);
+		ret = sbi_hsm_hart_state_to_status(hstate);
+		break;
+	default:
+		ret = SBI_ENOTSUPP;
+	};
+	if (ret >= 0) {
+		*out_val = ret;
+		ret = 0;
+	}
+
+	return ret;
+}
+
+struct sbi_ecall_extension ecall_hsm = {
+	.extid_start = SBI_EXT_HSM,
+	.extid_end = SBI_EXT_HSM,
+	.handle = sbi_ecall_hsm_handler,
+};

lib/sbi/sbi_ecall_legacy.c

@@ -8,11 +8,14 @@
  *   Atish Patra <atish.patra@wdc.com>
  */
 
+#include <sbi/riscv_asm.h>
 #include <sbi/sbi_console.h>
 #include <sbi/sbi_ecall.h>
 #include <sbi/sbi_ecall_interface.h>
 #include <sbi/sbi_error.h>
+#include <sbi/sbi_hsm.h>
 #include <sbi/sbi_ipi.h>
+#include <sbi/sbi_platform.h>
 #include <sbi/sbi_system.h>
 #include <sbi/sbi_timer.h>
 #include <sbi/sbi_tlb.h>
@@ -20,40 +23,38 @@
 #include <sbi/sbi_unpriv.h>
 #include <sbi/sbi_hart.h>
 
-static int sbi_load_hart_mask_unpriv(struct sbi_scratch *scratch,
-				     ulong *pmask, ulong *hmask,
+static int sbi_load_hart_mask_unpriv(ulong *pmask, ulong *hmask,
 				     struct sbi_trap_info *uptrap)
 {
 	ulong mask = 0;
 
 	if (pmask) {
-		mask = sbi_load_ulong(pmask, scratch, uptrap);
+		mask = sbi_load_ulong(pmask, uptrap);
 		if (uptrap->cause)
 			return SBI_ETRAP;
 	} else {
-		mask = sbi_hart_available_mask();
+		sbi_hsm_hart_started_mask(0, &mask);
 	}
 	*hmask = mask;
+
 	return 0;
 }
 
-static int sbi_ecall_legacy_handler(struct sbi_scratch *scratch,
-				    unsigned long extid, unsigned long funcid,
+static int sbi_ecall_legacy_handler(unsigned long extid, unsigned long funcid,
 				    unsigned long *args, unsigned long *out_val,
 				    struct sbi_trap_info *out_trap)
 {
 	int ret = 0;
 	struct sbi_tlb_info tlb_info;
-	u32 source_hart = sbi_current_hartid();
+	u32 source_hart = current_hartid();
 	ulong hmask = 0;
 
 	switch (extid) {
 	case SBI_EXT_0_1_SET_TIMER:
 #if __riscv_xlen == 32
-		sbi_timer_event_start(scratch,
-				      (((u64)args[1] << 32) | (u64)args[0]));
+		sbi_timer_event_start((((u64)args[1] << 32) | (u64)args[0]));
 #else
-		sbi_timer_event_start(scratch, (u64)args[0]);
+		sbi_timer_event_start((u64)args[0]);
 #endif
 		break;
 	case SBI_EXT_0_1_CONSOLE_PUTCHAR:
@@ -63,47 +64,44 @@ static int sbi_ecall_legacy_handler(struct sbi_scratch *scratch,
 		ret = sbi_getc();
 		break;
 	case SBI_EXT_0_1_CLEAR_IPI:
-		sbi_ipi_clear_smode(scratch);
+		sbi_ipi_clear_smode();
 		break;
 	case SBI_EXT_0_1_SEND_IPI:
-		ret = sbi_load_hart_mask_unpriv(scratch, (ulong *)args[0],
+		ret = sbi_load_hart_mask_unpriv((ulong *)args[0],
 						&hmask, out_trap);
 		if (ret != SBI_ETRAP)
-			ret = sbi_ipi_send_smode(scratch, hmask, 0);
+			ret = sbi_ipi_send_smode(hmask, 0);
 		break;
 	case SBI_EXT_0_1_REMOTE_FENCE_I:
-		tlb_info.start  = 0;
-		tlb_info.size  = 0;
-		tlb_info.type  = SBI_ITLB_FLUSH;
-		tlb_info.shart_mask = 1UL << source_hart;
-		ret = sbi_load_hart_mask_unpriv(scratch, (ulong *)args[0],
+		ret = sbi_load_hart_mask_unpriv((ulong *)args[0],
 						&hmask, out_trap);
-		if (ret != SBI_ETRAP)
-			ret = sbi_tlb_request(scratch, hmask, 0, &tlb_info);
+		if (ret != SBI_ETRAP) {
+			SBI_TLB_INFO_INIT(&tlb_info, 0, 0, 0, 0,
+					  SBI_ITLB_FLUSH, source_hart);
+			ret = sbi_tlb_request(hmask, 0, &tlb_info);
+		}
 		break;
 	case SBI_EXT_0_1_REMOTE_SFENCE_VMA:
-		tlb_info.start = (unsigned long)args[1];
-		tlb_info.size  = (unsigned long)args[2];
-		tlb_info.type  = SBI_TLB_FLUSH_VMA;
-		tlb_info.shart_mask = 1UL << source_hart;
-		ret = sbi_load_hart_mask_unpriv(scratch, (ulong *)args[0],
+		ret = sbi_load_hart_mask_unpriv((ulong *)args[0],
 						&hmask, out_trap);
-		if (ret != SBI_ETRAP)
-			ret = sbi_tlb_request(scratch, hmask, 0, &tlb_info);
+		if (ret != SBI_ETRAP) {
+			SBI_TLB_INFO_INIT(&tlb_info, args[1], args[2], 0, 0,
+					  SBI_TLB_FLUSH_VMA, source_hart);
+			ret = sbi_tlb_request(hmask, 0, &tlb_info);
+		}
 		break;
 	case SBI_EXT_0_1_REMOTE_SFENCE_VMA_ASID:
-		tlb_info.start = (unsigned long)args[1];
-		tlb_info.size  = (unsigned long)args[2];
-		tlb_info.asid  = (unsigned long)args[3];
-		tlb_info.type  = SBI_TLB_FLUSH_VMA_ASID;
-		tlb_info.shart_mask = 1UL << source_hart;
-		ret = sbi_load_hart_mask_unpriv(scratch, (ulong *)args[0],
+		ret = sbi_load_hart_mask_unpriv((ulong *)args[0],
 						&hmask, out_trap);
-		if (ret != SBI_ETRAP)
-			ret = sbi_tlb_request(scratch, hmask, 0, &tlb_info);
+		if (ret != SBI_ETRAP) {
+			SBI_TLB_INFO_INIT(&tlb_info, args[1], args[2], args[3],
+					  0, SBI_TLB_FLUSH_VMA_ASID,
+					  source_hart);
+			ret = sbi_tlb_request(hmask, 0, &tlb_info);
+		}
 		break;
 	case SBI_EXT_0_1_SHUTDOWN:
-		sbi_system_shutdown(scratch, 0);
+		sbi_system_reset(SBI_PLATFORM_RESET_SHUTDOWN);
 		break;
 	default:
 		ret = SBI_ENOTSUPP;

lib/sbi/sbi_ecall_replace.c

@@ -8,6 +8,7 @@
  *   Atish Patra <atish.patra@wdc.com>
  */
 
+#include <sbi/riscv_asm.h>
 #include <sbi/sbi_ecall.h>
 #include <sbi/sbi_ecall_interface.h>
 #include <sbi/sbi_error.h>
@@ -15,10 +16,8 @@
 #include <sbi/sbi_ipi.h>
 #include <sbi/sbi_timer.h>
 #include <sbi/sbi_tlb.h>
-#include <sbi/riscv_asm.h>
 
-static int sbi_ecall_time_handler(struct sbi_scratch *scratch,
-				  unsigned long extid, unsigned long funcid,
+static int sbi_ecall_time_handler(unsigned long extid, unsigned long funcid,
 				  unsigned long *args, unsigned long *out_val,
 				  struct sbi_trap_info *out_trap)
 {
@@ -26,10 +25,9 @@ static int sbi_ecall_time_handler(struct sbi_scratch *scratch,
 
 	if (funcid == SBI_EXT_TIME_SET_TIMER) {
 #if __riscv_xlen == 32
-		sbi_timer_event_start(scratch,
-				      (((u64)args[1] << 32) | (u64)args[0]));
+		sbi_timer_event_start((((u64)args[1] << 32) | (u64)args[0]));
 #else
-		sbi_timer_event_start(scratch, (u64)args[0]);
+		sbi_timer_event_start((u64)args[0]);
 #endif
 	} else
 		ret = SBI_ENOTSUPP;
@@ -43,14 +41,14 @@ struct sbi_ecall_extension ecall_time = {
 	.handle = sbi_ecall_time_handler,
 };
 
-static int sbi_ecall_rfence_handler(struct sbi_scratch *scratch,
-				    unsigned long extid, unsigned long funcid,
+static int sbi_ecall_rfence_handler(unsigned long extid, unsigned long funcid,
 				    unsigned long *args, unsigned long *out_val,
 				    struct sbi_trap_info *out_trap)
 {
 	int ret = 0;
+	unsigned long vmid;
 	struct sbi_tlb_info tlb_info;
-	u32 source_hart = sbi_current_hartid();
+	u32 source_hart = current_hartid();
 
 	if (funcid >= SBI_EXT_RFENCE_REMOTE_HFENCE_GVMA &&
 	    funcid <= SBI_EXT_RFENCE_REMOTE_HFENCE_VVMA_ASID)
@@ -59,58 +57,44 @@ static int sbi_ecall_rfence_handler(struct sbi_scratch *scratch,
 
 	switch (funcid) {
 	case SBI_EXT_RFENCE_REMOTE_FENCE_I:
-		tlb_info.start  = 0;
-		tlb_info.size  = 0;
-		tlb_info.type  = SBI_ITLB_FLUSH;
-		tlb_info.shart_mask = 1UL << source_hart;
-		ret = sbi_tlb_request(scratch, args[0], args[1], &tlb_info);
+		SBI_TLB_INFO_INIT(&tlb_info, 0, 0, 0, 0,
+				  SBI_ITLB_FLUSH, source_hart);
+		ret = sbi_tlb_request(args[0], args[1], &tlb_info);
 		break;
 	case SBI_EXT_RFENCE_REMOTE_HFENCE_GVMA:
-		tlb_info.start = (unsigned long)args[2];
-		tlb_info.size  = (unsigned long)args[3];
-		tlb_info.type  = SBI_TLB_FLUSH_GVMA;
-		tlb_info.shart_mask = 1UL << source_hart;
-		ret = sbi_tlb_request(scratch, args[0], args[1], &tlb_info);
+		SBI_TLB_INFO_INIT(&tlb_info, args[2], args[3], 0, 0,
+				  SBI_TLB_FLUSH_GVMA, source_hart);
+		ret = sbi_tlb_request(args[0], args[1], &tlb_info);
 		break;
 	case SBI_EXT_RFENCE_REMOTE_HFENCE_GVMA_VMID:
-		tlb_info.start = (unsigned long)args[2];
-		tlb_info.size  = (unsigned long)args[3];
-		tlb_info.asid  = (unsigned long)args[4];
-		tlb_info.type  = SBI_TLB_FLUSH_GVMA_VMID;
-		tlb_info.shart_mask = 1UL << source_hart;
-		ret = sbi_tlb_request(scratch, args[0], args[1], &tlb_info);
+		SBI_TLB_INFO_INIT(&tlb_info, args[2], args[3], 0, args[4],
+				  SBI_TLB_FLUSH_GVMA_VMID, source_hart);
+		ret = sbi_tlb_request(args[0], args[1], &tlb_info);
 		break;
 	case SBI_EXT_RFENCE_REMOTE_HFENCE_VVMA:
-		tlb_info.start = (unsigned long)args[2];
-		tlb_info.size  = (unsigned long)args[3];
-		tlb_info.type  = SBI_TLB_FLUSH_VVMA;
-		tlb_info.shart_mask = 1UL << source_hart;
-		ret = sbi_tlb_request(scratch, args[0], args[1], &tlb_info);
+		vmid = (csr_read(CSR_HGATP) & HGATP_VMID_MASK);
+		vmid = vmid >> HGATP_VMID_SHIFT;
+		SBI_TLB_INFO_INIT(&tlb_info, args[2], args[3], 0, vmid,
+				  SBI_TLB_FLUSH_VVMA, source_hart);
+		ret = sbi_tlb_request(args[0], args[1], &tlb_info);
 		break;
 	case SBI_EXT_RFENCE_REMOTE_HFENCE_VVMA_ASID:
-		tlb_info.start = (unsigned long)args[2];
-		tlb_info.size  = (unsigned long)args[3];
-		tlb_info.asid  = (unsigned long)args[4];
-		tlb_info.type  = SBI_TLB_FLUSH_VVMA_ASID;
-		tlb_info.shart_mask = 1UL << source_hart;
-		ret = sbi_tlb_request(scratch, args[0], args[1], &tlb_info);
+		vmid = (csr_read(CSR_HGATP) & HGATP_VMID_MASK);
+		vmid = vmid >> HGATP_VMID_SHIFT;
+		SBI_TLB_INFO_INIT(&tlb_info, args[2], args[3], args[4], vmid,
+				  SBI_TLB_FLUSH_VVMA_ASID, source_hart);
+		ret = sbi_tlb_request(args[0], args[1], &tlb_info);
 		break;
 	case SBI_EXT_RFENCE_REMOTE_SFENCE_VMA:
-		tlb_info.start = (unsigned long)args[2];
-		tlb_info.size  = (unsigned long)args[3];
-		tlb_info.type  = SBI_TLB_FLUSH_VMA;
-		tlb_info.shart_mask = 1UL << source_hart;
-		ret = sbi_tlb_request(scratch, args[0], args[1], &tlb_info);
+		SBI_TLB_INFO_INIT(&tlb_info, args[2], args[3], 0, 0,
+				  SBI_TLB_FLUSH_VMA, source_hart);
+		ret = sbi_tlb_request(args[0], args[1], &tlb_info);
 		break;
 	case SBI_EXT_RFENCE_REMOTE_SFENCE_VMA_ASID:
-		tlb_info.start = (unsigned long)args[2];
-		tlb_info.size  = (unsigned long)args[3];
-		tlb_info.asid  = (unsigned long)args[4];
-		tlb_info.type  = SBI_TLB_FLUSH_VMA_ASID;
-		tlb_info.shart_mask = 1UL << source_hart;
-		ret = sbi_tlb_request(scratch, args[0], args[1], &tlb_info);
+		SBI_TLB_INFO_INIT(&tlb_info, args[2], args[3], args[4], 0,
+				  SBI_TLB_FLUSH_VMA_ASID, source_hart);
+		ret = sbi_tlb_request(args[0], args[1], &tlb_info);
 		break;
-
 	default:
 		ret = SBI_ENOTSUPP;
 	};
@@ -124,15 +108,14 @@ struct sbi_ecall_extension ecall_rfence = {
 	.handle = sbi_ecall_rfence_handler,
 };
 
-static int sbi_ecall_ipi_handler(struct sbi_scratch *scratch,
-				 unsigned long extid, unsigned long funcid,
+static int sbi_ecall_ipi_handler(unsigned long extid, unsigned long funcid,
 				 unsigned long *args, unsigned long *out_val,
 				 struct sbi_trap_info *out_trap)
 {
 	int ret = 0;
 
 	if (funcid == SBI_EXT_IPI_SEND_IPI)
-		ret = sbi_ipi_send_smode(scratch, args[0], args[1]);
+		ret = sbi_ipi_send_smode(args[0], args[1]);
 	else
 		ret = SBI_ENOTSUPP;
 

lib/sbi/sbi_ecall_vendor.c

@@ -13,21 +13,19 @@
 #include <sbi/sbi_error.h>
 #include <sbi/sbi_platform.h>
 
-static int sbi_ecall_vendor_probe(struct sbi_scratch *scratch,
-				  unsigned long extid,
+static int sbi_ecall_vendor_probe(unsigned long extid,
 				  unsigned long *out_val)
 {
-	*out_val = sbi_platform_vendor_ext_check(sbi_platform_ptr(scratch),
+	*out_val = sbi_platform_vendor_ext_check(sbi_platform_thishart_ptr(),
 						 extid);
 	return 0;
 }
 
-static int sbi_ecall_vendor_handler(struct sbi_scratch *scratch,
-				    unsigned long extid, unsigned long funcid,
+static int sbi_ecall_vendor_handler(unsigned long extid, unsigned long funcid,
 				    unsigned long *args, unsigned long *out_val,
 				    struct sbi_trap_info *out_trap)
 {
-	return sbi_platform_vendor_ext_provider(sbi_platform_ptr(scratch),
+	return sbi_platform_vendor_ext_provider(sbi_platform_thishart_ptr(),
 						extid, funcid, args,
 						out_val, out_trap);
 }

lib/sbi/sbi_emulate_csr.c

@@ -9,15 +9,15 @@
 
 #include <sbi/riscv_asm.h>
 #include <sbi/riscv_encoding.h>
-#include <sbi/sbi_bits.h>
+#include <sbi/sbi_bitops.h>
 #include <sbi/sbi_console.h>
 #include <sbi/sbi_emulate_csr.h>
 #include <sbi/sbi_error.h>
 #include <sbi/sbi_timer.h>
 #include <sbi/sbi_trap.h>
 
-int sbi_emulate_csr_read(int csr_num, u32 hartid, struct sbi_trap_regs *regs,
-			 struct sbi_scratch *scratch, ulong *csr_val)
+int sbi_emulate_csr_read(int csr_num, struct sbi_trap_regs *regs,
+			 ulong *csr_val)
 {
 	int ret = 0;
 	ulong cen = -1UL;
@@ -34,7 +34,7 @@ int sbi_emulate_csr_read(int csr_num, u32 hartid, struct sbi_trap_regs *regs,
 	switch (csr_num) {
 	case CSR_HTIMEDELTA:
 		if (prev_mode == PRV_S && !virt)
-			*csr_val = sbi_timer_get_delta(scratch);
+			*csr_val = sbi_timer_get_delta();
 		else
 			ret = SBI_ENOTSUPP;
 		break;
@@ -46,8 +46,8 @@ int sbi_emulate_csr_read(int csr_num, u32 hartid, struct sbi_trap_regs *regs,
 	case CSR_TIME:
 		if (!((cen >> (CSR_TIME - CSR_CYCLE)) & 1))
 			return -1;
-		*csr_val = (virt) ? sbi_timer_virt_value(scratch):
-				    sbi_timer_value(scratch);
+		*csr_val = (virt) ? sbi_timer_virt_value():
+				    sbi_timer_value();
 		break;
 	case CSR_INSTRET:
 		if (!((cen >> (CSR_INSTRET - CSR_CYCLE)) & 1))
@@ -67,7 +67,7 @@ int sbi_emulate_csr_read(int csr_num, u32 hartid, struct sbi_trap_regs *regs,
 #if __riscv_xlen == 32
 	case CSR_HTIMEDELTAH:
 		if (prev_mode == PRV_S && !virt)
-			*csr_val = sbi_timer_get_delta(scratch) >> 32;
+			*csr_val = sbi_timer_get_delta() >> 32;
 		else
 			ret = SBI_ENOTSUPP;
 		break;
@@ -79,8 +79,8 @@ int sbi_emulate_csr_read(int csr_num, u32 hartid, struct sbi_trap_regs *regs,
 	case CSR_TIMEH:
 		if (!((cen >> (CSR_TIME - CSR_CYCLE)) & 1))
 			return -1;
-		*csr_val = (virt) ? sbi_timer_virt_value(scratch) >> 32:
-				    sbi_timer_value(scratch) >> 32;
+		*csr_val = (virt) ? sbi_timer_virt_value() >> 32:
+				    sbi_timer_value() >> 32;
 		break;
 	case CSR_INSTRETH:
 		if (!((cen >> (CSR_INSTRET - CSR_CYCLE)) & 1))
@@ -110,14 +110,14 @@ int sbi_emulate_csr_read(int csr_num, u32 hartid, struct sbi_trap_regs *regs,
 	};
 
 	if (ret)
-		sbi_dprintf(scratch, "%s: hartid%d: invalid csr_num=0x%x\n",
-			    __func__, hartid, csr_num);
+		sbi_dprintf("%s: hartid%d: invalid csr_num=0x%x\n",
+			    __func__, current_hartid(), csr_num);
 
 	return ret;
 }
 
-int sbi_emulate_csr_write(int csr_num, u32 hartid, struct sbi_trap_regs *regs,
-			  struct sbi_scratch *scratch, ulong csr_val)
+int sbi_emulate_csr_write(int csr_num, struct sbi_trap_regs *regs,
+			  ulong csr_val)
 {
 	int ret = 0;
 	ulong prev_mode = (regs->mstatus & MSTATUS_MPP) >> MSTATUS_MPP_SHIFT;
@@ -130,7 +130,7 @@ int sbi_emulate_csr_write(int csr_num, u32 hartid, struct sbi_trap_regs *regs,
 	switch (csr_num) {
 	case CSR_HTIMEDELTA:
 		if (prev_mode == PRV_S && !virt)
-			sbi_timer_set_delta(scratch, csr_val);
+			sbi_timer_set_delta(csr_val);
 		else
 			ret = SBI_ENOTSUPP;
 		break;
@@ -149,7 +149,7 @@ int sbi_emulate_csr_write(int csr_num, u32 hartid, struct sbi_trap_regs *regs,
 #if __riscv_xlen == 32
 	case CSR_HTIMEDELTAH:
 		if (prev_mode == PRV_S && !virt)
-			sbi_timer_set_delta_upper(scratch, csr_val);
+			sbi_timer_set_delta_upper(csr_val);
 		else
 			ret = SBI_ENOTSUPP;
 		break;
@@ -178,8 +178,8 @@ int sbi_emulate_csr_write(int csr_num, u32 hartid, struct sbi_trap_regs *regs,
 	};
 
 	if (ret)
-		sbi_dprintf(scratch, "%s: hartid%d: invalid csr_num=0x%x\n",
-			    __func__, hartid, csr_num);
+		sbi_dprintf("%s: hartid%d: invalid csr_num=0x%x\n",
+			    __func__, current_hartid(), csr_num);
 
 	return ret;
 }

lib/sbi/sbi_expected_trap.S

@@ -0,0 +1,56 @@
+/*
+ * SPDX-License-Identifier: BSD-2-Clause
+ *
+ * Copyright (c) 2020 Western Digital Corporation or its affiliates.
+ *
+ * Authors:
+ *   Anup Patel <anup.patel@wdc.com>
+ */
+
+#include <sbi/riscv_asm.h>
+#include <sbi/sbi_trap.h>
+
+	/*
+	 * We assume that faulting instruction is is 4-byte long and blindly
+	 * increment SEPC by 4.
+	 *
+	 * The trap info will be saved as follows:
+	 * A3 <- pointer struct sbi_trap_info
+	 * A4 <- temporary
+	 */
+
+	.align 3
+	.global __sbi_expected_trap
+__sbi_expected_trap:
+	/* Without H-extension so, MTVAL2 and MTINST CSRs not available */
+	csrr	a4, CSR_MEPC
+	REG_S	a4, SBI_TRAP_INFO_OFFSET(epc)(a3)
+	csrr	a4, CSR_MCAUSE
+	REG_S	a4, SBI_TRAP_INFO_OFFSET(cause)(a3)
+	csrr	a4, CSR_MTVAL
+	REG_S	a4, SBI_TRAP_INFO_OFFSET(tval)(a3)
+	REG_S	zero, SBI_TRAP_INFO_OFFSET(tval2)(a3)
+	REG_S	zero, SBI_TRAP_INFO_OFFSET(tinst)(a3)
+	csrr	a4, CSR_MEPC
+	addi	a4, a4, 4
+	csrw	CSR_MEPC, a4
+	mret
+
+	.align 3
+	.global __sbi_expected_trap_hext
+__sbi_expected_trap_hext:
+	/* With H-extension so, MTVAL2 and MTINST CSRs available */
+	csrr	a4, CSR_MEPC
+	REG_S	a4, SBI_TRAP_INFO_OFFSET(epc)(a3)
+	csrr	a4, CSR_MCAUSE
+	REG_S	a4, SBI_TRAP_INFO_OFFSET(cause)(a3)
+	csrr	a4, CSR_MTVAL
+	REG_S	a4, SBI_TRAP_INFO_OFFSET(tval)(a3)
+	csrr	a4, CSR_MTVAL2
+	REG_S	a4, SBI_TRAP_INFO_OFFSET(tval2)(a3)
+	csrr	a4, CSR_MTINST
+	REG_S	a4, SBI_TRAP_INFO_OFFSET(tinst)(a3)
+	csrr	a4, CSR_MEPC
+	addi	a4, a4, 4
+	csrw	CSR_MEPC, a4
+	mret

lib/sbi/sbi_hart.c

@@ -11,33 +11,45 @@
 #include <sbi/riscv_barrier.h>
 #include <sbi/riscv_encoding.h>
 #include <sbi/riscv_fp.h>
-#include <sbi/riscv_locks.h>
-#include <sbi/sbi_bits.h>
+#include <sbi/sbi_bitops.h>
 #include <sbi/sbi_console.h>
+#include <sbi/sbi_csr_detect.h>
 #include <sbi/sbi_error.h>
 #include <sbi/sbi_hart.h>
+#include <sbi/sbi_math.h>
 #include <sbi/sbi_platform.h>
+#include <sbi/sbi_string.h>
 
-/**
- * Return HART ID of the caller.
- */
-unsigned int sbi_current_hartid()
-{
-	return (u32)csr_read(CSR_MHARTID);
-}
+extern void __sbi_expected_trap(void);
+extern void __sbi_expected_trap_hext(void);
+
+void (*sbi_hart_expected_trap)(void) = &__sbi_expected_trap;
+
+struct hart_features {
+	unsigned long features;
+	unsigned int pmp_count;
+};
+static unsigned long hart_features_offset;
 
 static void mstatus_init(struct sbi_scratch *scratch, u32 hartid)
 {
-	const struct sbi_platform *plat = sbi_platform_ptr(scratch);
+	unsigned long mstatus_val = 0;
 
 	/* Enable FPU */
 	if (misa_extension('D') || misa_extension('F'))
-		csr_write(CSR_MSTATUS, MSTATUS_FS);
+		mstatus_val |=  MSTATUS_FS;
+
+	/* Enable Vector context */
+	if (misa_extension('V'))
+		mstatus_val |=  MSTATUS_VS;
+
+	csr_write(CSR_MSTATUS, mstatus_val);
 
 	/* Enable user/supervisor use of perf counters */
-	if (misa_extension('S') && sbi_platform_has_scounteren(plat))
+	if (misa_extension('S') &&
+	    sbi_hart_has_feature(scratch, SBI_HART_HAS_SCOUNTEREN))
 		csr_write(CSR_SCOUNTEREN, -1);
-	if (sbi_platform_has_mcounteren(plat))
+	if (sbi_hart_has_feature(scratch, SBI_HART_HAS_MCOUNTEREN))
 		csr_write(CSR_MCOUNTEREN, -1);
 
 	/* Disable all interrupts */
@@ -75,7 +87,7 @@ static int delegate_traps(struct sbi_scratch *scratch, u32 hartid)
 	unsigned long interrupts, exceptions;
 
 	if (!misa_extension('S'))
-		/* No delegation possible as mideleg does not exist*/
+		/* No delegation possible as mideleg does not exist */
 		return 0;
 
 	/* Send M-mode interrupts and most exceptions to S-mode */
@@ -98,6 +110,7 @@ static int delegate_traps(struct sbi_scratch *scratch, u32 hartid)
 		exceptions |= (1U << CAUSE_SUPERVISOR_ECALL);
 		exceptions |= (1U << CAUSE_FETCH_GUEST_PAGE_FAULT);
 		exceptions |= (1U << CAUSE_LOAD_GUEST_PAGE_FAULT);
+		exceptions |= (1U << CAUSE_VIRTUAL_INST_FAULT);
 		exceptions |= (1U << CAUSE_STORE_GUEST_PAGE_FAULT);
 	}
 
@@ -109,6 +122,10 @@ static int delegate_traps(struct sbi_scratch *scratch, u32 hartid)
 
 void sbi_hart_delegation_dump(struct sbi_scratch *scratch)
 {
+	if (!misa_extension('S'))
+		/* No delegation possible as mideleg does not exist*/
+		return;
+
 #if __riscv_xlen == 32
 	sbi_printf("MIDELEG : 0x%08lx\n", csr_read(CSR_MIDELEG));
 	sbi_printf("MEDELEG : 0x%08lx\n", csr_read(CSR_MEDELEG));
@@ -118,36 +135,37 @@ void sbi_hart_delegation_dump(struct sbi_scratch *scratch)
 #endif
 }
 
-unsigned long log2roundup(unsigned long x)
+unsigned int sbi_hart_pmp_count(struct sbi_scratch *scratch)
 {
-	unsigned long ret = 0;
+	struct hart_features *hfeatures =
+			sbi_scratch_offset_ptr(scratch, hart_features_offset);
 
-	while (ret < __riscv_xlen) {
-		if (x <= (1UL << ret))
-			break;
-		ret++;
-	}
+	return hfeatures->pmp_count;
+}
 
-	return ret;
+int sbi_hart_pmp_get(struct sbi_scratch *scratch, unsigned int n,
+		     unsigned long *prot_out, unsigned long *addr_out,
+		     unsigned long *size)
+{
+	if (sbi_hart_pmp_count(scratch) <= n)
+		return SBI_EINVAL;
+
+	return pmp_get(n, prot_out, addr_out, size);
 }
 
 void sbi_hart_pmp_dump(struct sbi_scratch *scratch)
 {
-	const struct sbi_platform *plat = sbi_platform_ptr(scratch);
-	unsigned long prot, addr, size, l2l;
-	unsigned int i;
+	unsigned long prot, addr, size;
+	unsigned int i, pmp_count;
 
-	if (!sbi_platform_has_pmp(plat))
+	if (!sbi_hart_has_feature(scratch, SBI_HART_HAS_PMP))
 		return;
 
-	for (i = 0; i < PMP_COUNT; i++) {
-		pmp_get(i, &prot, &addr, &l2l);
+	pmp_count = sbi_hart_pmp_count(scratch);
+	for (i = 0; i < pmp_count; i++) {
+		pmp_get(i, &prot, &addr, &size);
 		if (!(prot & PMP_A))
 			continue;
-		if (l2l < __riscv_xlen)
-			size = (1UL << l2l);
-		else
-			size = 0;
 #if __riscv_xlen == 32
 		sbi_printf("PMP%d    : 0x%08lx-0x%08lx (A",
 #else
@@ -166,48 +184,243 @@ void sbi_hart_pmp_dump(struct sbi_scratch *scratch)
 	}
 }
 
+int sbi_hart_pmp_check_addr(struct sbi_scratch *scratch, unsigned long addr,
+			    unsigned long attr)
+{
+	unsigned long prot, size, tempaddr;
+	unsigned int i, pmp_count;
+
+	if (!sbi_hart_has_feature(scratch, SBI_HART_HAS_PMP))
+		return SBI_OK;
+
+	pmp_count = sbi_hart_pmp_count(scratch);
+	for (i = 0; i < pmp_count; i++) {
+		pmp_get(i, &prot, &tempaddr, &size);
+		if (!(prot & PMP_A))
+			continue;
+		if (tempaddr <= addr && addr <= tempaddr + size)
+			if (!(prot & attr))
+				return SBI_EINVALID_ADDR;
+	}
+
+	return SBI_OK;
+}
+
 static int pmp_init(struct sbi_scratch *scratch, u32 hartid)
 {
-	u32 i, count;
+	u32 i, pmp_idx = 0, pmp_count, count;
 	unsigned long fw_start, fw_size_log2;
 	ulong prot, addr, log2size;
 	const struct sbi_platform *plat = sbi_platform_ptr(scratch);
 
-	if (!sbi_platform_has_pmp(plat))
+	if (!sbi_hart_has_feature(scratch, SBI_HART_HAS_PMP))
 		return 0;
 
+	/* Firmware PMP region to protect OpenSBI firmware */
 	fw_size_log2 = log2roundup(scratch->fw_size);
-	fw_start     = scratch->fw_start & ~((1UL << fw_size_log2) - 1UL);
-
-	pmp_set(0, 0, fw_start, fw_size_log2);
+	fw_start = scratch->fw_start & ~((1UL << fw_size_log2) - 1UL);
+	pmp_set(pmp_idx++, 0, fw_start, fw_size_log2);
 
+	/* Platform specific PMP regions */
 	count = sbi_platform_pmp_region_count(plat, hartid);
-	if ((PMP_COUNT - 1) < count)
-		count = (PMP_COUNT - 1);
-
-	for (i = 0; i < count; i++) {
+	pmp_count = sbi_hart_pmp_count(scratch);
+	for (i = 0; i < count && pmp_idx < (pmp_count - 1); i++) {
 		if (sbi_platform_pmp_region_info(plat, hartid, i, &prot, &addr,
 						 &log2size))
 			continue;
-		pmp_set(i + 1, prot, addr, log2size);
+		pmp_set(pmp_idx++, prot, addr, log2size);
 	}
 
+	/*
+	 * Default PMP region for allowing S-mode and U-mode access to
+	 * memory not covered by:
+	 * 1) Firmware PMP region
+	 * 2) Platform specific PMP regions
+	 */
+	pmp_set(pmp_idx++, PMP_R | PMP_W | PMP_X, 0, __riscv_xlen);
+
 	return 0;
 }
 
-static unsigned long trap_info_offset;
+/**
+ * Check whether a particular hart feature is available
+ *
+ * @param scratch pointer to the HART scratch space
+ * @param feature the feature to check
+ * @returns true (feature available) or false (feature not available)
+ */
+bool sbi_hart_has_feature(struct sbi_scratch *scratch, unsigned long feature)
+{
+	struct hart_features *hfeatures =
+			sbi_scratch_offset_ptr(scratch, hart_features_offset);
+
+	if (hfeatures->features & feature)
+		return true;
+	else
+		return false;
+}
+
+static unsigned long hart_get_features(struct sbi_scratch *scratch)
+{
+	struct hart_features *hfeatures =
+			sbi_scratch_offset_ptr(scratch, hart_features_offset);
+
+	return hfeatures->features;
+}
+
+static inline char *sbi_hart_feature_id2string(unsigned long feature)
+{
+	char *fstr = NULL;
+
+	if (!feature)
+		return NULL;
+
+	switch (feature) {
+	case SBI_HART_HAS_PMP:
+		fstr = "pmp";
+		break;
+	case SBI_HART_HAS_SCOUNTEREN:
+		fstr = "scounteren";
+		break;
+	case SBI_HART_HAS_MCOUNTEREN:
+		fstr = "mcounteren";
+		break;
+	case SBI_HART_HAS_TIME:
+		fstr = "time";
+		break;
+	default:
+		break;
+	}
+
+	return fstr;
+}
+
+/**
+ * Get the hart features in string format
+ *
+ * @param scratch pointer to the HART scratch space
+ * @param features_str pointer to a char array where the features string will be
+ *		       updated
+ * @param nfstr length of the features_str. The feature string will be truncated
+ *		if nfstr is not long enough.
+ */
+void sbi_hart_get_features_str(struct sbi_scratch *scratch,
+			       char *features_str, int nfstr)
+{
+	unsigned long features, feat = 1UL;
+	char *temp;
+	int offset = 0;
+
+	if (!features_str || nfstr <= 0)
+		return;
+	sbi_memset(features_str, 0, nfstr);
+
+	features = hart_get_features(scratch);
+	if (!features)
+		goto done;
+
+	do {
+		if (features & feat) {
+			temp = sbi_hart_feature_id2string(feat);
+			if (temp) {
+				sbi_snprintf(features_str + offset, nfstr,
+					     "%s,", temp);
+				offset = offset + sbi_strlen(temp) + 1;
+			}
+		}
+		feat = feat << 1;
+	} while (feat <= SBI_HART_HAS_LAST_FEATURE);
+
+done:
+	if (offset)
+		features_str[offset - 1] = '\0';
+	else
+		sbi_strncpy(features_str, "none", nfstr);
+}
+
+static void hart_detect_features(struct sbi_scratch *scratch)
+{
+	struct sbi_trap_info trap = {0};
+	struct hart_features *hfeatures;
+	unsigned long val;
+
+	/* Reset hart features */
+	hfeatures = sbi_scratch_offset_ptr(scratch, hart_features_offset);
+	hfeatures->features = 0;
+	hfeatures->pmp_count = 0;
+
+	/* Detect if hart supports PMP feature */
+#define __detect_pmp(__pmp_csr)					\
+	val = csr_read_allowed(__pmp_csr, (ulong)&trap);	\
+	if (!trap.cause) {					\
+		csr_write_allowed(__pmp_csr, (ulong)&trap, val);\
+		if (!trap.cause)				\
+			hfeatures->pmp_count++;			\
+	}
+	__detect_pmp(CSR_PMPADDR0);
+	__detect_pmp(CSR_PMPADDR1);
+	__detect_pmp(CSR_PMPADDR2);
+	__detect_pmp(CSR_PMPADDR3);
+	__detect_pmp(CSR_PMPADDR4);
+	__detect_pmp(CSR_PMPADDR5);
+	__detect_pmp(CSR_PMPADDR6);
+	__detect_pmp(CSR_PMPADDR7);
+	__detect_pmp(CSR_PMPADDR8);
+	__detect_pmp(CSR_PMPADDR9);
+	__detect_pmp(CSR_PMPADDR10);
+	__detect_pmp(CSR_PMPADDR11);
+	__detect_pmp(CSR_PMPADDR12);
+	__detect_pmp(CSR_PMPADDR13);
+	__detect_pmp(CSR_PMPADDR14);
+	__detect_pmp(CSR_PMPADDR15);
+#undef __detect_pmp
+
+	/* Set hart PMP feature if we have at least one PMP region */
+	if (hfeatures->pmp_count)
+		hfeatures->features |= SBI_HART_HAS_PMP;
+
+	/* Detect if hart supports SCOUNTEREN feature */
+	trap.cause = 0;
+	val = csr_read_allowed(CSR_SCOUNTEREN, (unsigned long)&trap);
+	if (!trap.cause) {
+		csr_write_allowed(CSR_SCOUNTEREN, (unsigned long)&trap, val);
+		if (!trap.cause)
+			hfeatures->features |= SBI_HART_HAS_SCOUNTEREN;
+	}
+
+	/* Detect if hart supports MCOUNTEREN feature */
+	trap.cause = 0;
+	val = csr_read_allowed(CSR_MCOUNTEREN, (unsigned long)&trap);
+	if (!trap.cause) {
+		csr_write_allowed(CSR_MCOUNTEREN, (unsigned long)&trap, val);
+		if (!trap.cause)
+			hfeatures->features |= SBI_HART_HAS_MCOUNTEREN;
+	}
+
+	/* Detect if hart supports time CSR */
+	trap.cause = 0;
+	csr_read_allowed(CSR_TIME, (unsigned long)&trap);
+	if (!trap.cause)
+		hfeatures->features |= SBI_HART_HAS_TIME;
+}
 
 int sbi_hart_init(struct sbi_scratch *scratch, u32 hartid, bool cold_boot)
 {
 	int rc;
 
 	if (cold_boot) {
-		trap_info_offset = sbi_scratch_alloc_offset(__SIZEOF_POINTER__,
-							    "HART_TRAP_INFO");
-		if (!trap_info_offset)
+		if (misa_extension('H'))
+			sbi_hart_expected_trap = &__sbi_expected_trap_hext;
+
+		hart_features_offset = sbi_scratch_alloc_offset(
+						sizeof(struct hart_features),
+						"HART_FEATURES");
+		if (!hart_features_offset)
 			return SBI_ENOMEM;
 	}
 
+	hart_detect_features(scratch);
+
 	mstatus_init(scratch, hartid);
 
 	rc = fp_init(hartid);
@@ -221,29 +434,6 @@ int sbi_hart_init(struct sbi_scratch *scratch, u32 hartid, bool cold_boot)
 	return pmp_init(scratch, hartid);
 }
 
-void *sbi_hart_get_trap_info(struct sbi_scratch *scratch)
-{
-	unsigned long *trap_info;
-
-	if (!trap_info_offset)
-		return NULL;
-
-	trap_info = sbi_scratch_offset_ptr(scratch, trap_info_offset);
-
-	return (void *)(*trap_info);
-}
-
-void sbi_hart_set_trap_info(struct sbi_scratch *scratch, void *data)
-{
-	unsigned long *trap_info;
-
-	if (!trap_info_offset)
-		return;
-
-	trap_info = sbi_scratch_offset_ptr(scratch, trap_info_offset);
-	*trap_info = (unsigned long)data;
-}
-
 void __attribute__((noreturn)) sbi_hart_hang(void)
 {
 	while (1)
@@ -316,106 +506,3 @@ sbi_hart_switch_mode(unsigned long arg0, unsigned long arg1,
 	__asm__ __volatile__("mret" : : "r"(a0), "r"(a1));
 	__builtin_unreachable();
 }
-
-static spinlock_t avail_hart_mask_lock	      = SPIN_LOCK_INITIALIZER;
-static volatile unsigned long avail_hart_mask = 0;
-
-void sbi_hart_mark_available(u32 hartid)
-{
-	spin_lock(&avail_hart_mask_lock);
-	avail_hart_mask |= (1UL << hartid);
-	spin_unlock(&avail_hart_mask_lock);
-}
-
-void sbi_hart_unmark_available(u32 hartid)
-{
-	spin_lock(&avail_hart_mask_lock);
-	avail_hart_mask &= ~(1UL << hartid);
-	spin_unlock(&avail_hart_mask_lock);
-}
-
-ulong sbi_hart_available_mask(void)
-{
-	ulong ret;
-
-	spin_lock(&avail_hart_mask_lock);
-	ret = avail_hart_mask;
-	spin_unlock(&avail_hart_mask_lock);
-
-	return ret;
-}
-
-typedef struct sbi_scratch *(*h2s)(ulong hartid);
-
-struct sbi_scratch *sbi_hart_id_to_scratch(struct sbi_scratch *scratch,
-					   u32 hartid)
-{
-	return ((h2s)scratch->hartid_to_scratch)(hartid);
-}
-
-#define COLDBOOT_WAIT_BITMAP_SIZE __riscv_xlen
-static spinlock_t coldboot_lock = SPIN_LOCK_INITIALIZER;
-static unsigned long coldboot_done = 0;
-static unsigned long coldboot_wait_bitmap = 0;
-
-void sbi_hart_wait_for_coldboot(struct sbi_scratch *scratch, u32 hartid)
-{
-	unsigned long saved_mie;
-	const struct sbi_platform *plat = sbi_platform_ptr(scratch);
-
-	if ((sbi_platform_hart_count(plat) <= hartid) ||
-	    (COLDBOOT_WAIT_BITMAP_SIZE <= hartid))
-		sbi_hart_hang();
-
-	/* Save MIE CSR */
-	saved_mie = csr_read(CSR_MIE);
-
-	/* Set MSIE bit to receive IPI */
-	csr_set(CSR_MIE, MIP_MSIP);
-
-	/* Acquire coldboot lock */
-	spin_lock(&coldboot_lock);
-
-	/* Mark current HART as waiting */
-	coldboot_wait_bitmap |= (1UL << hartid);
-
-	/* Wait for coldboot to finish using WFI */
-	while (!coldboot_done) {
-		spin_unlock(&coldboot_lock);
-		wfi();
-		spin_lock(&coldboot_lock);
-	};
-
-	/* Unmark current HART as waiting */
-	coldboot_wait_bitmap &= ~(1UL << hartid);
-
-	/* Release coldboot lock */
-	spin_unlock(&coldboot_lock);
-
-	/* Restore MIE CSR */
-	csr_write(CSR_MIE, saved_mie);
-
-	/* Clear current HART IPI */
-	sbi_platform_ipi_clear(plat, hartid);
-}
-
-void sbi_hart_wake_coldboot_harts(struct sbi_scratch *scratch, u32 hartid)
-{
-	const struct sbi_platform *plat = sbi_platform_ptr(scratch);
-	int max_hart			= sbi_platform_hart_count(plat);
-
-	/* Acquire coldboot lock */
-	spin_lock(&coldboot_lock);
-
-	/* Mark coldboot done */
-	coldboot_done = 1;
-
-	/* Send an IPI to all HARTs waiting for coldboot */
-	for (int i = 0; i < max_hart; i++) {
-		if ((i != hartid) && (coldboot_wait_bitmap & (1UL << i)))
-			sbi_platform_ipi_send(plat, i);
-	}
-
-	/* Release coldboot lock */
-	spin_unlock(&coldboot_lock);
-}

lib/sbi/sbi_hfence.S

@@ -9,67 +9,127 @@
  */
 
 	/*
-	 * Instruction encoding of hfence.gvma is:
+	 * HFENCE.GVMA rs1, rs2
+	 * HFENCE.GVMA zero, rs2
+	 * HFENCE.GVMA rs1
+	 * HFENCE.GVMA
+	 *
+	 * rs1!=zero and rs2!=zero ==> HFENCE.GVMA rs1, rs2
+	 * rs1==zero and rs2!=zero ==> HFENCE.GVMA zero, rs2
+	 * rs1!=zero and rs2==zero ==> HFENCE.GVMA rs1
+	 * rs1==zero and rs2==zero ==> HFENCE.GVMA
+	 *
+	 * Instruction encoding of HFENCE.GVMA is:
 	 * 0110001 rs2(5) rs1(5) 000 00000 1110011
 	 */
 
 	.align 3
 	.global __sbi_hfence_gvma_vmid_gpa
 __sbi_hfence_gvma_vmid_gpa:
-	/* hfence.gvma a1, a0 */
-	.word 0x62a60073
+	/*
+	 * rs1 = a0 (GPA)
+	 * rs2 = a1 (VMID)
+	 * HFENCE.GVMA a0, a1
+	 * 0110001 01011 01010 000 00000 1110011
+	 */
+	.word 0x62b50073
 	ret
 
 	.align 3
 	.global __sbi_hfence_gvma_vmid
 __sbi_hfence_gvma_vmid:
-	/* hfence.gvma zero, a0 */
+	/*
+	 * rs1 = zero
+	 * rs2 = a0 (VMID)
+	 * HFENCE.GVMA zero, a0
+	 * 0110001 01010 00000 000 00000 1110011
+	 */
 	.word 0x62a00073
 	ret
 
 	.align 3
 	.global __sbi_hfence_gvma_gpa
 __sbi_hfence_gvma_gpa:
-	/* hfence.gvma a0 */
+	/*
+	 * rs1 = a0 (GPA)
+	 * rs2 = zero
+	 * HFENCE.GVMA a0
+	 * 0110001 00000 01010 000 00000 1110011
+	 */
 	.word 0x62050073
 	ret
 
 	.align 3
 	.global __sbi_hfence_gvma_all
 __sbi_hfence_gvma_all:
-	/* hfence.gvma */
+	/*
+	 * rs1 = zero
+	 * rs2 = zero
+	 * HFENCE.GVMA
+	 * 0110001 00000 00000 000 00000 1110011
+	 */
 	.word 0x62000073
 	ret
 
 	/*
-	 * Instruction encoding of hfence.bvma is:
+	 * HFENCE.VVMA rs1, rs2
+	 * HFENCE.VVMA zero, rs2
+	 * HFENCE.VVMA rs1
+	 * HFENCE.VVMA
+	 *
+	 * rs1!=zero and rs2!=zero ==> HFENCE.VVMA rs1, rs2
+	 * rs1==zero and rs2!=zero ==> HFENCE.VVMA zero, rs2
+	 * rs1!=zero and rs2==zero ==> HFENCE.VVMA rs1
+	 * rs1==zero and rs2==zero ==> HFENCE.vVMA
+	 *
+	 * Instruction encoding of HFENCE.VVMA is:
 	 * 0010001 rs2(5) rs1(5) 000 00000 1110011
 	 */
 
 	.align 3
 	.global __sbi_hfence_vvma_asid_va
 __sbi_hfence_vvma_asid_va:
-	/* hfence.bvma a1, a0 */
-	.word 0x22a60073
+	/*
+	 * rs1 = a0 (VA)
+	 * rs2 = a1 (ASID)
+	 * HFENCE.VVMA a0, a1
+	 * 0010001 01011 01010 000 00000 1110011
+	 */
+	.word 0x22b50073
 	ret
 
 	.align 3
 	.global __sbi_hfence_vvma_asid
 __sbi_hfence_vvma_asid:
-	/* hfence.bvma zero, a0 */
+	/*
+	 * rs1 = zero
+	 * rs2 = a0 (ASID)
+	 * HFENCE.VVMA zero, a0
+	 * 0010001 01010 00000 000 00000 1110011
+	 */
 	.word 0x22a00073
 	ret
 
 	.align 3
 	.global __sbi_hfence_vvma_va
 __sbi_hfence_vvma_va:
-	/* hfence.bvma a0 */
+	/*
+	 * rs1 = a0 (VA)
+	 * rs2 = zero
+	 * HFENCE.VVMA zero, a0
+	 * 0010001 00000 01010 000 00000 1110011
+	 */
 	.word 0x22050073
 	ret
 
 	.align 3
 	.global __sbi_hfence_vvma_all
 __sbi_hfence_vvma_all:
-	/* hfence.bvma */
+	/*
+	 * rs1 = zero
+	 * rs2 = zero
+	 * HFENCE.VVMA
+	 * 0010001 00000 00000 000 00000 1110011
+	 */
 	.word 0x22000073
 	ret

lib/sbi/sbi_hsm.c

@@ -0,0 +1,273 @@
+/*
+ * SPDX-License-Identifier: BSD-2-Clause
+ *
+ * Copyright (c) 2020 Western Digital Corporation or its affiliates.
+ *
+ * Authors:
+ *   Atish Patra <atish.patra@wdc.com>
+ */
+
+#include <sbi/riscv_asm.h>
+#include <sbi/riscv_barrier.h>
+#include <sbi/riscv_encoding.h>
+#include <sbi/riscv_atomic.h>
+#include <sbi/sbi_bitops.h>
+#include <sbi/sbi_console.h>
+#include <sbi/sbi_error.h>
+#include <sbi/sbi_ecall_interface.h>
+#include <sbi/sbi_hart.h>
+#include <sbi/sbi_hartmask.h>
+#include <sbi/sbi_hsm.h>
+#include <sbi/sbi_init.h>
+#include <sbi/sbi_ipi.h>
+#include <sbi/sbi_platform.h>
+#include <sbi/sbi_system.h>
+#include <sbi/sbi_timer.h>
+#include <sbi/sbi_console.h>
+
+static unsigned long hart_data_offset;
+
+/** Per hart specific data to manage state transition **/
+struct sbi_hsm_data {
+	atomic_t state;
+};
+
+int sbi_hsm_hart_state_to_status(int state)
+{
+	int ret;
+
+	switch (state) {
+	case SBI_HART_STOPPED:
+		ret = SBI_HSM_HART_STATUS_STOPPED;
+		break;
+	case SBI_HART_STOPPING:
+		ret = SBI_HSM_HART_STATUS_STOP_PENDING;
+		break;
+	case SBI_HART_STARTING:
+		ret = SBI_HSM_HART_STATUS_START_PENDING;
+		break;
+	case SBI_HART_STARTED:
+		ret = SBI_HSM_HART_STATUS_STARTED;
+		break;
+	default:
+		ret = SBI_EINVAL;
+	}
+
+	return ret;
+}
+
+int sbi_hsm_hart_get_state(u32 hartid)
+{
+	struct sbi_hsm_data *hdata;
+	struct sbi_scratch *scratch;
+
+	scratch = sbi_hartid_to_scratch(hartid);
+	if (!scratch)
+		return SBI_HART_UNKNOWN;
+
+	hdata = sbi_scratch_offset_ptr(scratch, hart_data_offset);
+
+	return atomic_read(&hdata->state);
+}
+
+bool sbi_hsm_hart_started(u32 hartid)
+{
+	if (sbi_hsm_hart_get_state(hartid) == SBI_HART_STARTED)
+		return TRUE;
+	else
+		return FALSE;
+}
+
+/**
+ * Get ulong HART mask for given HART base ID
+ * @param hbase the HART base ID
+ * @param out_hmask the output ulong HART mask
+ * @return 0 on success and SBI_Exxx (< 0) on failure
+ * Note: the output HART mask will be set to zero on failure as well.
+ */
+int sbi_hsm_hart_started_mask(ulong hbase, ulong *out_hmask)
+{
+	ulong i;
+	ulong hcount = sbi_scratch_last_hartid() + 1;
+
+	*out_hmask = 0;
+	if (hcount <= hbase)
+		return SBI_EINVAL;
+	if (BITS_PER_LONG < (hcount - hbase))
+		hcount = BITS_PER_LONG;
+
+	for (i = hbase; i < hcount; i++) {
+		if (sbi_hsm_hart_get_state(i) == SBI_HART_STARTED)
+			*out_hmask |= 1UL << (i - hbase);
+	}
+
+	return 0;
+}
+
+void sbi_hsm_prepare_next_jump(struct sbi_scratch *scratch, u32 hartid)
+{
+	u32 oldstate;
+	struct sbi_hsm_data *hdata = sbi_scratch_offset_ptr(scratch,
+							    hart_data_offset);
+
+	oldstate = atomic_cmpxchg(&hdata->state, SBI_HART_STARTING,
+				  SBI_HART_STARTED);
+	if (oldstate != SBI_HART_STARTING)
+		sbi_hart_hang();
+}
+
+static void sbi_hsm_hart_wait(struct sbi_scratch *scratch, u32 hartid)
+{
+	unsigned long saved_mie;
+	const struct sbi_platform *plat = sbi_platform_ptr(scratch);
+	struct sbi_hsm_data *hdata = sbi_scratch_offset_ptr(scratch,
+							    hart_data_offset);
+	/* Save MIE CSR */
+	saved_mie = csr_read(CSR_MIE);
+
+	/* Set MSIE bit to receive IPI */
+	csr_set(CSR_MIE, MIP_MSIP);
+
+	/* Wait for hart_add call*/
+	while (atomic_read(&hdata->state) != SBI_HART_STARTING) {
+		wfi();
+	};
+
+	/* Restore MIE CSR */
+	csr_write(CSR_MIE, saved_mie);
+
+	/* Clear current HART IPI */
+	sbi_platform_ipi_clear(plat, hartid);
+}
+
+int sbi_hsm_init(struct sbi_scratch *scratch, u32 hartid, bool cold_boot)
+{
+	u32 i;
+	struct sbi_scratch *rscratch;
+	struct sbi_hsm_data *hdata;
+
+	if (cold_boot) {
+		hart_data_offset = sbi_scratch_alloc_offset(sizeof(*hdata),
+							    "HART_DATA");
+		if (!hart_data_offset)
+			return SBI_ENOMEM;
+
+		/* Initialize hart state data for every hart */
+		for (i = 0; i <= sbi_scratch_last_hartid(); i++) {
+			rscratch = sbi_hartid_to_scratch(i);
+			if (!rscratch)
+				continue;
+
+			hdata = sbi_scratch_offset_ptr(rscratch,
+						       hart_data_offset);
+			ATOMIC_INIT(&hdata->state,
+			(i == hartid) ? SBI_HART_STARTING : SBI_HART_STOPPED);
+		}
+	} else {
+		sbi_hsm_hart_wait(scratch, hartid);
+	}
+
+	return 0;
+}
+
+void __noreturn sbi_hsm_exit(struct sbi_scratch *scratch)
+{
+	u32 hstate;
+	const struct sbi_platform *plat = sbi_platform_ptr(scratch);
+	struct sbi_hsm_data *hdata = sbi_scratch_offset_ptr(scratch,
+							    hart_data_offset);
+	void (*jump_warmboot)(void) = (void (*)(void))scratch->warmboot_addr;
+
+	hstate = atomic_cmpxchg(&hdata->state, SBI_HART_STOPPING,
+				SBI_HART_STOPPED);
+	if (hstate != SBI_HART_STOPPING)
+		goto fail_exit;
+
+	if (sbi_platform_has_hart_hotplug(plat)) {
+		sbi_platform_hart_stop(plat);
+		/* It should never reach here */
+		goto fail_exit;
+	}
+
+	/**
+	 * As platform is lacking support for hotplug, directly jump to warmboot
+	 * and wait for interrupts in warmboot. We do it preemptively in order
+	 * preserve the hart states and reuse the code path for hotplug.
+	 */
+	jump_warmboot();
+
+fail_exit:
+	/* It should never reach here */
+	sbi_printf("ERR: Failed stop hart [%u]\n", current_hartid());
+	sbi_hart_hang();
+}
+
+int sbi_hsm_hart_start(struct sbi_scratch *scratch, u32 hartid,
+		       ulong saddr, ulong priv)
+{
+	int rc;
+	unsigned long init_count;
+	unsigned int hstate;
+	struct sbi_scratch *rscratch;
+	struct sbi_hsm_data *hdata;
+	const struct sbi_platform *plat = sbi_platform_ptr(scratch);
+
+	rscratch = sbi_hartid_to_scratch(hartid);
+	if (!rscratch)
+		return SBI_EINVAL;
+	hdata = sbi_scratch_offset_ptr(rscratch, hart_data_offset);
+	hstate = atomic_cmpxchg(&hdata->state, SBI_HART_STOPPED,
+				SBI_HART_STARTING);
+	if (hstate == SBI_HART_STARTED)
+		return SBI_EALREADY;
+
+	/**
+	 * if a hart is already transition to start or stop, another start call
+	 * is considered as invalid request.
+	 */
+	if (hstate != SBI_HART_STOPPED)
+		return SBI_EINVAL;
+
+	rc = sbi_hart_pmp_check_addr(scratch, saddr, PMP_X);
+	if (rc)
+		return rc;
+	//TODO: We also need to check saddr for valid physical address as well.
+
+	init_count = sbi_init_count(hartid);
+	rscratch->next_arg1 = priv;
+	rscratch->next_addr = saddr;
+
+	if (sbi_platform_has_hart_hotplug(plat) ||
+	   (sbi_platform_has_hart_secondary_boot(plat) && !init_count)) {
+		return sbi_platform_hart_start(plat, hartid,
+					       scratch->warmboot_addr);
+	} else {
+		sbi_platform_ipi_send(plat, hartid);
+	}
+
+	return 0;
+}
+
+int sbi_hsm_hart_stop(struct sbi_scratch *scratch, bool exitnow)
+{
+	int oldstate;
+	u32 hartid = current_hartid();
+	struct sbi_hsm_data *hdata = sbi_scratch_offset_ptr(scratch,
+							    hart_data_offset);
+
+	if (!sbi_hsm_hart_started(hartid))
+		return SBI_EINVAL;
+
+	oldstate = atomic_cmpxchg(&hdata->state, SBI_HART_STARTED,
+				  SBI_HART_STOPPING);
+	if (oldstate != SBI_HART_STARTED) {
+		sbi_printf("%s: ERR: The hart is in invalid state [%u]\n",
+			   __func__, oldstate);
+		return SBI_EDENIED;
+	}
+
+	if (exitnow)
+		sbi_exit(scratch);
+
+	return 0;
+}

lib/sbi/sbi_illegal_insn.c

@@ -9,57 +9,39 @@
 
 #include <sbi/riscv_asm.h>
 #include <sbi/riscv_encoding.h>
-#include <sbi/sbi_bits.h>
+#include <sbi/sbi_bitops.h>
 #include <sbi/sbi_emulate_csr.h>
 #include <sbi/sbi_error.h>
 #include <sbi/sbi_illegal_insn.h>
 #include <sbi/sbi_trap.h>
 #include <sbi/sbi_unpriv.h>
 
-typedef int (*illegal_insn_func)(ulong insn, u32 hartid, ulong mcause,
-				 struct sbi_trap_regs *regs,
-				 struct sbi_scratch *scratch);
+typedef int (*illegal_insn_func)(ulong insn, struct sbi_trap_regs *regs);
 
-static int truly_illegal_insn(ulong insn, u32 hartid, ulong mcause,
-			      struct sbi_trap_regs *regs,
-			      struct sbi_scratch *scratch)
+static int truly_illegal_insn(ulong insn, struct sbi_trap_regs *regs)
 {
 	struct sbi_trap_info trap;
 
 	trap.epc = regs->mepc;
-	trap.cause = mcause;
+	trap.cause = CAUSE_ILLEGAL_INSTRUCTION;
 	trap.tval = insn;
 	trap.tval2 = 0;
 	trap.tinst = 0;
 
-	return sbi_trap_redirect(regs, &trap, scratch);
+	return sbi_trap_redirect(regs, &trap);
 }
 
-static int system_opcode_insn(ulong insn, u32 hartid, ulong mcause,
-			      struct sbi_trap_regs *regs,
-			      struct sbi_scratch *scratch)
+static int system_opcode_insn(ulong insn, struct sbi_trap_regs *regs)
 {
 	int do_write, rs1_num = (insn >> 15) & 0x1f;
 	ulong rs1_val = GET_RS1(insn, regs);
 	int csr_num   = (u32)insn >> 20;
 	ulong csr_val, new_csr_val;
 
-	/*
-	 * WFI always traps as illegal instruction when executed from
-	 * VS/VU mode so we just forward it to HS-mode.
-	 */
-#if __riscv_xlen == 32
-	if ((regs->mstatusH & MSTATUSH_MPV) &&
-#else
-	if ((regs->mstatus & MSTATUS_MPV) &&
-#endif
-	    (insn & INSN_MASK_WFI) == INSN_MATCH_WFI)
-		return truly_illegal_insn(insn, hartid, mcause,
-					  regs, scratch);
+	/* TODO: Ensure that we got CSR read/write instruction */
 
-	if (sbi_emulate_csr_read(csr_num, hartid, regs, scratch, &csr_val))
-		return truly_illegal_insn(insn, hartid, mcause,
-					  regs, scratch);
+	if (sbi_emulate_csr_read(csr_num, regs, &csr_val))
+		return truly_illegal_insn(insn, regs);
 
 	do_write = rs1_num;
 	switch (GET_RM(insn)) {
@@ -84,12 +66,11 @@ static int system_opcode_insn(ulong insn, u32 hartid, ulong mcause,
 		new_csr_val = csr_val & ~rs1_num;
 		break;
 	default:
-		return truly_illegal_insn(insn, hartid, mcause, regs, scratch);
+		return truly_illegal_insn(insn, regs);
 	};
 
-	if (do_write && sbi_emulate_csr_write(csr_num, hartid, regs,
-					      scratch, new_csr_val))
-		return truly_illegal_insn(insn, hartid, mcause, regs, scratch);
+	if (do_write && sbi_emulate_csr_write(csr_num, regs, new_csr_val))
+		return truly_illegal_insn(insn, regs);
 
 	SET_RD(insn, regs, csr_val);
 
@@ -133,26 +114,21 @@ static illegal_insn_func illegal_insn_table[32] = {
 	truly_illegal_insn  /* 31 */
 };
 
-int sbi_illegal_insn_handler(u32 hartid, ulong mcause, ulong insn,
-			     struct sbi_trap_regs *regs,
-			     struct sbi_scratch *scratch)
+int sbi_illegal_insn_handler(ulong insn, struct sbi_trap_regs *regs)
 {
 	struct sbi_trap_info uptrap;
 
 	if (unlikely((insn & 3) != 3)) {
 		if (insn == 0) {
-			insn = sbi_get_insn(regs->mepc, scratch, &uptrap);
+			insn = sbi_get_insn(regs->mepc, &uptrap);
 			if (uptrap.cause) {
 				uptrap.epc = regs->mepc;
-				return sbi_trap_redirect(regs, &uptrap,
-							 scratch);
+				return sbi_trap_redirect(regs, &uptrap);
 			}
 		}
 		if ((insn & 3) != 3)
-			return truly_illegal_insn(insn, hartid, mcause, regs,
-						  scratch);
+			return truly_illegal_insn(insn, regs);
 	}
 
-	return illegal_insn_table[(insn & 0x7c) >> 2](insn, hartid, mcause,
-						      regs, scratch);
+	return illegal_insn_table[(insn & 0x7c) >> 2](insn, regs);
 }

lib/sbi/sbi_init.c

@@ -9,12 +9,16 @@
 
 #include <sbi/riscv_asm.h>
 #include <sbi/riscv_atomic.h>
+#include <sbi/riscv_locks.h>
 #include <sbi/sbi_console.h>
 #include <sbi/sbi_ecall.h>
 #include <sbi/sbi_hart.h>
+#include <sbi/sbi_hartmask.h>
+#include <sbi/sbi_hsm.h>
 #include <sbi/sbi_ipi.h>
 #include <sbi/sbi_platform.h>
 #include <sbi/sbi_system.h>
+#include <sbi/sbi_string.h>
 #include <sbi/sbi_timer.h>
 #include <sbi/sbi_tlb.h>
 #include <sbi/sbi_version.h>
@@ -32,7 +36,7 @@
 static void sbi_boot_prints(struct sbi_scratch *scratch, u32 hartid)
 {
 	int xlen;
-	char str[64];
+	char str[128];
 	const struct sbi_platform *plat = sbi_platform_ptr(scratch);
 
 #ifdef OPENSBI_VERSION_GIT
@@ -50,21 +54,29 @@ static void sbi_boot_prints(struct sbi_scratch *scratch, u32 hartid)
 		sbi_printf("Error %d getting MISA XLEN\n", xlen);
 		sbi_hart_hang();
 	}
-	xlen = 16 * (1 << xlen);
-	misa_string(str, sizeof(str));
 
 	/* Platform details */
-	sbi_printf("Platform Name          : %s\n", sbi_platform_name(plat));
-	sbi_printf("Platform HART Features : RV%d%s\n", xlen, str);
-	sbi_printf("Platform Max HARTs     : %d\n",
+	sbi_printf("Platform Name       : %s\n", sbi_platform_name(plat));
+	sbi_platform_get_features_str(plat, str, sizeof(str));
+	sbi_printf("Platform Features   : %s\n", str);
+	sbi_printf("Platform HART Count : %u\n",
 		   sbi_platform_hart_count(plat));
-	sbi_printf("Current Hart           : %u\n", hartid);
+
+	/* Boot HART details */
+	sbi_printf("Boot HART ID        : %u\n", hartid);
+	misa_string(xlen, str, sizeof(str));
+	sbi_printf("Boot HART ISA       : %s\n", str);
+	sbi_hart_get_features_str(scratch, str, sizeof(str));
+	sbi_printf("BOOT HART Features  : %s\n", str);
+	sbi_printf("BOOT HART PMP Count : %d\n", sbi_hart_pmp_count(scratch));
+
 	/* Firmware details */
-	sbi_printf("Firmware Base          : 0x%lx\n", scratch->fw_start);
-	sbi_printf("Firmware Size          : %d KB\n",
+	sbi_printf("Firmware Base       : 0x%lx\n", scratch->fw_start);
+	sbi_printf("Firmware Size       : %d KB\n",
 		   (u32)(scratch->fw_size / 1024));
+
 	/* Generic details */
-	sbi_printf("Runtime SBI Version    : %d.%d\n",
+	sbi_printf("Runtime SBI Version : %d.%d\n",
 		   sbi_ecall_version_major(), sbi_ecall_version_minor());
 	sbi_printf("\n");
 
@@ -72,6 +84,71 @@ static void sbi_boot_prints(struct sbi_scratch *scratch, u32 hartid)
 	sbi_hart_pmp_dump(scratch);
 }
 
+static spinlock_t coldboot_lock = SPIN_LOCK_INITIALIZER;
+static unsigned long coldboot_done = 0;
+static struct sbi_hartmask coldboot_wait_hmask = { 0 };
+
+static void wait_for_coldboot(struct sbi_scratch *scratch, u32 hartid)
+{
+	unsigned long saved_mie, cmip;
+	const struct sbi_platform *plat = sbi_platform_ptr(scratch);
+
+	/* Save MIE CSR */
+	saved_mie = csr_read(CSR_MIE);
+
+	/* Set MSIE bit to receive IPI */
+	csr_set(CSR_MIE, MIP_MSIP);
+
+	/* Acquire coldboot lock */
+	spin_lock(&coldboot_lock);
+
+	/* Mark current HART as waiting */
+	sbi_hartmask_set_hart(hartid, &coldboot_wait_hmask);
+
+	/* Wait for coldboot to finish using WFI */
+	while (!coldboot_done) {
+		spin_unlock(&coldboot_lock);
+		do {
+			wfi();
+			cmip = csr_read(CSR_MIP);
+		 } while (!(cmip & MIP_MSIP));
+		spin_lock(&coldboot_lock);
+	};
+
+	/* Unmark current HART as waiting */
+	sbi_hartmask_clear_hart(hartid, &coldboot_wait_hmask);
+
+	/* Release coldboot lock */
+	spin_unlock(&coldboot_lock);
+
+	/* Restore MIE CSR */
+	csr_write(CSR_MIE, saved_mie);
+
+	/* Clear current HART IPI */
+	sbi_platform_ipi_clear(plat, hartid);
+}
+
+static void wake_coldboot_harts(struct sbi_scratch *scratch, u32 hartid)
+{
+	const struct sbi_platform *plat = sbi_platform_ptr(scratch);
+
+	/* Acquire coldboot lock */
+	spin_lock(&coldboot_lock);
+
+	/* Mark coldboot done */
+	coldboot_done = 1;
+
+	/* Send an IPI to all HARTs waiting for coldboot */
+	for (int i = 0; i <= sbi_scratch_last_hartid(); i++) {
+		if ((i != hartid) &&
+		    sbi_hartmask_test_hart(i, &coldboot_wait_hmask))
+			sbi_platform_ipi_send(plat, i);
+	}
+
+	/* Release coldboot lock */
+	spin_unlock(&coldboot_lock);
+}
+
 static unsigned long init_count_offset;
 
 static void __noreturn init_coldboot(struct sbi_scratch *scratch, u32 hartid)
@@ -80,12 +157,21 @@ static void __noreturn init_coldboot(struct sbi_scratch *scratch, u32 hartid)
 	unsigned long *init_count;
 	const struct sbi_platform *plat = sbi_platform_ptr(scratch);
 
+	/* Note: This has to be first thing in coldboot init sequence */
+	rc = sbi_scratch_init(scratch);
+	if (rc)
+		sbi_hart_hang();
+
 	init_count_offset = sbi_scratch_alloc_offset(__SIZEOF_POINTER__,
 						     "INIT_COUNT");
 	if (!init_count_offset)
 		sbi_hart_hang();
 
-	rc = sbi_system_early_init(scratch, TRUE);
+	rc = sbi_hsm_init(scratch, hartid, TRUE);
+	if (rc)
+		sbi_hart_hang();
+
+	rc = sbi_platform_early_init(plat, TRUE);
 	if (rc)
 		sbi_hart_hang();
 
@@ -117,20 +203,19 @@ static void __noreturn init_coldboot(struct sbi_scratch *scratch, u32 hartid)
 	if (rc)
 		sbi_hart_hang();
 
-	rc = sbi_system_final_init(scratch, TRUE);
+	rc = sbi_platform_final_init(plat, TRUE);
 	if (rc)
 		sbi_hart_hang();
 
 	if (!(scratch->options & SBI_SCRATCH_NO_BOOT_PRINTS))
 		sbi_boot_prints(scratch, hartid);
 
-	sbi_hart_wake_coldboot_harts(scratch, hartid);
-
-	sbi_hart_mark_available(hartid);
+	wake_coldboot_harts(scratch, hartid);
 
 	init_count = sbi_scratch_offset_ptr(scratch, init_count_offset);
 	(*init_count)++;
 
+	sbi_hsm_prepare_next_jump(scratch, hartid);
 	sbi_hart_switch_mode(hartid, scratch->next_arg1, scratch->next_addr,
 			     scratch->next_mode, FALSE);
 }
@@ -141,12 +226,16 @@ static void __noreturn init_warmboot(struct sbi_scratch *scratch, u32 hartid)
 	unsigned long *init_count;
 	const struct sbi_platform *plat = sbi_platform_ptr(scratch);
 
-	sbi_hart_wait_for_coldboot(scratch, hartid);
+	wait_for_coldboot(scratch, hartid);
 
 	if (!init_count_offset)
 		sbi_hart_hang();
 
-	rc = sbi_system_early_init(scratch, FALSE);
+	rc = sbi_hsm_init(scratch, hartid, FALSE);
+	if (rc)
+		sbi_hart_hang();
+
+	rc = sbi_platform_early_init(plat, FALSE);
 	if (rc)
 		sbi_hart_hang();
 
@@ -170,15 +259,14 @@ static void __noreturn init_warmboot(struct sbi_scratch *scratch, u32 hartid)
 	if (rc)
 		sbi_hart_hang();
 
-	rc = sbi_system_final_init(scratch, FALSE);
+	rc = sbi_platform_final_init(plat, FALSE);
 	if (rc)
 		sbi_hart_hang();
 
-	sbi_hart_mark_available(hartid);
-
 	init_count = sbi_scratch_offset_ptr(scratch, init_count_offset);
 	(*init_count)++;
 
+	sbi_hsm_prepare_next_jump(scratch, hartid);
 	sbi_hart_switch_mode(hartid, scratch->next_arg1,
 			     scratch->next_addr,
 			     scratch->next_mode, FALSE);
@@ -201,13 +289,14 @@ static atomic_t coldboot_lottery = ATOMIC_INITIALIZER(0);
 void __noreturn sbi_init(struct sbi_scratch *scratch)
 {
 	bool coldboot			= FALSE;
-	u32 hartid			= sbi_current_hartid();
+	u32 hartid			= current_hartid();
 	const struct sbi_platform *plat = sbi_platform_ptr(scratch);
 
-	if (sbi_platform_hart_disabled(plat, hartid))
+	if ((SBI_HARTMASK_MAX_BITS <= hartid) ||
+	    sbi_platform_hart_invalid(plat, hartid))
 		sbi_hart_hang();
 
-	if (atomic_add_return(&coldboot_lottery, 1) == 1)
+	if (atomic_xchg(&coldboot_lottery, 1) == 0)
 		coldboot = TRUE;
 
 	if (coldboot)
@@ -221,11 +310,13 @@ unsigned long sbi_init_count(u32 hartid)
 	struct sbi_scratch *scratch;
 	unsigned long *init_count;
 
-	if (sbi_platform_hart_count(sbi_platform_thishart_ptr()) <= hartid ||
-	    !init_count_offset)
+	if (!init_count_offset)
+		return 0;
+
+	scratch = sbi_hartid_to_scratch(hartid);
+	if (!scratch)
 		return 0;
 
-	scratch = sbi_hart_id_to_scratch(sbi_scratch_thishart_ptr(), hartid);
 	init_count = sbi_scratch_offset_ptr(scratch, init_count_offset);
 
 	return *init_count;
@@ -242,14 +333,12 @@ unsigned long sbi_init_count(u32 hartid)
  */
 void __noreturn sbi_exit(struct sbi_scratch *scratch)
 {
-	u32 hartid			= sbi_current_hartid();
+	u32 hartid			= current_hartid();
 	const struct sbi_platform *plat = sbi_platform_ptr(scratch);
 
-	if (sbi_platform_hart_disabled(plat, hartid))
+	if (sbi_platform_hart_invalid(plat, hartid))
 		sbi_hart_hang();
 
-	sbi_hart_unmark_available(hartid);
-
 	sbi_platform_early_exit(plat);
 
 	sbi_timer_exit(scratch);
@@ -260,5 +349,5 @@ void __noreturn sbi_exit(struct sbi_scratch *scratch)
 
 	sbi_platform_final_exit(plat);
 
-	sbi_hart_hang();
+	sbi_hsm_exit(scratch);
 }

lib/sbi/sbi_ipi.c

@@ -14,6 +14,7 @@
 #include <sbi/sbi_bitops.h>
 #include <sbi/sbi_error.h>
 #include <sbi/sbi_hart.h>
+#include <sbi/sbi_hsm.h>
 #include <sbi/sbi_init.h>
 #include <sbi/sbi_ipi.h>
 #include <sbi/sbi_platform.h>
@@ -36,16 +37,14 @@ static int sbi_ipi_send(struct sbi_scratch *scratch, u32 remote_hartid,
 	const struct sbi_ipi_event_ops *ipi_ops;
 
 	if ((SBI_IPI_EVENT_MAX <= event) ||
-	    !ipi_ops_array[event] ||
-	    sbi_platform_hart_disabled(plat, remote_hartid))
+	    !ipi_ops_array[event])
 		return SBI_EINVAL;
 	ipi_ops = ipi_ops_array[event];
 
-	/*
-	 * Set IPI type on remote hart's scratch area and
-	 * trigger the interrupt
-	 */
-	remote_scratch = sbi_hart_id_to_scratch(scratch, remote_hartid);
+	remote_scratch = sbi_hartid_to_scratch(remote_hartid);
+	if (!remote_scratch)
+		return SBI_EINVAL;
+
 	ipi_data = sbi_scratch_offset_ptr(remote_scratch, ipi_data_off);
 
 	if (ipi_ops->update) {
@@ -55,6 +54,10 @@ static int sbi_ipi_send(struct sbi_scratch *scratch, u32 remote_hartid,
 			return ret;
 	}
 
+	/*
+	 * Set IPI type on remote hart's scratch area and
+	 * trigger the interrupt
+	 */
 	atomic_raw_set_bit(event, &ipi_data->ipi_type);
 	smp_wmb();
 	sbi_platform_ipi_send(plat, remote_hartid);
@@ -70,36 +73,35 @@ static int sbi_ipi_send(struct sbi_scratch *scratch, u32 remote_hartid,
  * set to all online harts if the intention is to send IPIs to all the harts.
  * If hmask is zero, no IPIs will be sent.
  */
-int sbi_ipi_send_many(struct sbi_scratch *scratch, ulong hmask, ulong hbase,
-			u32 event, void *data)
+int sbi_ipi_send_many(ulong hmask, ulong hbase, u32 event, void *data)
 {
+	int rc;
 	ulong i, m;
-	ulong mask = sbi_hart_available_mask();
-	ulong tempmask;
-	unsigned long last_bit = __fls(mask);
+	struct sbi_scratch *scratch = sbi_scratch_thishart_ptr();
 
 	if (hbase != -1UL) {
-		if (hbase > last_bit)
-			/* hart base is not available */
-			return SBI_EINVAL;
-		/**
-		 * FIXME: This check is valid only ULONG size. This is okay for
-		 * now as avaialble hart mask can support upto ULONG size only.
-		 */
-		tempmask = hmask << hbase;
-		tempmask = ~mask & tempmask;
-		if (tempmask)
-			/* at least one of the hart in hmask is not available */
-			return SBI_EINVAL;
+		rc = sbi_hsm_hart_started_mask(hbase, &m);
+		if (rc)
+			return rc;
+		m &= hmask;
 
-		mask &= (hmask << hbase);
+		/* Send IPIs */
+		for (i = hbase; m; i++, m >>= 1) {
+			if (m & 1UL)
+				sbi_ipi_send(scratch, i, event, data);
+		}
+	} else {
+		hbase = 0;
+		while (!sbi_hsm_hart_started_mask(hbase, &m)) {
+			/* Send IPIs */
+			for (i = hbase; m; i++, m >>= 1) {
+				if (m & 1UL)
+					sbi_ipi_send(scratch, i, event, data);
+			}
+			hbase += BITS_PER_LONG;
+		}
 	}
 
-	/* Send IPIs to every other hart on the set */
-	for (i = 0, m = mask; m; i++, m >>= 1)
-		if (m & 1UL)
-			sbi_ipi_send(scratch, i, event, data);
-
 	return 0;
 }
 
@@ -141,19 +143,19 @@ static struct sbi_ipi_event_ops ipi_smode_ops = {
 
 static u32 ipi_smode_event = SBI_IPI_EVENT_MAX;
 
-int sbi_ipi_send_smode(struct sbi_scratch *scratch, ulong hmask, ulong hbase)
+int sbi_ipi_send_smode(ulong hmask, ulong hbase)
 {
-	return sbi_ipi_send_many(scratch, hmask, hbase, ipi_smode_event, NULL);
+	return sbi_ipi_send_many(hmask, hbase, ipi_smode_event, NULL);
 }
 
-void sbi_ipi_clear_smode(struct sbi_scratch *scratch)
+void sbi_ipi_clear_smode(void)
 {
 	csr_clear(CSR_MIP, MIP_SSIP);
 }
 
 static void sbi_ipi_process_halt(struct sbi_scratch *scratch)
 {
-	sbi_exit(scratch);
+	sbi_hsm_hart_stop(scratch, TRUE);
 }
 
 static struct sbi_ipi_event_ops ipi_halt_ops = {
@@ -163,21 +165,22 @@ static struct sbi_ipi_event_ops ipi_halt_ops = {
 
 static u32 ipi_halt_event = SBI_IPI_EVENT_MAX;
 
-int sbi_ipi_send_halt(struct sbi_scratch *scratch, ulong hmask, ulong hbase)
+int sbi_ipi_send_halt(ulong hmask, ulong hbase)
 {
-	return sbi_ipi_send_many(scratch, hmask, hbase, ipi_halt_event, NULL);
+	return sbi_ipi_send_many(hmask, hbase, ipi_halt_event, NULL);
 }
 
-void sbi_ipi_process(struct sbi_scratch *scratch)
+void sbi_ipi_process(void)
 {
 	unsigned long ipi_type;
 	unsigned int ipi_event;
 	const struct sbi_ipi_event_ops *ipi_ops;
+	struct sbi_scratch *scratch = sbi_scratch_thishart_ptr();
 	const struct sbi_platform *plat = sbi_platform_ptr(scratch);
 	struct sbi_ipi_data *ipi_data =
 			sbi_scratch_offset_ptr(scratch, ipi_data_off);
 
-	u32 hartid = sbi_current_hartid();
+	u32 hartid = current_hartid();
 	sbi_platform_ipi_clear(plat, hartid);
 
 	ipi_type = atomic_raw_xchg_ulong(&ipi_data->ipi_type, 0);
@@ -242,7 +245,7 @@ void sbi_ipi_exit(struct sbi_scratch *scratch)
 	csr_clear(CSR_MIE, MIP_MSIP);
 
 	/* Process pending IPIs */
-	sbi_ipi_process(scratch);
+	sbi_ipi_process();
 
 	/* Platform exit */
 	sbi_platform_ipi_exit(sbi_platform_ptr(scratch));

lib/sbi/sbi_math.c

@@ -0,0 +1,23 @@
+/*
+ * SPDX-License-Identifier: BSD-2-Clause
+ *
+ * Copyright (c) 2020 Western Digital Corporation or its affiliates.
+ *
+ * Common helper functions used across OpenSBI project.
+ *
+ * Authors:
+ *   Atish Patra <atish.patra@wdc.com>
+ */
+
+unsigned long log2roundup(unsigned long x)
+{
+	unsigned long ret = 0;
+
+	while (ret < __riscv_xlen) {
+		if (x <= (1UL << ret))
+			break;
+		ret++;
+	}
+
+	return ret;
+}

lib/sbi/sbi_misaligned_ldst.c

@@ -21,10 +21,8 @@ union reg_data {
 	u64 data_u64;
 };
 
-int sbi_misaligned_load_handler(u32 hartid, ulong mcause,
-				ulong addr, ulong tval2, ulong tinst,
-				struct sbi_trap_regs *regs,
-				struct sbi_scratch *scratch)
+int sbi_misaligned_load_handler(ulong addr, ulong tval2, ulong tinst,
+				struct sbi_trap_regs *regs)
 {
 	ulong insn;
 	union reg_data val;
@@ -42,10 +40,10 @@ int sbi_misaligned_load_handler(u32 hartid, ulong mcause,
 		 * Bit[0] == 0 implies trapped instruction value is
 		 * zero or special value.
 		 */
-		insn = sbi_get_insn(regs->mepc, scratch, &uptrap);
+		insn = sbi_get_insn(regs->mepc, &uptrap);
 		if (uptrap.cause) {
 			uptrap.epc = regs->mepc;
-			return sbi_trap_redirect(regs, &uptrap, scratch);
+			return sbi_trap_redirect(regs, &uptrap);
 		}
 	}
 
@@ -72,7 +70,6 @@ int sbi_misaligned_load_handler(u32 hartid, ulong mcause,
 		shift = 8 * (sizeof(ulong) - len);
 	} else if ((insn & INSN_MASK_LHU) == INSN_MATCH_LHU) {
 		len = 2;
-#ifdef __riscv_compressed
 #if __riscv_xlen >= 64
 	} else if ((insn & INSN_MASK_C_LD) == INSN_MATCH_C_LD) {
 		len   = 8;
@@ -108,24 +105,23 @@ int sbi_misaligned_load_handler(u32 hartid, ulong mcause,
 		fp  = 1;
 		len = 4;
 #endif
-#endif
 #endif
 	} else {
 		uptrap.epc = regs->mepc;
-		uptrap.cause = mcause;
+		uptrap.cause = CAUSE_MISALIGNED_LOAD;
 		uptrap.tval = addr;
 		uptrap.tval2 = tval2;
 		uptrap.tinst = tinst;
-		return sbi_trap_redirect(regs, &uptrap, scratch);
+		return sbi_trap_redirect(regs, &uptrap);
 	}
 
 	val.data_u64 = 0;
 	for (i = 0; i < len; i++) {
 		val.data_bytes[i] = sbi_load_u8((void *)(addr + i),
-						scratch, &uptrap);
+						&uptrap);
 		if (uptrap.cause) {
 			uptrap.epc = regs->mepc;
-			return sbi_trap_redirect(regs, &uptrap, scratch);
+			return sbi_trap_redirect(regs, &uptrap);
 		}
 	}
 
@@ -143,10 +139,8 @@ int sbi_misaligned_load_handler(u32 hartid, ulong mcause,
 	return 0;
 }
 
-int sbi_misaligned_store_handler(u32 hartid, ulong mcause,
-				 ulong addr, ulong tval2, ulong tinst,
-				 struct sbi_trap_regs *regs,
-				 struct sbi_scratch *scratch)
+int sbi_misaligned_store_handler(ulong addr, ulong tval2, ulong tinst,
+				 struct sbi_trap_regs *regs)
 {
 	ulong insn;
 	union reg_data val;
@@ -164,10 +158,10 @@ int sbi_misaligned_store_handler(u32 hartid, ulong mcause,
 		 * Bit[0] == 0 implies trapped instruction value is
 		 * zero or special value.
 		 */
-		insn = sbi_get_insn(regs->mepc, scratch, &uptrap);
+		insn = sbi_get_insn(regs->mepc, &uptrap);
 		if (uptrap.cause) {
 			uptrap.epc = regs->mepc;
-			return sbi_trap_redirect(regs, &uptrap, scratch);
+			return sbi_trap_redirect(regs, &uptrap);
 		}
 	}
 
@@ -189,7 +183,6 @@ int sbi_misaligned_store_handler(u32 hartid, ulong mcause,
 #endif
 	} else if ((insn & INSN_MASK_SH) == INSN_MATCH_SH) {
 		len = 2;
-#ifdef __riscv_compressed
 #if __riscv_xlen >= 64
 	} else if ((insn & INSN_MASK_C_SD) == INSN_MATCH_C_SD) {
 		len	       = 8;
@@ -221,23 +214,22 @@ int sbi_misaligned_store_handler(u32 hartid, ulong mcause,
 		len	       = 4;
 		val.data_ulong = GET_F32_RS2C(insn, regs);
 #endif
-#endif
 #endif
 	} else {
 		uptrap.epc = regs->mepc;
-		uptrap.cause = mcause;
+		uptrap.cause = CAUSE_MISALIGNED_STORE;
 		uptrap.tval = addr;
 		uptrap.tval2 = tval2;
 		uptrap.tinst = tinst;
-		return sbi_trap_redirect(regs, &uptrap, scratch);
+		return sbi_trap_redirect(regs, &uptrap);
 	}
 
 	for (i = 0; i < len; i++) {
 		sbi_store_u8((void *)(addr + i), val.data_bytes[i],
-			     scratch, &uptrap);
+			     &uptrap);
 		if (uptrap.cause) {
 			uptrap.epc = regs->mepc;
-			return sbi_trap_redirect(regs, &uptrap, scratch);
+			return sbi_trap_redirect(regs, &uptrap);
 		}
 	}
 

lib/sbi/sbi_platform.c

@@ -0,0 +1,90 @@
+/*
+ * SPDX-License-Identifier: BSD-2-Clause
+ *
+ * Copyright (c) 2020 Western Digital Corporation or its affiliates.
+ *
+ * Authors:
+ *   Atish Patra <atish.patra@wdc.com>
+ */
+
+#include <sbi/sbi_console.h>
+#include <sbi/sbi_platform.h>
+#include <sbi/sbi_string.h>
+
+static inline char *sbi_platform_feature_id2string(unsigned long feature)
+{
+	char *fstr = NULL;
+
+	if (!feature)
+		return NULL;
+
+	switch (feature) {
+	case SBI_PLATFORM_HAS_TIMER_VALUE:
+		fstr = "timer";
+		break;
+	case SBI_PLATFORM_HAS_HART_HOTPLUG:
+		fstr = "hotplug";
+		break;
+	case SBI_PLATFORM_HAS_MFAULTS_DELEGATION:
+		fstr = "mfdeleg";
+		break;
+	case SBI_PLATFORM_HAS_HART_SECONDARY_BOOT:
+		fstr = "sec_boot";
+		break;
+	default:
+		break;
+	}
+
+	return fstr;
+}
+
+void sbi_platform_get_features_str(const struct sbi_platform *plat,
+				   char *features_str, int nfstr)
+{
+	unsigned long features, feat = 1UL;
+	char *temp;
+	int offset = 0;
+
+	if (!plat || !features_str || !nfstr)
+		return;
+	sbi_memset(features_str, 0, nfstr);
+
+	features = sbi_platform_get_features(plat);
+	if (!features)
+		goto done;
+
+	do {
+		if (features & feat) {
+			temp = sbi_platform_feature_id2string(feat);
+			if (temp) {
+				sbi_snprintf(features_str + offset, nfstr,
+					     "%s,", temp);
+				offset = offset + sbi_strlen(temp) + 1;
+			}
+		}
+		feat = feat << 1;
+	} while (feat <= SBI_PLATFORM_HAS_LAST_FEATURE);
+
+done:
+	if (offset)
+		features_str[offset - 1] = '\0';
+	else
+		sbi_strncpy(features_str, "none", nfstr);
+}
+
+u32 sbi_platform_hart_index(const struct sbi_platform *plat, u32 hartid)
+{
+	u32 i;
+
+	if (!plat)
+		return -1U;
+	if (plat->hart_index2id) {
+		for (i = 0; i < plat->hart_count; i++) {
+			if (plat->hart_index2id[i] == hartid)
+				return i;
+		}
+		return -1U;
+	}
+
+	return hartid;
+}

lib/sbi/sbi_scratch.c

@@ -9,20 +9,43 @@
 
 #include <sbi/riscv_locks.h>
 #include <sbi/sbi_hart.h>
+#include <sbi/sbi_hartmask.h>
 #include <sbi/sbi_platform.h>
 #include <sbi/sbi_scratch.h>
 #include <sbi/sbi_string.h>
 
+u32 last_hartid_having_scratch = SBI_HARTMASK_MAX_BITS;
+struct sbi_scratch *hartid_to_scratch_table[SBI_HARTMASK_MAX_BITS] = { 0 };
+
 static spinlock_t extra_lock = SPIN_LOCK_INITIALIZER;
 static unsigned long extra_offset = SBI_SCRATCH_EXTRA_SPACE_OFFSET;
 
+typedef struct sbi_scratch *(*hartid2scratch)(ulong hartid, ulong hartindex);
+
+int sbi_scratch_init(struct sbi_scratch *scratch)
+{
+	u32 i;
+	const struct sbi_platform *plat = sbi_platform_ptr(scratch);
+
+	for (i = 0; i < SBI_HARTMASK_MAX_BITS; i++) {
+		if (sbi_platform_hart_invalid(plat, i))
+			continue;
+		hartid_to_scratch_table[i] =
+			((hartid2scratch)scratch->hartid_to_scratch)(i,
+					sbi_platform_hart_index(plat, i));
+		if (hartid_to_scratch_table[i])
+			last_hartid_having_scratch = i;
+	}
+
+	return 0;
+}
+
 unsigned long sbi_scratch_alloc_offset(unsigned long size, const char *owner)
 {
 	u32 i;
 	void *ptr;
 	unsigned long ret = 0;
-	struct sbi_scratch *scratch, *rscratch;
-	const struct sbi_platform *plat;
+	struct sbi_scratch *rscratch;
 
 	/*
 	 * We have a simple brain-dead allocator which never expects
@@ -51,10 +74,10 @@ done:
 	spin_unlock(&extra_lock);
 
 	if (ret) {
-		scratch = sbi_scratch_thishart_ptr();
-		plat = sbi_platform_ptr(scratch);
-		for (i = 0; i < sbi_platform_hart_count(plat); i++) {
-			rscratch = sbi_hart_id_to_scratch(scratch, i);
+		for (i = 0; i < sbi_scratch_last_hartid(); i++) {
+			rscratch = sbi_hartid_to_scratch(i);
+			if (!rscratch)
+				continue;
 			ptr = sbi_scratch_offset_ptr(rscratch, ret);
 			sbi_memset(ptr, 0, size);
 		}

lib/sbi/sbi_system.c

@@ -8,58 +8,37 @@
  *   Nick Kossifidis <mick@ics.forth.gr>
  */
 
+#include <sbi/riscv_asm.h>
+#include <sbi/sbi_bitops.h>
 #include <sbi/sbi_hart.h>
+#include <sbi/sbi_hsm.h>
 #include <sbi/sbi_platform.h>
 #include <sbi/sbi_system.h>
 #include <sbi/sbi_ipi.h>
 #include <sbi/sbi_init.h>
 
-int sbi_system_early_init(struct sbi_scratch *scratch, bool cold_boot)
+void __noreturn sbi_system_reset(u32 platform_reset_type)
 {
-	return sbi_platform_early_init(sbi_platform_ptr(scratch), cold_boot);
-}
-
-int sbi_system_final_init(struct sbi_scratch *scratch, bool cold_boot)
-{
-	return sbi_platform_final_init(sbi_platform_ptr(scratch), cold_boot);
-}
-
-void sbi_system_early_exit(struct sbi_scratch *scratch)
-{
-	sbi_platform_early_exit(sbi_platform_ptr(scratch));
-}
-
-void sbi_system_final_exit(struct sbi_scratch *scratch)
-{
-	sbi_platform_final_exit(sbi_platform_ptr(scratch));
-}
-
-void __noreturn sbi_system_reboot(struct sbi_scratch *scratch, u32 type)
-{
-	u32 current_hartid_mask = 1UL << sbi_current_hartid();
+	ulong hbase = 0, hmask;
+	u32 cur_hartid = current_hartid();
+	struct sbi_scratch *scratch = sbi_scratch_thishart_ptr();
 
 	/* Send HALT IPI to every hart other than the current hart */
-	sbi_ipi_send_halt(scratch,
-			  sbi_hart_available_mask() & ~current_hartid_mask, 0);
+	while (!sbi_hsm_hart_started_mask(hbase, &hmask)) {
+		if (hbase <= cur_hartid)
+			hmask &= ~(1UL << (cur_hartid - hbase));
+		if (hmask)
+			sbi_ipi_send_halt(hmask, hbase);
+		hbase += BITS_PER_LONG;
+	}
 
-	/* Platform specific reooot */
-	sbi_platform_system_reboot(sbi_platform_ptr(scratch), type);
+	/* Stop current HART */
+	sbi_hsm_hart_stop(scratch, FALSE);
 
-	/* If platform specific reboot did not work then do sbi_exit() */
-	sbi_exit(scratch);
-}
-
-void __noreturn sbi_system_shutdown(struct sbi_scratch *scratch, u32 type)
-{
-	u32 current_hartid_mask = 1UL << sbi_current_hartid();
-
-	/* Send HALT IPI to every hart other than the current hart */
-	sbi_ipi_send_halt(scratch,
-			  sbi_hart_available_mask() & ~current_hartid_mask, 0);
-
-	/* Platform specific shutdown */
-	sbi_platform_system_shutdown(sbi_platform_ptr(scratch), type);
-
-	/* If platform specific shutdown did not work then do sbi_exit() */
+	/* Platform specific reset */
+	sbi_platform_system_reset(sbi_platform_ptr(scratch),
+				  platform_reset_type);
+
+	/* If platform specific reset did not work then do sbi_exit() */
 	sbi_exit(scratch);
 }

lib/sbi/sbi_timer.c

@@ -10,13 +10,16 @@
 #include <sbi/riscv_asm.h>
 #include <sbi/riscv_encoding.h>
 #include <sbi/sbi_error.h>
+#include <sbi/sbi_hart.h>
 #include <sbi/sbi_platform.h>
+#include <sbi/sbi_scratch.h>
 #include <sbi/sbi_timer.h>
 
 static unsigned long time_delta_off;
+static u64 (*get_time_val)(const struct sbi_platform *plat);
 
 #if __riscv_xlen == 32
-u64 get_ticks(void)
+static u64 get_ticks(const struct sbi_platform *plat)
 {
 	u32 lo, hi, tmp;
 	__asm__ __volatile__("1:\n"
@@ -28,7 +31,7 @@ u64 get_ticks(void)
 	return ((u64)hi << 32) | lo;
 }
 #else
-u64 get_ticks(void)
+static u64 get_ticks(const struct sbi_platform *plat)
 {
 	unsigned long n;
 
@@ -37,53 +40,52 @@ u64 get_ticks(void)
 }
 #endif
 
-u64 sbi_timer_value(struct sbi_scratch *scratch)
+u64 sbi_timer_value(void)
 {
-	const struct sbi_platform *plat = sbi_platform_ptr(scratch);
-
-	if (sbi_platform_has_timer_value(plat))
-		return sbi_platform_timer_value(plat);
-	else
-		return get_ticks();
+	return get_time_val(sbi_platform_thishart_ptr());
 }
 
-u64 sbi_timer_virt_value(struct sbi_scratch *scratch)
+u64 sbi_timer_virt_value(void)
 {
-	u64 *time_delta = sbi_scratch_offset_ptr(scratch, time_delta_off);
+	u64 *time_delta = sbi_scratch_offset_ptr(sbi_scratch_thishart_ptr(),
+						 time_delta_off);
 
-	return sbi_timer_value(scratch) + *time_delta;
+	return sbi_timer_value() + *time_delta;
 }
 
-u64 sbi_timer_get_delta(struct sbi_scratch *scratch)
+u64 sbi_timer_get_delta(void)
 {
-	u64 *time_delta = sbi_scratch_offset_ptr(scratch, time_delta_off);
+	u64 *time_delta = sbi_scratch_offset_ptr(sbi_scratch_thishart_ptr(),
+						 time_delta_off);
 
 	return *time_delta;
 }
 
-void sbi_timer_set_delta(struct sbi_scratch *scratch, ulong delta)
+void sbi_timer_set_delta(ulong delta)
 {
-	u64 *time_delta = sbi_scratch_offset_ptr(scratch, time_delta_off);
+	u64 *time_delta = sbi_scratch_offset_ptr(sbi_scratch_thishart_ptr(),
+						 time_delta_off);
 
 	*time_delta = (u64)delta;
 }
 
-void sbi_timer_set_delta_upper(struct sbi_scratch *scratch, ulong delta_upper)
+void sbi_timer_set_delta_upper(ulong delta_upper)
 {
-	u64 *time_delta = sbi_scratch_offset_ptr(scratch, time_delta_off);
+	u64 *time_delta = sbi_scratch_offset_ptr(sbi_scratch_thishart_ptr(),
+						 time_delta_off);
 
 	*time_delta &= 0xffffffffULL;
 	*time_delta |= ((u64)delta_upper << 32);
 }
 
-void sbi_timer_event_start(struct sbi_scratch *scratch, u64 next_event)
+void sbi_timer_event_start(u64 next_event)
 {
-	sbi_platform_timer_event_start(sbi_platform_ptr(scratch), next_event);
+	sbi_platform_timer_event_start(sbi_platform_thishart_ptr(), next_event);
 	csr_clear(CSR_MIP, MIP_STIP);
 	csr_set(CSR_MIE, MIP_MTIP);
 }
 
-void sbi_timer_process(struct sbi_scratch *scratch)
+void sbi_timer_process(void)
 {
 	csr_clear(CSR_MIE, MIP_MTIP);
 	csr_set(CSR_MIP, MIP_STIP);
@@ -92,6 +94,8 @@ void sbi_timer_process(struct sbi_scratch *scratch)
 int sbi_timer_init(struct sbi_scratch *scratch, bool cold_boot)
 {
 	u64 *time_delta;
+	const struct sbi_platform *plat = sbi_platform_ptr(scratch);
+	int ret;
 
 	if (cold_boot) {
 		time_delta_off = sbi_scratch_alloc_offset(sizeof(*time_delta),
@@ -106,7 +110,19 @@ int sbi_timer_init(struct sbi_scratch *scratch, bool cold_boot)
 	time_delta = sbi_scratch_offset_ptr(scratch, time_delta_off);
 	*time_delta = 0;
 
-	return sbi_platform_timer_init(sbi_platform_ptr(scratch), cold_boot);
+	ret = sbi_platform_timer_init(plat, cold_boot);
+	if (ret)
+		return ret;
+
+	if (sbi_hart_has_feature(scratch, SBI_HART_HAS_TIME))
+		get_time_val = get_ticks;
+	else if (sbi_platform_has_timer_value(plat))
+		get_time_val = sbi_platform_timer_value;
+	else
+		/* There is no method to provide timer value */
+		return SBI_ENODEV;
+
+	return 0;
 }
 
 void sbi_timer_exit(struct sbi_scratch *scratch)

lib/sbi/sbi_tlb.c

@@ -36,16 +36,23 @@ static void sbi_tlb_hfence_vvma(struct sbi_tlb_info *tinfo)
 {
 	unsigned long start = tinfo->start;
 	unsigned long size  = tinfo->size;
-	unsigned long i;
+	unsigned long vmid  = tinfo->vmid;
+	unsigned long i, hgatp;
+
+	hgatp = csr_swap(CSR_HGATP,
+			 (vmid << HGATP_VMID_SHIFT) & HGATP_VMID_MASK);
 
 	if ((start == 0 && size == 0) || (size == SBI_TLB_FLUSH_ALL)) {
 		__sbi_hfence_vvma_all();
-		return;
+		goto done;
 	}
 
 	for (i = 0; i < size; i += PAGE_SIZE) {
 		__sbi_hfence_vvma_va(start+i);
 	}
+
+done:
+	csr_write(CSR_HGATP, hgatp);
 }
 
 static void sbi_tlb_hfence_gvma(struct sbi_tlb_info *tinfo)
@@ -88,28 +95,35 @@ static void sbi_tlb_hfence_vvma_asid(struct sbi_tlb_info *tinfo)
 	unsigned long start = tinfo->start;
 	unsigned long size  = tinfo->size;
 	unsigned long asid  = tinfo->asid;
-	unsigned long i;
+	unsigned long vmid  = tinfo->vmid;
+	unsigned long i, hgatp;
+
+	hgatp = csr_swap(CSR_HGATP,
+			 (vmid << HGATP_VMID_SHIFT) & HGATP_VMID_MASK);
 
 	if (start == 0 && size == 0) {
 		__sbi_hfence_vvma_all();
-		return;
+		goto done;
 	}
 
 	if (size == SBI_TLB_FLUSH_ALL) {
 		__sbi_hfence_vvma_asid(asid);
-		return;
+		goto done;
 	}
 
 	for (i = 0; i < size; i += PAGE_SIZE) {
-		__sbi_hfence_vvma_asid_va(asid, start + i);
+		__sbi_hfence_vvma_asid_va(start + i, asid);
 	}
+
+done:
+	csr_write(CSR_HGATP, hgatp);
 }
 
 static void sbi_tlb_hfence_gvma_vmid(struct sbi_tlb_info *tinfo)
 {
 	unsigned long start = tinfo->start;
 	unsigned long size  = tinfo->size;
-	unsigned long vmid  = tinfo->asid;
+	unsigned long vmid  = tinfo->vmid;
 	unsigned long i;
 
 	if (start == 0 && size == 0) {
@@ -123,7 +137,7 @@ static void sbi_tlb_hfence_gvma_vmid(struct sbi_tlb_info *tinfo)
 	}
 
 	for (i = 0; i < size; i += PAGE_SIZE) {
-		__sbi_hfence_gvma_vmid_gpa(vmid, start+i);
+		__sbi_hfence_gvma_vmid_gpa(start + i, vmid);
 	}
 }
 
@@ -187,20 +201,19 @@ static void sbi_tlb_local_flush(struct sbi_tlb_info *tinfo)
 	return;
 }
 
-static void sbi_tlb_entry_process(struct sbi_scratch *scratch,
-				  struct sbi_tlb_info *tinfo)
+static void sbi_tlb_entry_process(struct sbi_tlb_info *tinfo)
 {
-	u32 i;
-	u64 m;
+	u32 rhartid;
 	struct sbi_scratch *rscratch = NULL;
 	unsigned long *rtlb_sync = NULL;
 
 	sbi_tlb_local_flush(tinfo);
-	for (i = 0, m = tinfo->shart_mask; m; i++, m >>= 1) {
-		if (!(m & 1UL))
+
+	sbi_hartmask_for_each_hart(rhartid, &tinfo->smask) {
+		rscratch = sbi_hartid_to_scratch(rhartid);
+		if (!rscratch)
 			continue;
 
-		rscratch = sbi_hart_id_to_scratch(scratch, i);
 		rtlb_sync = sbi_scratch_offset_ptr(rscratch, tlb_sync_off);
 		while (atomic_raw_xchg_ulong(rtlb_sync, 1)) ;
 	}
@@ -214,7 +227,7 @@ static void sbi_tlb_process_count(struct sbi_scratch *scratch, int count)
 			sbi_scratch_offset_ptr(scratch, tlb_fifo_off);
 
 	while (!sbi_fifo_dequeue(tlb_fifo, &tinfo)) {
-		sbi_tlb_entry_process(scratch, &tinfo);
+		sbi_tlb_entry_process(&tinfo);
 		deq_count++;
 		if (deq_count > count)
 			break;
@@ -229,7 +242,7 @@ static void sbi_tlb_process(struct sbi_scratch *scratch)
 			sbi_scratch_offset_ptr(scratch, tlb_fifo_off);
 
 	while (!sbi_fifo_dequeue(tlb_fifo, &tinfo))
-		sbi_tlb_entry_process(scratch, &tinfo);
+		sbi_tlb_entry_process(&tinfo);
 }
 
 static void sbi_tlb_sync(struct sbi_scratch *scratch)
@@ -263,11 +276,11 @@ static inline int __sbi_tlb_range_check(struct sbi_tlb_info *curr,
 	if (next->start <= curr->start && next_end > curr_end) {
 		curr->start = next->start;
 		curr->size  = next->size;
-		curr->shart_mask = curr->shart_mask | next->shart_mask;
-		ret	    = SBI_FIFO_UPDATED;
+		sbi_hartmask_or(&curr->smask, &curr->smask, &next->smask);
+		ret = SBI_FIFO_UPDATED;
 	} else if (next->start >= curr->start && next_end <= curr_end) {
-		curr->shart_mask = curr->shart_mask | next->shart_mask;
-		ret		 = SBI_FIFO_SKIP;
+		sbi_hartmask_or(&curr->smask, &curr->smask, &next->smask);
+		ret = SBI_FIFO_SKIP;
 	}
 
 	return ret;
@@ -322,7 +335,7 @@ static int sbi_tlb_update(struct sbi_scratch *scratch,
 	int ret;
 	struct sbi_fifo *tlb_fifo_r;
 	struct sbi_tlb_info *tinfo = data;
-	u32 curr_hartid = sbi_current_hartid();
+	u32 curr_hartid = current_hartid();
 
 	/*
 	 * If address range to flush is too big then simply
@@ -360,7 +373,7 @@ static int sbi_tlb_update(struct sbi_scratch *scratch,
 		 * this properly.
 		 */
 		sbi_tlb_process_count(scratch, 1);
-		sbi_dprintf(remote_scratch, "hart%d: hart%d tlb fifo full\n",
+		sbi_dprintf("hart%d: hart%d tlb fifo full\n",
 			    curr_hartid, remote_hartid);
 	}
 
@@ -376,10 +389,9 @@ static struct sbi_ipi_event_ops tlb_ops = {
 
 static u32 tlb_event = SBI_IPI_EVENT_MAX;
 
-int sbi_tlb_request(struct sbi_scratch *scratch, ulong hmask,
-		    ulong hbase, struct sbi_tlb_info *tinfo)
+int sbi_tlb_request(ulong hmask, ulong hbase, struct sbi_tlb_info *tinfo)
 {
-	return sbi_ipi_send_many(scratch, hmask, hbase, tlb_event, tinfo);
+	return sbi_ipi_send_many(hmask, hbase, tlb_event, tinfo);
 }
 
 int sbi_tlb_init(struct sbi_scratch *scratch, bool cold_boot)
@@ -392,11 +404,11 @@ int sbi_tlb_init(struct sbi_scratch *scratch, bool cold_boot)
 
 	if (cold_boot) {
 		tlb_sync_off = sbi_scratch_alloc_offset(sizeof(*tlb_sync),
-							    "IPI_TLB_SYNC");
+							"IPI_TLB_SYNC");
 		if (!tlb_sync_off)
 			return SBI_ENOMEM;
 		tlb_fifo_off = sbi_scratch_alloc_offset(sizeof(*tlb_q),
-							    "IPI_TLB_FIFO");
+							"IPI_TLB_FIFO");
 		if (!tlb_fifo_off) {
 			sbi_scratch_free_offset(tlb_sync_off);
 			return SBI_ENOMEM;

lib/sbi/sbi_trap.c

@@ -19,10 +19,12 @@
 #include <sbi/sbi_timer.h>
 #include <sbi/sbi_trap.h>
 
-static void __noreturn sbi_trap_error(const char *msg, int rc, u32 hartid,
+static void __noreturn sbi_trap_error(const char *msg, int rc,
 				      ulong mcause, ulong mtval, ulong mtval2,
 				      ulong mtinst, struct sbi_trap_regs *regs)
 {
+	u32 hartid = current_hartid();
+
 	sbi_printf("%s: hart%d: %s (error %d)\n", __func__, hartid, msg, rc);
 	sbi_printf("%s: hart%d: mcause=0x%" PRILX " mtval=0x%" PRILX "\n",
 		   __func__, hartid, mcause, mtval);
@@ -74,13 +76,11 @@ static void __noreturn sbi_trap_error(const char *msg, int rc, u32 hartid,
  *
  * @param regs pointer to register state
  * @param trap pointer to trap details
- * @param scratch pointer to sbi_scratch of current HART
  *
  * @return 0 on success and negative error code on failure
  */
 int sbi_trap_redirect(struct sbi_trap_regs *regs,
-		      struct sbi_trap_info *trap,
-		      struct sbi_scratch *scratch)
+		      struct sbi_trap_info *trap)
 {
 	ulong hstatus, vsstatus, prev_mode;
 #if __riscv_xlen == 32
@@ -120,12 +120,10 @@ int sbi_trap_redirect(struct sbi_trap_regs *regs,
 
 	/* Update HSTATUS for VS/VU-mode to HS-mode transition */
 	if (misa_extension('H') && prev_virt && !next_virt) {
-		/* Update HSTATUS SP2P, SP2V, and SPV bits */
+		/* Update HSTATUS SPVP and SPV bits */
 		hstatus = csr_read(CSR_HSTATUS);
-		hstatus &= ~HSTATUS_SP2P;
-		hstatus |= (regs->mstatus & MSTATUS_SPP) ? HSTATUS_SP2P : 0;
-		hstatus &= ~HSTATUS_SP2V;
-		hstatus |= (hstatus & HSTATUS_SPV) ? HSTATUS_SP2V : 0;
+		hstatus &= ~HSTATUS_SPVP;
+		hstatus |= (regs->mstatus & MSTATUS_SPP) ? HSTATUS_SPVP : 0;
 		hstatus &= ~HSTATUS_SPV;
 		hstatus |= (prev_virt) ? HSTATUS_SPV : 0;
 		csr_write(CSR_HSTATUS, hstatus);
@@ -178,7 +176,7 @@ int sbi_trap_redirect(struct sbi_trap_regs *regs,
 		regs->mstatus &= ~MSTATUS_MPP;
 		regs->mstatus |= (PRV_S << MSTATUS_MPP_SHIFT);
 
-		/* Set SPP for S-mode*/
+		/* Set SPP for S-mode */
 		regs->mstatus &= ~MSTATUS_SPP;
 		if (prev_mode == PRV_S)
 			regs->mstatus |= (1UL << MSTATUS_SPP_SHIFT);
@@ -210,17 +208,14 @@ int sbi_trap_redirect(struct sbi_trap_regs *regs,
  * 7. Interrupts are disabled in MSTATUS CSR
  *
  * @param regs pointer to register state
- * @param scratch pointer to sbi_scratch of current HART
  */
-void sbi_trap_handler(struct sbi_trap_regs *regs,
-		      struct sbi_scratch *scratch)
+void sbi_trap_handler(struct sbi_trap_regs *regs)
 {
 	int rc = SBI_ENOTSUPP;
 	const char *msg = "trap handler failed";
-	u32 hartid = sbi_current_hartid();
 	ulong mcause = csr_read(CSR_MCAUSE);
 	ulong mtval = csr_read(CSR_MTVAL), mtval2 = 0, mtinst = 0;
-	struct sbi_trap_info trap, *uptrap;
+	struct sbi_trap_info trap;
 
 	if (misa_extension('H')) {
 		mtval2 = csr_read(CSR_MTVAL2);
@@ -231,10 +226,10 @@ void sbi_trap_handler(struct sbi_trap_regs *regs,
 		mcause &= ~(1UL << (__riscv_xlen - 1));
 		switch (mcause) {
 		case IRQ_M_TIMER:
-			sbi_timer_process(scratch);
+			sbi_timer_process();
 			break;
 		case IRQ_M_SOFT:
-			sbi_ipi_process(scratch);
+			sbi_ipi_process();
 			break;
 		default:
 			msg = "unhandled external interrupt";
@@ -245,50 +240,22 @@ void sbi_trap_handler(struct sbi_trap_regs *regs,
 
 	switch (mcause) {
 	case CAUSE_ILLEGAL_INSTRUCTION:
-		rc  = sbi_illegal_insn_handler(hartid, mcause, mtval,
-					       regs, scratch);
+		rc  = sbi_illegal_insn_handler(mtval, regs);
 		msg = "illegal instruction handler failed";
 		break;
 	case CAUSE_MISALIGNED_LOAD:
-		rc = sbi_misaligned_load_handler(hartid, mcause, mtval,
-						 mtval2, mtinst, regs,
-						 scratch);
+		rc = sbi_misaligned_load_handler(mtval, mtval2, mtinst, regs);
 		msg = "misaligned load handler failed";
 		break;
 	case CAUSE_MISALIGNED_STORE:
-		rc  = sbi_misaligned_store_handler(hartid, mcause, mtval,
-						   mtval2, mtinst, regs,
-						   scratch);
+		rc  = sbi_misaligned_store_handler(mtval, mtval2, mtinst, regs);
 		msg = "misaligned store handler failed";
 		break;
 	case CAUSE_SUPERVISOR_ECALL:
 	case CAUSE_HYPERVISOR_ECALL:
-		rc  = sbi_ecall_handler(hartid, mcause, regs, scratch);
+		rc  = sbi_ecall_handler(regs);
 		msg = "ecall handler failed";
 		break;
-	case CAUSE_LOAD_ACCESS:
-	case CAUSE_STORE_ACCESS:
-	case CAUSE_LOAD_PAGE_FAULT:
-	case CAUSE_STORE_PAGE_FAULT:
-		uptrap = sbi_hart_get_trap_info(scratch);
-		if ((regs->mstatus & MSTATUS_MPRV) && uptrap) {
-			rc = 0;
-			uptrap->epc = regs->mepc;
-			regs->mepc += 4;
-			uptrap->cause = mcause;
-			uptrap->tval = mtval;
-			uptrap->tval2 = mtval2;
-			uptrap->tinst = mtinst;
-		} else {
-			trap.epc = regs->mepc;
-			trap.cause = mcause;
-			trap.tval = mtval;
-			trap.tval2 = mtval2;
-			trap.tinst = mtinst;
-			rc = sbi_trap_redirect(regs, &trap, scratch);
-		}
-		msg = "page/access fault handler failed";
-		break;
 	default:
 		/* If the trap came from S or U mode, redirect it there */
 		trap.epc = regs->mepc;
@@ -296,13 +263,11 @@ void sbi_trap_handler(struct sbi_trap_regs *regs,
 		trap.tval = mtval;
 		trap.tval2 = mtval2;
 		trap.tinst = mtinst;
-		rc = sbi_trap_redirect(regs, &trap, scratch);
+		rc = sbi_trap_redirect(regs, &trap);
 		break;
 	};
 
 trap_error:
-	if (rc) {
-		sbi_trap_error(msg, rc, hartid, mcause, mtval,
-			       mtval2, mtinst, regs);
-	}
+	if (rc)
+		sbi_trap_error(msg, rc, mcause, mtval, mtval2, mtinst, regs);
 }

lib/sbi/sbi_unpriv.c

@@ -8,60 +8,66 @@
  */
 
 #include <sbi/riscv_encoding.h>
-#include <sbi/sbi_bits.h>
+#include <sbi/sbi_bitops.h>
 #include <sbi/sbi_hart.h>
 #include <sbi/sbi_scratch.h>
 #include <sbi/sbi_trap.h>
 #include <sbi/sbi_unpriv.h>
 
+/**
+ * a3 must a pointer to the sbi_trap_info and a4 is used as a temporary
+ * register in the trap handler. Make sure that compiler doesn't use a3 & a4.
+ */
 #define DEFINE_UNPRIVILEGED_LOAD_FUNCTION(type, insn)                         \
 	type sbi_load_##type(const type *addr,                                \
-			     struct sbi_scratch *scratch,                     \
 			     struct sbi_trap_info *trap)                      \
 	{                                                                     \
-		register ulong __mstatus asm("a2");                           \
-		type val = 0;                                                 \
-		trap->epc = 0;                                                \
+		register ulong tinfo asm("a3");                               \
+		register ulong mstatus = 0;                                   \
+		register ulong mtvec = sbi_hart_expected_trap_addr();         \
+		type ret = 0;                                                 \
 		trap->cause = 0;                                              \
-		trap->tval = 0;                                               \
-		trap->tval2 = 0;                                              \
-		trap->tinst = 0;                                              \
-		sbi_hart_set_trap_info(scratch, trap);                        \
 		asm volatile(                                                 \
-			"csrrs %0, " STR(CSR_MSTATUS) ", %3\n"                \
+			"add %[tinfo], %[taddr], zero\n"                      \
+			"csrrw %[mtvec], " STR(CSR_MTVEC) ", %[mtvec]\n"      \
+			"csrrs %[mstatus], " STR(CSR_MSTATUS) ", %[mprv]\n"   \
 			".option push\n"                                      \
 			".option norvc\n"                                     \
-			#insn " %1, %2\n"                                     \
+			#insn " %[ret], %[addr]\n"                            \
 			".option pop\n"                                       \
-			"csrw " STR(CSR_MSTATUS) ", %0"                       \
-		    : "+&r"(__mstatus), "=&r"(val)                            \
-		    : "m"(*addr), "r"(MSTATUS_MPRV));                         \
-		sbi_hart_set_trap_info(scratch, NULL);                        \
-		return val;                                                   \
+			"csrw " STR(CSR_MSTATUS) ", %[mstatus]\n"             \
+			"csrw " STR(CSR_MTVEC) ", %[mtvec]"                   \
+		    : [mstatus] "+&r"(mstatus), [mtvec] "+&r"(mtvec),         \
+		      [tinfo] "+&r"(tinfo), [ret] "=&r"(ret)                  \
+		    : [addr] "m"(*addr), [mprv] "r"(MSTATUS_MPRV),            \
+		      [taddr] "r"((ulong)trap)                                \
+		    : "a4", "memory");                                        \
+		return ret;                                                   \
 	}
 
 #define DEFINE_UNPRIVILEGED_STORE_FUNCTION(type, insn)                        \
 	void sbi_store_##type(type *addr, type val,                           \
-			      struct sbi_scratch *scratch,                    \
 			      struct sbi_trap_info *trap)                     \
 	{                                                                     \
-		register ulong __mstatus asm("a3");                           \
-		trap->epc = 0;                                                \
+		register ulong tinfo asm("a3") = (ulong)trap;                 \
+		register ulong mstatus = 0;                                   \
+		register ulong mtvec = sbi_hart_expected_trap_addr();         \
 		trap->cause = 0;                                              \
-		trap->tval = 0;                                               \
-		trap->tval2 = 0;                                              \
-		trap->tinst = 0;                                              \
-		sbi_hart_set_trap_info(scratch, trap);                        \
 		asm volatile(                                                 \
-			"csrrs %0, " STR(CSR_MSTATUS) ", %3\n"                \
+			"add %[tinfo], %[taddr], zero\n"                      \
+			"csrrw %[mtvec], " STR(CSR_MTVEC) ", %[mtvec]\n"      \
+			"csrrs %[mstatus], " STR(CSR_MSTATUS) ", %[mprv]\n"   \
 			".option push\n"                                      \
 			".option norvc\n"                                     \
-			#insn " %1, %2\n"                                     \
+			#insn " %[val], %[addr]\n"                            \
 			".option pop\n"                                       \
-			"csrw " STR(CSR_MSTATUS) ", %0"                       \
-			: "+&r"(__mstatus)                                    \
-			: "r"(val), "m"(*addr), "r"(MSTATUS_MPRV));           \
-		sbi_hart_set_trap_info(scratch, NULL);                        \
+			"csrw " STR(CSR_MSTATUS) ", %[mstatus]\n"             \
+			"csrw " STR(CSR_MTVEC) ", %[mtvec]"                   \
+		    : [mstatus] "+&r"(mstatus), [mtvec] "+&r"(mtvec),         \
+		      [tinfo] "+&r"(tinfo)                                    \
+		    : [addr] "m"(*addr), [mprv] "r"(MSTATUS_MPRV),            \
+		      [val] "r"(val), [taddr] "r"((ulong)trap)                \
+		    : "a4", "memory");                                        \
 	}
 
 DEFINE_UNPRIVILEGED_LOAD_FUNCTION(u8, lbu)
@@ -82,14 +88,13 @@ DEFINE_UNPRIVILEGED_LOAD_FUNCTION(u32, lw)
 DEFINE_UNPRIVILEGED_LOAD_FUNCTION(ulong, lw)
 
 u64 sbi_load_u64(const u64 *addr,
-		 struct sbi_scratch *scratch,
 		 struct sbi_trap_info *trap)
 {
-	u64 ret = sbi_load_u32((u32 *)addr, scratch, trap);
+	u64 ret = sbi_load_u32((u32 *)addr, trap);
 
 	if (trap->cause)
 		return 0;
-	ret |= ((u64)sbi_load_u32((u32 *)addr + 1, scratch, trap) << 32);
+	ret |= ((u64)sbi_load_u32((u32 *)addr + 1, trap) << 32);
 	if (trap->cause)
 		return 0;
 
@@ -97,68 +102,47 @@ u64 sbi_load_u64(const u64 *addr,
 }
 
 void sbi_store_u64(u64 *addr, u64 val,
-		   struct sbi_scratch *scratch,
 		   struct sbi_trap_info *trap)
 {
-	sbi_store_u32((u32 *)addr, val, scratch, trap);
+	sbi_store_u32((u32 *)addr, val, trap);
 	if (trap->cause)
 		return;
 
-	sbi_store_u32((u32 *)addr + 1, val >> 32, scratch, trap);
+	sbi_store_u32((u32 *)addr + 1, val >> 32, trap);
 	if (trap->cause)
 		return;
 }
 #endif
 
-ulong sbi_get_insn(ulong mepc, struct sbi_scratch *scratch,
-		   struct sbi_trap_info *trap)
+ulong sbi_get_insn(ulong mepc, struct sbi_trap_info *trap)
 {
-	ulong __mstatus = 0, val = 0;
-#ifdef __riscv_compressed
-	ulong rvc_mask = 3, tmp;
-#endif
+	register ulong tinfo asm("a3");
+	register ulong ttmp asm("a4");
+	register ulong mstatus = 0;
+	register ulong mtvec = sbi_hart_expected_trap_addr();
+	ulong insn = 0;
 
-	trap->epc = 0;
 	trap->cause = 0;
-	trap->tval = 0;
-	trap->tval2 = 0;
-	trap->tinst = 0;
-	sbi_hart_set_trap_info(scratch, trap);
 
-#ifndef __riscv_compressed
-	asm("csrrs %[mstatus], " STR(CSR_MSTATUS) ", %[mprv]\n"
-	    ".option push\n"
-	    ".option norvc\n"
-#if __riscv_xlen == 64
-	    STR(LWU) " %[insn], (%[addr])\n"
-#else
-	    STR(LW) " %[insn], (%[addr])\n"
-#endif
-	    ".option pop\n"
-	    "csrw " STR(CSR_MSTATUS) ", %[mstatus]"
-	    : [mstatus] "+&r"(__mstatus), [insn] "=&r"(val)
-	    : [mprv] "r"(MSTATUS_MPRV | MSTATUS_MXR), [addr] "r"(mepc));
-#else
-	asm("csrrs %[mstatus], " STR(CSR_MSTATUS) ", %[mprv]\n"
-	    ".option push\n"
-	    ".option norvc\n"
+	asm volatile(
+	    "add %[tinfo], %[taddr], zero\n"
+	    "csrrw %[mtvec], " STR(CSR_MTVEC) ", %[mtvec]\n"
+	    "csrrs %[mstatus], " STR(CSR_MSTATUS) ", %[mprv]\n"
 	    "lhu %[insn], (%[addr])\n"
-	    ".option pop\n"
-	    "and %[tmp], %[insn], %[rvc_mask]\n"
-	    "bne %[tmp], %[rvc_mask], 2f\n"
-	    ".option push\n"
-	    ".option norvc\n"
-	    "lhu %[tmp], 2(%[addr])\n"
-	    ".option pop\n"
-	    "sll %[tmp], %[tmp], 16\n"
-	    "add %[insn], %[insn], %[tmp]\n"
-	    "2: csrw " STR(CSR_MSTATUS) ", %[mstatus]"
-	    : [mstatus] "+&r"(__mstatus), [insn] "=&r"(val), [tmp] "=&r"(tmp)
-	    : [mprv] "r"(MSTATUS_MPRV | MSTATUS_MXR), [addr] "r"(mepc),
-	      [rvc_mask] "r"(rvc_mask));
-#endif
-
-	sbi_hart_set_trap_info(scratch, NULL);
+	    "andi %[ttmp], %[insn], 3\n"
+	    "addi %[ttmp], %[ttmp], -3\n"
+	    "bne %[ttmp], zero, 2f\n"
+	    "lhu %[ttmp], 2(%[addr])\n"
+	    "sll %[ttmp], %[ttmp], 16\n"
+	    "add %[insn], %[insn], %[ttmp]\n"
+	    "2: csrw " STR(CSR_MSTATUS) ", %[mstatus]\n"
+	    "csrw " STR(CSR_MTVEC) ", %[mtvec]"
+	    : [mstatus] "+&r"(mstatus), [mtvec] "+&r"(mtvec),
+	      [tinfo] "+&r"(tinfo), [ttmp] "+&r"(ttmp),
+	      [insn] "=&r"(insn)
+	    : [mprv] "r"(MSTATUS_MPRV | MSTATUS_MXR),
+	      [taddr] "r"((ulong)trap), [addr] "r"(mepc)
+	    : "memory");
 
 	switch (trap->cause) {
 	case CAUSE_LOAD_ACCESS:
@@ -177,5 +161,5 @@ ulong sbi_get_insn(ulong mepc, struct sbi_scratch *scratch,
 		break;
 	};
 
-	return val;
+	return insn;
 }

lib/utils/fdt/fdt_fixup.c

@@ -0,0 +1,255 @@
+// SPDX-License-Identifier: BSD-2-Clause
+/*
+ * fdt_fixup.c - Flat Device Tree parsing helper routines
+ * Implement helper routines to parse FDT nodes on top of
+ * libfdt for OpenSBI usage
+ *
+ * Copyright (C) 2020 Bin Meng <bmeng.cn@gmail.com>
+ */
+
+#include <libfdt.h>
+#include <sbi/sbi_console.h>
+#include <sbi/sbi_math.h>
+#include <sbi/sbi_hart.h>
+#include <sbi/sbi_platform.h>
+#include <sbi/sbi_scratch.h>
+#include <sbi/sbi_string.h>
+#include <sbi_utils/fdt/fdt_fixup.h>
+#include <sbi_utils/fdt/fdt_helper.h>
+
+void fdt_cpu_fixup(void *fdt)
+{
+	struct sbi_scratch *scratch = sbi_scratch_thishart_ptr();
+	const struct sbi_platform *plat = sbi_platform_ptr(scratch);
+	int err, cpu_offset, cpus_offset;
+	u32 hartid;
+
+	err = fdt_open_into(fdt, fdt, fdt_totalsize(fdt) + 32);
+	if (err < 0)
+		return;
+
+	cpus_offset = fdt_path_offset(fdt, "/cpus");
+	if (cpus_offset < 0)
+		return;
+
+	fdt_for_each_subnode(cpu_offset, fdt, cpus_offset) {
+		err = fdt_parse_hart_id(fdt, cpu_offset, &hartid);
+		if (err)
+			continue;
+
+		if (sbi_platform_hart_invalid(plat, hartid))
+			fdt_setprop_string(fdt, cpu_offset, "status",
+					   "disabled");
+	}
+}
+
+void fdt_plic_fixup(void *fdt, const char *compat)
+{
+	u32 *cells;
+	int i, cells_count;
+	int plic_off;
+
+	plic_off = fdt_node_offset_by_compatible(fdt, 0, compat);
+	if (plic_off < 0)
+		return;
+
+	cells = (u32 *)fdt_getprop(fdt, plic_off,
+				   "interrupts-extended", &cells_count);
+	if (!cells)
+		return;
+
+	cells_count = cells_count / sizeof(u32);
+	if (!cells_count)
+		return;
+
+	for (i = 0; i < (cells_count / 2); i++) {
+		if (fdt32_to_cpu(cells[2 * i + 1]) == IRQ_M_EXT)
+			cells[2 * i + 1] = cpu_to_fdt32(0xffffffff);
+	}
+}
+
+static int fdt_resv_memory_update_node(void *fdt, unsigned long addr,
+				       unsigned long size, int index,
+				       int parent, bool no_map)
+{
+	int na = fdt_address_cells(fdt, 0);
+	int ns = fdt_size_cells(fdt, 0);
+	fdt32_t addr_high, addr_low;
+	fdt32_t size_high, size_low;
+	int subnode, err;
+	fdt32_t reg[4];
+	fdt32_t *val;
+	char name[32];
+
+	addr_high = (u64)addr >> 32;
+	addr_low = addr;
+	size_high = (u64)size >> 32;
+	size_low = size;
+
+	if (na > 1 && addr_high)
+		sbi_snprintf(name, sizeof(name),
+			     "mmode_pmp%d@%x,%x", index,
+			     addr_high, addr_low);
+	else
+		sbi_snprintf(name, sizeof(name),
+			     "mmode_pmp%d@%x", index,
+			     addr_low);
+
+	subnode = fdt_add_subnode(fdt, parent, name);
+	if (subnode < 0)
+		return subnode;
+
+	if (no_map) {
+		/*
+		 * Tell operating system not to create a virtual
+		 * mapping of the region as part of its standard
+		 * mapping of system memory.
+		 */
+		err = fdt_setprop_empty(fdt, subnode, "no-map");
+		if (err < 0)
+			return err;
+	}
+
+	/* encode the <reg> property value */
+	val = reg;
+	if (na > 1)
+		*val++ = cpu_to_fdt32(addr_high);
+	*val++ = cpu_to_fdt32(addr_low);
+	if (ns > 1)
+		*val++ = cpu_to_fdt32(size_high);
+	*val++ = cpu_to_fdt32(size_low);
+
+	err = fdt_setprop(fdt, subnode, "reg", reg,
+			  (na + ns) * sizeof(fdt32_t));
+	if (err < 0)
+		return err;
+
+	return 0;
+}
+
+/**
+ * We use PMP to protect OpenSBI firmware to safe-guard it from buggy S-mode
+ * software, see pmp_init() in lib/sbi/sbi_hart.c. The protected memory region
+ * information needs to be conveyed to S-mode software (e.g.: operating system)
+ * via some well-known method.
+ *
+ * With device tree, this can be done by inserting a child node of the reserved
+ * memory node which is used to specify one or more regions of reserved memory.
+ *
+ * For the reserved memory node bindings, see Linux kernel documentation at
+ * Documentation/devicetree/bindings/reserved-memory/reserved-memory.txt
+ *
+ * Some additional memory spaces may be protected by platform codes via PMP as
+ * well, and corresponding child nodes will be inserted.
+ */
+int fdt_reserved_memory_fixup(void *fdt)
+{
+	struct sbi_scratch *scratch = sbi_scratch_thishart_ptr();
+	unsigned long prot, addr, size;
+	int parent, i, j;
+	int err;
+	int na = fdt_address_cells(fdt, 0);
+	int ns = fdt_size_cells(fdt, 0);
+
+	/* expand the device tree to accommodate new node */
+	err  = fdt_open_into(fdt, fdt, fdt_totalsize(fdt) + 256);
+	if (err < 0)
+		return err;
+
+	/* try to locate the reserved memory node */
+	parent = fdt_path_offset(fdt, "/reserved-memory");
+	if (parent < 0) {
+		/* if such node does not exist, create one */
+		parent = fdt_add_subnode(fdt, 0, "reserved-memory");
+		if (parent < 0)
+			return parent;
+
+		/*
+		 * reserved-memory node has 3 required properties:
+		 * - #address-cells: the same value as the root node
+		 * - #size-cells: the same value as the root node
+		 * - ranges: should be empty
+		 */
+
+		err = fdt_setprop_empty(fdt, parent, "ranges");
+		if (err < 0)
+			return err;
+
+		err = fdt_setprop_u32(fdt, parent, "#size-cells", ns);
+		if (err < 0)
+			return err;
+
+		err = fdt_setprop_u32(fdt, parent, "#address-cells", na);
+		if (err < 0)
+			return err;
+	}
+
+	/*
+	 * We assume the given device tree does not contain any memory region
+	 * child node protected by PMP. Normally PMP programming happens at
+	 * M-mode firmware. The memory space used by OpenSBI is protected.
+	 * Some additional memory spaces may be protected by platform codes.
+	 *
+	 * With above assumption, we create child nodes directly.
+	 */
+
+	if (!sbi_hart_has_feature(scratch, SBI_HART_HAS_PMP)) {
+		/*
+		 * Update the DT with firmware start & size even if PMP is not
+		 * supported. This makes sure that supervisor OS is always
+		 * aware of OpenSBI resident memory area.
+		 */
+		addr = scratch->fw_start & ~(scratch->fw_size - 1UL);
+		size = (1UL << log2roundup(scratch->fw_size));
+		return fdt_resv_memory_update_node(fdt, addr, size,
+						   0, parent, true);
+	}
+
+	for (i = 0, j = 0; i < sbi_hart_pmp_count(scratch); i++) {
+		err = sbi_hart_pmp_get(scratch, i, &prot, &addr, &size);
+		if (err)
+			continue;
+		if (!(prot & PMP_A))
+			continue;
+		if (prot & (PMP_R | PMP_W | PMP_X))
+			continue;
+
+		fdt_resv_memory_update_node(fdt, addr, size, j, parent, false);
+		j++;
+	}
+
+	return 0;
+}
+
+int fdt_reserved_memory_nomap_fixup(void *fdt)
+{
+	int parent, subnode;
+	int err;
+
+	/* Locate the reserved memory node */
+	parent = fdt_path_offset(fdt, "/reserved-memory");
+	if (parent < 0)
+		return parent;
+
+	fdt_for_each_subnode(subnode, fdt, parent) {
+		/*
+		 * Tell operating system not to create a virtual
+		 * mapping of the region as part of its standard
+		 * mapping of system memory.
+		 */
+		err = fdt_setprop_empty(fdt, subnode, "no-map");
+		if (err < 0)
+			return err;
+	}
+
+	return 0;
+}
+
+void fdt_fixups(void *fdt)
+{
+	fdt_plic_fixup(fdt, "riscv,plic0");
+
+	fdt_reserved_memory_fixup(fdt);
+}
+
+

lib/utils/fdt/fdt_helper.c

@@ -0,0 +1,419 @@
+// SPDX-License-Identifier: BSD-2-Clause
+/*
+ * fdt_helper.c - Flat Device Tree manipulation helper routines
+ * Implement helper routines on top of libfdt for OpenSBI usage
+ *
+ * Copyright (C) 2020 Bin Meng <bmeng.cn@gmail.com>
+ */
+
+#include <libfdt.h>
+#include <sbi/riscv_asm.h>
+#include <sbi/sbi_console.h>
+#include <sbi/sbi_hartmask.h>
+#include <sbi/sbi_platform.h>
+#include <sbi/sbi_scratch.h>
+#include <sbi_utils/fdt/fdt_helper.h>
+#include <sbi_utils/irqchip/plic.h>
+#include <sbi_utils/sys/clint.h>
+
+#define DEFAULT_UART_FREQ		0
+#define DEFAULT_UART_BAUD		115200
+#define DEFAULT_UART_REG_SHIFT		0
+#define DEFAULT_UART_REG_IO_WIDTH	1
+
+#define DEFAULT_SIFIVE_UART_FREQ		0
+#define DEFAULT_SIFIVE_UART_BAUD		115200
+#define DEFAULT_SIFIVE_UART_REG_SHIFT		0
+#define DEFAULT_SIFIVE_UART_REG_IO_WIDTH	4
+
+#define DEFAULT_SHAKTI_UART_FREQ		50000000
+#define DEFAULT_SHAKTI_UART_BAUD		115200
+
+const struct fdt_match *fdt_match_node(void *fdt, int nodeoff,
+				       const struct fdt_match *match_table)
+{
+	int ret;
+
+	if (!fdt || nodeoff < 0 || !match_table)
+		return NULL;
+
+	while (match_table->compatible) {
+		ret = fdt_node_check_compatible(fdt, nodeoff,
+						match_table->compatible);
+		if (!ret)
+			return match_table;
+		match_table++;
+	}
+
+	return NULL;
+}
+
+int fdt_find_match(void *fdt, int startoff,
+		   const struct fdt_match *match_table,
+		   const struct fdt_match **out_match)
+{
+	int nodeoff;
+
+	if (!fdt || !match_table)
+		return SBI_ENODEV;
+
+	while (match_table->compatible) {
+		nodeoff = fdt_node_offset_by_compatible(fdt, startoff,
+						match_table->compatible);
+		if (nodeoff >= 0) {
+			if (out_match)
+				*out_match = match_table;
+			return nodeoff;
+		}
+		match_table++;
+	}
+
+	return SBI_ENODEV;
+}
+
+int fdt_get_node_addr_size(void *fdt, int node, unsigned long *addr,
+			   unsigned long *size)
+{
+	int parent, len, i;
+	int cell_addr, cell_size;
+	const fdt32_t *prop_addr, *prop_size;
+	uint64_t temp = 0;
+
+	parent = fdt_parent_offset(fdt, node);
+	if (parent < 0)
+		return parent;
+	cell_addr = fdt_address_cells(fdt, parent);
+	if (cell_addr < 1)
+		return SBI_ENODEV;
+
+	cell_size = fdt_size_cells(fdt, parent);
+	if (cell_size < 0)
+		return SBI_ENODEV;
+
+	prop_addr = fdt_getprop(fdt, node, "reg", &len);
+	if (!prop_addr)
+		return SBI_ENODEV;
+	prop_size = prop_addr + cell_addr;
+
+	if (addr) {
+		for (i = 0; i < cell_addr; i++)
+			temp = (temp << 32) | fdt32_to_cpu(*prop_addr++);
+		*addr = temp;
+	}
+	temp = 0;
+
+	if (size) {
+		for (i = 0; i < cell_size; i++)
+			temp = (temp << 32) | fdt32_to_cpu(*prop_size++);
+		*size = temp;
+	}
+
+	return 0;
+}
+
+int fdt_parse_hart_id(void *fdt, int cpu_offset, u32 *hartid)
+{
+	int len;
+	const void *prop;
+	const fdt32_t *val;
+
+	if (!fdt || cpu_offset < 0)
+		return SBI_EINVAL;
+
+	prop = fdt_getprop(fdt, cpu_offset, "device_type", &len);
+	if (!prop || !len)
+		return SBI_EINVAL;
+	if (sbi_strcmp(prop, "cpu"))
+		return SBI_EINVAL;
+
+	val = fdt_getprop(fdt, cpu_offset, "reg", &len);
+	if (!val || len < sizeof(fdt32_t))
+		return SBI_EINVAL;
+
+	if (len > sizeof(fdt32_t))
+		val++;
+
+	if (hartid)
+		*hartid = fdt32_to_cpu(*val);
+
+	return 0;
+}
+
+int fdt_parse_max_hart_id(void *fdt, u32 *max_hartid)
+{
+	u32 hartid;
+	int err, cpu_offset, cpus_offset;
+
+	if (!fdt)
+		return SBI_EINVAL;
+	if (!max_hartid)
+		return 0;
+
+	*max_hartid = 0;
+
+	cpus_offset = fdt_path_offset(fdt, "/cpus");
+	if (cpus_offset < 0)
+		return cpus_offset;
+
+	fdt_for_each_subnode(cpu_offset, fdt, cpus_offset) {
+		err = fdt_parse_hart_id(fdt, cpu_offset, &hartid);
+		if (err)
+			continue;
+
+		if (hartid > *max_hartid)
+			*max_hartid = hartid;
+	}
+
+	return 0;
+}
+
+int fdt_parse_shakti_uart_node(void *fdt, int nodeoffset,
+			       struct platform_uart_data *uart)
+{
+	int len, rc;
+	const fdt32_t *val;
+	unsigned long reg_addr, reg_size;
+
+	if (nodeoffset < 0 || !uart || !fdt)
+		return SBI_ENODEV;
+
+	rc = fdt_get_node_addr_size(fdt, nodeoffset, &reg_addr, &reg_size);
+	if (rc < 0 || !reg_addr || !reg_size)
+		return SBI_ENODEV;
+	uart->addr = reg_addr;
+
+	/**
+	 * UART address is mandaotry. clock-frequency and current-speed
+	 * may not be present. Don't return error.
+	 */
+	val = (fdt32_t *)fdt_getprop(fdt, nodeoffset, "clock-frequency", &len);
+	if (len > 0 && val)
+		uart->freq = fdt32_to_cpu(*val);
+	else
+		uart->freq = DEFAULT_SHAKTI_UART_FREQ;
+
+	val = (fdt32_t *)fdt_getprop(fdt, nodeoffset, "current-speed", &len);
+	if (len > 0 && val)
+		uart->baud = fdt32_to_cpu(*val);
+	else
+		uart->baud = DEFAULT_SHAKTI_UART_BAUD;
+
+	return 0;
+}
+
+int fdt_parse_sifive_uart_node(void *fdt, int nodeoffset,
+			       struct platform_uart_data *uart)
+{
+	int len, rc;
+	const fdt32_t *val;
+	unsigned long reg_addr, reg_size;
+
+	if (nodeoffset < 0 || !uart || !fdt)
+		return SBI_ENODEV;
+
+	rc = fdt_get_node_addr_size(fdt, nodeoffset, &reg_addr, &reg_size);
+	if (rc < 0 || !reg_addr || !reg_size)
+		return SBI_ENODEV;
+	uart->addr = reg_addr;
+
+	/**
+	 * UART address is mandaotry. clock-frequency and current-speed
+	 * may not be present. Don't return error.
+	 */
+	val = (fdt32_t *)fdt_getprop(fdt, nodeoffset, "clock-frequency", &len);
+	if (len > 0 && val)
+		uart->freq = fdt32_to_cpu(*val);
+	else
+		uart->freq = DEFAULT_SIFIVE_UART_FREQ;
+
+	val = (fdt32_t *)fdt_getprop(fdt, nodeoffset, "current-speed", &len);
+	if (len > 0 && val)
+		uart->baud = fdt32_to_cpu(*val);
+	else
+		uart->baud = DEFAULT_SIFIVE_UART_BAUD;
+
+	/* For SiFive UART, the reg-shift and reg-io-width are fixed .*/
+	uart->reg_shift = DEFAULT_SIFIVE_UART_REG_SHIFT;
+	uart->reg_io_width = DEFAULT_SIFIVE_UART_REG_IO_WIDTH;
+
+	return 0;
+}
+
+int fdt_parse_uart8250_node(void *fdt, int nodeoffset,
+			    struct platform_uart_data *uart)
+{
+	int len, rc;
+	const fdt32_t *val;
+	unsigned long reg_addr, reg_size;
+
+	if (nodeoffset < 0 || !uart || !fdt)
+		return SBI_ENODEV;
+
+	rc = fdt_get_node_addr_size(fdt, nodeoffset, &reg_addr, &reg_size);
+	if (rc < 0 || !reg_addr || !reg_size)
+		return SBI_ENODEV;
+	uart->addr = reg_addr;
+
+	/**
+	 * UART address is mandaotry. clock-frequency and current-speed
+	 * may not be present. Don't return error.
+	 */
+	val = (fdt32_t *)fdt_getprop(fdt, nodeoffset, "clock-frequency", &len);
+	if (len > 0 && val)
+		uart->freq = fdt32_to_cpu(*val);
+	else
+		uart->freq = DEFAULT_UART_FREQ;
+
+	val = (fdt32_t *)fdt_getprop(fdt, nodeoffset, "current-speed", &len);
+	if (len > 0 && val)
+		uart->baud = fdt32_to_cpu(*val);
+	else
+		uart->baud = DEFAULT_UART_BAUD;
+
+	val = (fdt32_t *)fdt_getprop(fdt, nodeoffset, "reg-shift", &len);
+	if (len > 0 && val)
+		uart->reg_shift = fdt32_to_cpu(*val);
+	else
+		uart->reg_shift = DEFAULT_UART_REG_SHIFT;
+
+	val = (fdt32_t *)fdt_getprop(fdt, nodeoffset, "reg-io-width", &len);
+	if (len > 0 && val)
+		uart->reg_io_width = fdt32_to_cpu(*val);
+	else
+		uart->reg_io_width = DEFAULT_UART_REG_IO_WIDTH;
+
+	return 0;
+}
+
+int fdt_parse_uart8250(void *fdt, struct platform_uart_data *uart,
+		   const char *compatible)
+{
+	int nodeoffset;
+
+	if (!compatible || !uart || !fdt)
+		return SBI_ENODEV;
+
+	nodeoffset = fdt_node_offset_by_compatible(fdt, -1, compatible);
+	if (nodeoffset < 0)
+		return nodeoffset;
+
+	return fdt_parse_uart8250_node(fdt, nodeoffset, uart);
+}
+
+int fdt_parse_plic_node(void *fdt, int nodeoffset, struct plic_data *plic)
+{
+	int len, rc;
+	const fdt32_t *val;
+	unsigned long reg_addr, reg_size;
+
+	if (nodeoffset < 0 || !plic || !fdt)
+		return SBI_ENODEV;
+
+	rc = fdt_get_node_addr_size(fdt, nodeoffset, &reg_addr, &reg_size);
+	if (rc < 0 || !reg_addr || !reg_size)
+		return SBI_ENODEV;
+	plic->addr = reg_addr;
+
+	val = fdt_getprop(fdt, nodeoffset, "riscv,ndev", &len);
+	if (len > 0)
+		plic->num_src = fdt32_to_cpu(*val);
+
+	return 0;
+}
+
+int fdt_parse_plic(void *fdt, struct plic_data *plic, const char *compat)
+{
+	int nodeoffset;
+
+	if (!compat || !plic || !fdt)
+		return SBI_ENODEV;
+
+	nodeoffset = fdt_node_offset_by_compatible(fdt, -1, compat);
+	if (nodeoffset < 0)
+		return nodeoffset;
+
+	return fdt_parse_plic_node(fdt, nodeoffset, plic);
+}
+
+int fdt_parse_clint_node(void *fdt, int nodeoffset, bool for_timer,
+			 struct clint_data *clint)
+{
+	const fdt32_t *val;
+	unsigned long reg_addr, reg_size;
+	int i, rc, count, cpu_offset, cpu_intc_offset;
+	u32 phandle, hwirq, hartid, first_hartid, last_hartid;
+	u32 match_hwirq = (for_timer) ? IRQ_M_TIMER : IRQ_M_SOFT;
+
+	if (nodeoffset < 0 || !clint || !fdt)
+		return SBI_ENODEV;
+
+	rc = fdt_get_node_addr_size(fdt, nodeoffset, &reg_addr, &reg_size);
+	if (rc < 0 || !reg_addr || !reg_size)
+		return SBI_ENODEV;
+	clint->addr = reg_addr;
+
+	val = fdt_getprop(fdt, nodeoffset, "interrupts-extended", &count);
+	if (!val || count < sizeof(fdt32_t))
+		return SBI_EINVAL;
+	count = count / sizeof(fdt32_t);
+
+	first_hartid = -1U;
+	last_hartid = 0;
+	clint->hart_count = 0;
+	for (i = 0; i < count; i += 2) {
+		phandle = fdt32_to_cpu(val[i]);
+		hwirq = fdt32_to_cpu(val[i + 1]);
+
+		cpu_intc_offset = fdt_node_offset_by_phandle(fdt, phandle);
+		if (cpu_intc_offset < 0)
+			continue;
+
+		cpu_offset = fdt_parent_offset(fdt, cpu_intc_offset);
+		if (cpu_intc_offset < 0)
+			continue;
+
+		rc = fdt_parse_hart_id(fdt, cpu_offset, &hartid);
+		if (rc)
+			continue;
+
+		if (SBI_HARTMASK_MAX_BITS <= hartid)
+			continue;
+
+		if (match_hwirq == hwirq) {
+			if (hartid < first_hartid)
+				first_hartid = hartid;
+			if (hartid > last_hartid)
+				last_hartid = hartid;
+			clint->hart_count++;
+		}
+	}
+
+	if ((last_hartid < first_hartid) || first_hartid == -1U)
+		return SBI_ENODEV;
+
+	clint->first_hartid = first_hartid;
+	count = last_hartid - first_hartid + 1;
+	if (clint->hart_count < count)
+		clint->hart_count = count;
+
+	/* TODO: We should figure-out CLINT has_64bit_mmio from DT node */
+	clint->has_64bit_mmio = TRUE;
+
+	return 0;
+}
+
+int fdt_parse_compat_addr(void *fdt, unsigned long *addr,
+			  const char *compatible)
+{
+	int nodeoffset, rc;
+
+	nodeoffset = fdt_node_offset_by_compatible(fdt, -1, compatible);
+	if (nodeoffset < 0)
+		return nodeoffset;
+
+	rc = fdt_get_node_addr_size(fdt, nodeoffset, addr, NULL);
+	if (rc < 0 || !addr)
+		return SBI_ENODEV;
+
+	return 0;
+}

lib/utils/fdt/objects.mk

@@ -0,0 +1,8 @@
+#
+# SPDX-License-Identifier: BSD-2-Clause
+#
+# Copyright (C) 2020 Bin Meng <bmeng.cn@gmail.com>
+#
+
+libsbiutils-objs-y += fdt/fdt_helper.o
+libsbiutils-objs-y += fdt/fdt_fixup.o

lib/utils/ipi/fdt_ipi.c

@@ -0,0 +1,101 @@
+/*
+ * SPDX-License-Identifier: BSD-2-Clause
+ *
+ * Copyright (c) 2020 Western Digital Corporation or its affiliates.
+ *
+ * Authors:
+ *   Anup Patel <anup.patel@wdc.com>
+ */
+
+#include <sbi/sbi_scratch.h>
+#include <sbi_utils/fdt/fdt_helper.h>
+#include <sbi_utils/ipi/fdt_ipi.h>
+
+extern struct fdt_ipi fdt_ipi_clint;
+
+static struct fdt_ipi *ipi_drivers[] = {
+	&fdt_ipi_clint
+};
+
+static void dummy_send(u32 target_hart)
+{
+}
+
+static void dummy_clear(u32 target_hart)
+{
+}
+
+static struct fdt_ipi dummy = {
+	.match_table = NULL,
+	.cold_init = NULL,
+	.warm_init = NULL,
+	.exit = NULL,
+	.send = dummy_send,
+	.clear = dummy_clear
+};
+
+static struct fdt_ipi *current_driver = &dummy;
+
+void fdt_ipi_send(u32 target_hart)
+{
+	current_driver->send(target_hart);
+}
+
+void fdt_ipi_clear(u32 target_hart)
+{
+	current_driver->clear(target_hart);
+}
+
+void fdt_ipi_exit(void)
+{
+	if (current_driver->exit)
+		current_driver->exit();
+}
+
+static int fdt_ipi_warm_init(void)
+{
+	if (current_driver->warm_init)
+		return current_driver->warm_init();
+	return 0;
+}
+
+static int fdt_ipi_cold_init(void)
+{
+	int pos, noff, rc;
+	struct fdt_ipi *drv;
+	const struct fdt_match *match;
+	void *fdt = sbi_scratch_thishart_arg1_ptr();
+
+	for (pos = 0; pos < array_size(ipi_drivers); pos++) {
+		drv = ipi_drivers[pos];
+
+		noff = -1;
+		while ((noff = fdt_find_match(fdt, noff,
+					drv->match_table, &match)) >= 0) {
+			if (drv->cold_init) {
+				rc = drv->cold_init(fdt, noff, match);
+				if (rc)
+					return rc;
+			}
+			current_driver = drv;
+		}
+
+		if (current_driver != &dummy)
+			break;
+	}
+
+	return 0;
+}
+
+int fdt_ipi_init(bool cold_boot)
+{
+	int rc;
+
+	if (cold_boot) {
+		rc = fdt_ipi_cold_init();
+		if (rc)
+			return rc;
+	}
+
+	return fdt_ipi_warm_init();
+}

lib/utils/ipi/fdt_ipi_clint.c

@@ -0,0 +1,49 @@
+/*
+ * SPDX-License-Identifier: BSD-2-Clause
+ *
+ * Copyright (c) 2020 Western Digital Corporation or its affiliates.
+ *
+ * Authors:
+ *   Anup Patel <anup.patel@wdc.com>
+ */
+
+#include <sbi/sbi_error.h>
+#include <sbi_utils/fdt/fdt_helper.h>
+#include <sbi_utils/ipi/fdt_ipi.h>
+#include <sbi_utils/sys/clint.h>
+
+#define CLINT_IPI_MAX_NR			16
+
+static unsigned long clint_ipi_count = 0;
+static struct clint_data clint_ipi[CLINT_IPI_MAX_NR];
+
+static int ipi_clint_cold_init(void *fdt, int nodeoff,
+			       const struct fdt_match *match)
+{
+	int rc;
+	struct clint_data *ci;
+
+	if (CLINT_IPI_MAX_NR <= clint_ipi_count)
+		return SBI_ENOSPC;
+	ci = &clint_ipi[clint_ipi_count++];
+
+	rc = fdt_parse_clint_node(fdt, nodeoff, FALSE, ci);
+	if (rc)
+		return rc;
+
+	return clint_cold_ipi_init(ci);
+}
+
+static const struct fdt_match ipi_clint_match[] = {
+	{ .compatible = "riscv,clint0" },
+	{ },
+};
+
+struct fdt_ipi fdt_ipi_clint = {
+	.match_table = ipi_clint_match,
+	.cold_init = ipi_clint_cold_init,
+	.warm_init = clint_warm_ipi_init,
+	.exit = NULL,
+	.send = clint_ipi_send,
+	.clear = clint_ipi_clear,
+};

lib/utils/ipi/objects.mk

@@ -0,0 +1,11 @@
+#
+# SPDX-License-Identifier: BSD-2-Clause
+#
+# Copyright (c) 2020 Western Digital Corporation or its affiliates.
+#
+# Authors:
+#   Anup Patel <anup.patel@wdc.com>
+#
+
+libsbiutils-objs-y += ipi/fdt_ipi.o
+libsbiutils-objs-y += ipi/fdt_ipi_clint.o

lib/utils/irqchip/fdt_irqchip.c

@@ -0,0 +1,74 @@
+/*
+ * SPDX-License-Identifier: BSD-2-Clause
+ *
+ * Copyright (c) 2020 Western Digital Corporation or its affiliates.
+ *
+ * Authors:
+ *   Anup Patel <anup.patel@wdc.com>
+ */
+
+#include <sbi/sbi_scratch.h>
+#include <sbi_utils/fdt/fdt_helper.h>
+#include <sbi_utils/irqchip/fdt_irqchip.h>
+
+extern struct fdt_irqchip fdt_irqchip_plic;
+
+static struct fdt_irqchip *irqchip_drivers[] = {
+	&fdt_irqchip_plic
+};
+
+static struct fdt_irqchip *current_driver = NULL;
+
+void fdt_irqchip_exit(void)
+{
+	if (current_driver && current_driver->exit)
+		current_driver->exit();
+}
+
+static int fdt_irqchip_warm_init(void)
+{
+	if (current_driver && current_driver->warm_init)
+		return current_driver->warm_init();
+	return 0;
+}
+
+static int fdt_irqchip_cold_init(void)
+{
+	int pos, noff, rc;
+	struct fdt_irqchip *drv;
+	const struct fdt_match *match;
+	void *fdt = sbi_scratch_thishart_arg1_ptr();
+
+	for (pos = 0; pos < array_size(irqchip_drivers); pos++) {
+		drv = irqchip_drivers[pos];
+
+		noff = -1;
+		while ((noff = fdt_find_match(fdt, noff,
+					drv->match_table, &match)) >= 0) {
+			if (drv->cold_init) {
+				rc = drv->cold_init(fdt, noff, match);
+				if (rc)
+					return rc;
+			}
+			current_driver = drv;
+		}
+
+		if (current_driver)
+			break;
+	}
+
+	return 0;
+}
+
+int fdt_irqchip_init(bool cold_boot)
+{
+	int rc;
+
+	if (cold_boot) {
+		rc = fdt_irqchip_cold_init();
+		if (rc)
+			return rc;
+	}
+
+	return fdt_irqchip_warm_init();
+}

lib/utils/irqchip/fdt_irqchip_plic.c

@@ -0,0 +1,120 @@
+/*
+ * SPDX-License-Identifier: BSD-2-Clause
+ *
+ * Copyright (c) 2020 Western Digital Corporation or its affiliates.
+ *
+ * Authors:
+ *   Anup Patel <anup.patel@wdc.com>
+ */
+
+#include <libfdt.h>
+#include <sbi/riscv_asm.h>
+#include <sbi/sbi_error.h>
+#include <sbi/sbi_hartmask.h>
+#include <sbi_utils/fdt/fdt_helper.h>
+#include <sbi_utils/irqchip/fdt_irqchip.h>
+#include <sbi_utils/irqchip/plic.h>
+
+#define PLIC_MAX_NR			16
+
+static unsigned long plic_count = 0;
+static struct plic_data plic[PLIC_MAX_NR];
+
+static struct plic_data *plic_hartid2data[SBI_HARTMASK_MAX_BITS];
+static int plic_hartid2context[SBI_HARTMASK_MAX_BITS][2];
+
+static int irqchip_plic_warm_init(void)
+{
+	u32 hartid = current_hartid();
+
+	return plic_warm_irqchip_init(plic_hartid2data[hartid],
+				      plic_hartid2context[hartid][0],
+				      plic_hartid2context[hartid][1]);
+}
+
+static int irqchip_plic_update_hartid_table(void *fdt, int nodeoff,
+					    struct plic_data *pd)
+{
+	const fdt32_t *val;
+	u32 phandle, hwirq, hartid;
+	int i, err, count, cpu_offset, cpu_intc_offset;
+
+	val = fdt_getprop(fdt, nodeoff, "interrupts-extended", &count);
+	if (!val || count < sizeof(fdt32_t))
+		return SBI_EINVAL;
+	count = count / sizeof(fdt32_t);
+
+	for (i = 0; i < count; i += 2) {
+		phandle = fdt32_to_cpu(val[i]);
+		hwirq = fdt32_to_cpu(val[i + 1]);
+
+		cpu_intc_offset = fdt_node_offset_by_phandle(fdt, phandle);
+		if (cpu_intc_offset < 0)
+			continue;
+
+		cpu_offset = fdt_parent_offset(fdt, cpu_intc_offset);
+		if (cpu_intc_offset < 0)
+			continue;
+
+		err = fdt_parse_hart_id(fdt, cpu_offset, &hartid);
+		if (err)
+			continue;
+
+		if (SBI_HARTMASK_MAX_BITS <= hartid)
+			continue;
+
+		plic_hartid2data[hartid] = pd;
+		switch (hwirq) {
+		case IRQ_M_EXT:
+			plic_hartid2context[hartid][0] = i / 2;
+			break;
+		case IRQ_S_EXT:
+			plic_hartid2context[hartid][1] = i / 2;
+			break;
+		}
+	}
+
+	return 0;
+}
+
+static int irqchip_plic_cold_init(void *fdt, int nodeoff,
+				  const struct fdt_match *match)
+{
+	int i, rc;
+	struct plic_data *pd;
+
+	if (PLIC_MAX_NR <= plic_count)
+		return SBI_ENOSPC;
+	pd = &plic[plic_count++];
+
+	rc = fdt_parse_plic_node(fdt, nodeoff, pd);
+	if (rc)
+		return rc;
+
+	rc = plic_cold_irqchip_init(pd);
+	if (rc)
+		return rc;
+
+	if (plic_count == 1) {
+		for (i = 0; i < SBI_HARTMASK_MAX_BITS; i++) {
+			plic_hartid2data[i] = NULL;
+			plic_hartid2context[i][0] = -1;
+			plic_hartid2context[i][1] = -1;
+		}
+	}
+
+	return irqchip_plic_update_hartid_table(fdt, nodeoff, pd);
+}
+
+static const struct fdt_match irqchip_plic_match[] = {
+	{ .compatible = "riscv,plic0" },
+	{ .compatible = "sifive,plic-1.0.0" },
+	{ },
+};
+
+struct fdt_irqchip fdt_irqchip_plic = {
+	.match_table = irqchip_plic_match,
+	.cold_init = irqchip_plic_cold_init,
+	.warm_init = irqchip_plic_warm_init,
+	.exit = NULL,
+};

lib/utils/irqchip/objects.mk

@@ -7,4 +7,6 @@
 #   Anup Patel <anup.patel@wdc.com>
 #
 
+libsbiutils-objs-y += irqchip/fdt_irqchip.o
+libsbiutils-objs-y += irqchip/fdt_irqchip_plic.o
 libsbiutils-objs-y += irqchip/plic.o

lib/utils/irqchip/plic.c

@@ -10,10 +10,9 @@
 #include <sbi/riscv_io.h>
 #include <sbi/riscv_encoding.h>
 #include <sbi/sbi_console.h>
+#include <sbi/sbi_error.h>
 #include <sbi/sbi_string.h>
 #include <sbi_utils/irqchip/plic.h>
-#include <libfdt.h>
-#include <fdt.h>
 
 #define PLIC_PRIORITY_BASE 0x0
 #define PLIC_PENDING_BASE 0x1000
@@ -22,97 +21,80 @@
 #define PLIC_CONTEXT_BASE 0x200000
 #define PLIC_CONTEXT_STRIDE 0x1000
 
-static u32 plic_hart_count;
-static u32 plic_num_sources;
-static volatile void *plic_base;
-
-static void plic_set_priority(u32 source, u32 val)
+static void plic_set_priority(struct plic_data *plic, u32 source, u32 val)
 {
-	volatile void *plic_priority =
-		plic_base + PLIC_PRIORITY_BASE + 4 * source;
+	volatile void *plic_priority = (void *)plic->addr +
+			PLIC_PRIORITY_BASE + 4 * source;
 	writel(val, plic_priority);
 }
 
-void plic_set_thresh(u32 cntxid, u32 val)
+void plic_set_thresh(struct plic_data *plic, u32 cntxid, u32 val)
 {
-	volatile void *plic_thresh =
-		plic_base + PLIC_CONTEXT_BASE + PLIC_CONTEXT_STRIDE * cntxid;
+	volatile void *plic_thresh;
+
+	if (!plic)
+		return;
+
+	plic_thresh = (void *)plic->addr +
+		      PLIC_CONTEXT_BASE + PLIC_CONTEXT_STRIDE * cntxid;
 	writel(val, plic_thresh);
 }
 
-void plic_set_ie(u32 cntxid, u32 word_index, u32 val)
+void plic_set_ie(struct plic_data *plic, u32 cntxid, u32 word_index, u32 val)
 {
-	volatile void *plic_ie =
-		plic_base + PLIC_ENABLE_BASE + PLIC_ENABLE_STRIDE * cntxid;
+	volatile void *plic_ie;
+
+	if (!plic)
+		return;
+
+	plic_ie = (void *)plic->addr +
+		   PLIC_ENABLE_BASE + PLIC_ENABLE_STRIDE * cntxid;
 	writel(val, plic_ie + word_index * 4);
 }
 
-void plic_fdt_fixup(void *fdt, const char *compat)
+int plic_warm_irqchip_init(struct plic_data *plic,
+			   int m_cntx_id, int s_cntx_id)
 {
-	u32 *cells;
-	int i, cells_count;
-	int plic_off;
+	size_t i, ie_words;
 
-	plic_off = fdt_node_offset_by_compatible(fdt, 0, compat);
-	if (plic_off < 0)
-		return;
+	if (!plic)
+		return SBI_EINVAL;
 
-	cells = (u32 *)fdt_getprop(fdt, plic_off,
-				   "interrupts-extended", &cells_count);
-	if (!cells)
-		return;
-
-	cells_count = cells_count / sizeof(u32);
-	if (!cells_count)
-		return;
-
-	for (i = 0; i < (cells_count / 2); i++) {
-		if (fdt32_to_cpu(cells[2 * i + 1]) == IRQ_M_EXT)
-			cells[2 * i + 1] = cpu_to_fdt32(0xffffffff);
-	}
-}
-
-int plic_warm_irqchip_init(u32 target_hart, int m_cntx_id, int s_cntx_id)
-{
-	size_t i, ie_words = plic_num_sources / 32 + 1;
-
-	if (plic_hart_count <= target_hart)
-		return -1;
+	ie_words = plic->num_src / 32 + 1;
 
 	/* By default, disable all IRQs for M-mode of target HART */
 	if (m_cntx_id > -1) {
 		for (i = 0; i < ie_words; i++)
-			plic_set_ie(m_cntx_id, i, 0);
+			plic_set_ie(plic, m_cntx_id, i, 0);
 	}
 
 	/* By default, disable all IRQs for S-mode of target HART */
 	if (s_cntx_id > -1) {
 		for (i = 0; i < ie_words; i++)
-			plic_set_ie(s_cntx_id, i, 0);
+			plic_set_ie(plic, s_cntx_id, i, 0);
 	}
 
 	/* By default, disable M-mode threshold */
 	if (m_cntx_id > -1)
-		plic_set_thresh(m_cntx_id, 0xffffffff);
+		plic_set_thresh(plic, m_cntx_id, 0x7);
 
 	/* By default, disable S-mode threshold */
 	if (s_cntx_id > -1)
-		plic_set_thresh(s_cntx_id, 0xffffffff);
+		plic_set_thresh(plic, s_cntx_id, 0x7);
 
 	return 0;
 }
 
-int plic_cold_irqchip_init(unsigned long base, u32 num_sources, u32 hart_count)
+int plic_cold_irqchip_init(struct plic_data *plic)
 {
 	int i;
 
-	plic_hart_count	 = hart_count;
-	plic_num_sources = num_sources;
-	plic_base	 = (void *)base;
+	if (!plic)
+		return SBI_EINVAL;
 
 	/* Configure default priorities of all IRQs */
-	for (i = 1; i <= plic_num_sources; i++)
-		plic_set_priority(i, 0);
+	for (i = 1; i <= plic->num_src; i++)
+		plic_set_priority(plic, i, 0);
 
 	return 0;
 }