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Author SHA1 Message Date
Yu Chien Peter LinandAnup Patel bd7ef41398 platform: andes/ae350: Remove enabling cache from an350_final_init 
The boot-time cache operations have been handled by U-boot SPL, so we
can drop duplicate code.

Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
 2022-10-23 10:23:13 +05:30
Yu Chien Peter LinandAnup Patel dcdaf30274 lib: sbi: Add sbi_domain_root_add_memrange() API 
This patch generalizes the logic to add a memory range with desired
alignment and flags of consecutive regions to the root domain.

Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
 2022-10-23 10:21:21 +05:30
Yu Chien Peter LinandAnup Patel 60b78fee92 include: sbi: Fix grammar in comment 
Fix minor grammar issue in function description.

Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
 2022-10-23 10:20:04 +05:30
Yu Chien Peter LinandAnup Patel 11d14ae7f2 lib: sbi: Fix typo in comment 
%s/is is/is

Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
 2022-10-23 10:19:28 +05:30
Yu Chien Peter LinandAnup Patel 98aa12738d include: sbi: Fix typo in comment 
%s/Priviledge/Privilege

Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
 2022-10-23 10:17:22 +05:30