Anup Patel and Anup Patel
b55bb4cdcb
lib: sbi_irqchip: Support irqchip device targetting subset of harts
...
It is possible to have platform where an irqchip device targets
a subset of harts and there are multiple irqchip devices to cover
all harts.
To support this scenario:
1) Add target_harts hartmask to struct sbi_irqchip_device which
represents the set of harts targetted by the irqchip device
2) Call warm_init() and process_hwirqs() callbacks of an irqchip
device on a hart only if irqchip device targets that particular
hart
Signed-off-by: Anup Patel <anup.patel@oss.qualcomm.com >
Link: https://lore.kernel.org/r/20260213055342.3124872-6-anup.patel@oss.qualcomm.com
Signed-off-by: Anup Patel <anup@brainfault.org >
2026-03-22 10:53:33 +05:30
Anup Patel and Anup Patel
5a300b32d5
lib: utils/irqchip: Add IDC to hartindex map in struct aplic_data
...
A platform can have multiple APLICs in direct-mode targetting
different subset of harts. Add APLIC ID to hartindex map in
struct aplic_data to capture the set of harts targeted by a
given APLIC in direct-mode.
Signed-off-by: Anup Patel <anup.patel@oss.qualcomm.com >
Link: https://lore.kernel.org/r/20260213055342.3124872-5-anup.patel@oss.qualcomm.com
Signed-off-by: Anup Patel <anup@brainfault.org >
2026-03-22 10:52:45 +05:30
Anup Patel and Anup Patel
6d68f3bebd
lib: utils/irqchip: Fix context_map init in irqchip_plic_update_context_map()
...
The context_map[][] elements should be initialized with negative
value so that context_map does not point to anything for non-existent
PLIC contexts.
Fixes: 69448a0790anup.patel@oss.qualcomm.com >
Link: https://lore.kernel.org/r/20260213055342.3124872-4-anup.patel@oss.qualcomm.com
Signed-off-by: Anup Patel <anup@brainfault.org >
2026-03-22 10:52:43 +05:30
Anup Patel and Anup Patel
2110aab68f
lib: sbi_irqchip: Rename irq_handle() callback to process_hwirqs()
...
The irq_handle() callback of irqchip device is meant to process
hardware interrupt of the irqchip hence rename it accordingly.
Signed-off-by: Anup Patel <anup.patel@oss.qualcomm.com >
Link: https://lore.kernel.org/r/20260213055342.3124872-3-anup.patel@oss.qualcomm.com
Signed-off-by: Anup Patel <anup@brainfault.org >
2026-03-22 10:52:41 +05:30
Anup Patel and Anup Patel
51837c731b
lib: sbi_irqchip: Use chip as variable name for irqchip device
...
The irqchip device represents an interrupt controller so use chip
as variable name instead of dev. This will avoid confusion as the
sbi_irqchip framework grows.
Signed-off-by: Anup Patel <anup.patel@oss.qualcomm.com >
Link: https://lore.kernel.org/r/20260213055342.3124872-2-anup.patel@oss.qualcomm.com
Signed-off-by: Anup Patel <anup@brainfault.org >
2026-03-22 10:52:40 +05:30
Anup Patel and Anup Patel
9a46ef43a4
include: Fix LLVM compile error in sbi_utils/hsm/fdt_hsm_sifive_inst.h
...
Currently, OpenSBI fails to compile for LLVM=1 using 2025.11.27
riscv-gnu-toolchain with the following error:
In file included from opensbi/lib/utils/suspend/fdt_suspend_sifive_smc0.c:20:
opensbi/include/sbi_utils/hsm/fdt_hsm_sifive_inst.h:17:23: error: expected instruction format
17 | __asm__ __volatile__(".insn 0xfc000073" ::: "memory");
| ^
<inline asm>:1:8: note: instantiated into assembly here
1 | .insn 0xfc000073
| ^
In file included from opensbi/lib/utils/suspend/fdt_suspend_sifive_smc0.c:20:
opensbi/include/sbi_utils/hsm/fdt_hsm_sifive_inst.h:12:23: error: expected instruction format
12 | __asm__ __volatile__(".insn 0x30500073" ::: "memory");
| ^
<inline asm>:1:8: note: instantiated into assembly here
1 | .insn 0x30500073
| ^
2 errors generated.
To fix this compile error, use ".word" in-place ".insn".
Fixes: 1514a32730anup.patel@oss.qualcomm.com >
Link: https://lore.kernel.org/r/20251227100916.327524-1-anup.patel@oss.qualcomm.com
Signed-off-by: Anup Patel <anup@brainfault.org >
2025-12-28 20:47:12 +05:30
