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Author	SHA1	Message	Date
Atish PatraandAnup Patel	a26dc609df	lib: sbi: Disable interrupt and inhibit counting in M-mode during init ... Currently, the mhpmevent CSRs are untouched during hart init during cold/warm boot. Ideally, we should clear out all the bits except overflow and MINH bit. That is required to disable overflow interrupt and inhibit counting in M-mode to avoid any spurious interrupts before perf start. Signed-off-by: Atish Patra <atishp@rivosinc.com> Reviewed-by: Anup Patel <anup@brainfault.org>	2022-02-04 10:10:28 +05:30
Atish PatraandAnup Patel	3b7c204dca	lib: sbi: Disable interrupt during config matching ... PMU overflow interrupt should be disabled durinig initial configuration of counters. They should be enabled while starting counters. Fixes: 730f01bb41 ("lib: sbi: Support sscofpmf extension in OpenSBI") Signed-off-by: Atish Patra <atishp@rivosinc.com> Reviewed-by: Anup Patel <anup@brainfault.org>	2022-02-04 10:08:57 +05:30
Atish PatraandAnup Patel	632f59392b	lib: sbi: Map only the counters enabled in hardware ... The counter mapping in DT may be incorrect if all the counters specified in the mapping are actually not physically present in the hardware. OpenSBI should only keep a mapping of counters enabled in hardware and defined in DT. This assume that all the programmable hpmcounters are consecutive as it doesn't make sense to build a system with sparse hpmcounters. Signed-off-by: Atish Patra <atishp@rivosinc.com> Reviewed-by: Anup Patel <anup@brainfault.org>	2022-02-04 10:07:07 +05:30