Some older toolchains may not have all the csr's defined. Update all
the csr functions to use the CSR_ #define values instead of the
toolchain defined values.
Signed-off-by: Atish Patra <atish.patra@wdc.com>
Some older toolchains may not have all the csr's defined. Update all
the csr functions to use the CSR_ #define values instead of the
toolchain defined values.
Suggested-by: Olof Johansson <olof@lixom.net>
Signed-off-by: Atish Patra <atish.patra@wdc.com>
Some older toolchains may not have all the csr's defined. Update all
the csr functions to use the CSR_ #define values instead of the
toolchain defined values.
Suggested-by: Olof Johansson <olof@lixom.net>
Signed-off-by: Atish Patra <atish.patra@wdc.com>
Currently, only hart 1 is enabled for fu540 platform to support U-boot.
Introduce a compile time FU540_ENABLED_HART_MASK option so that specific
harts can be selected for booting. As fu540 is a multicore, we should
boot all cores by default except hart 0.
Signed-off-by: Atish Patra <atish.patra@wdc.com>
As per the RISC-V ISA, mideleg and medeleg registers should not exist
if S-mode is not present for a hart.
We shouldn't access these CSRs if non S-mode harts.
Signed-off-by: Atish Patra <atish.patra@wdc.com>
S-mode software may send IPI to self. For example,
tlbflush may be executed for the same hart.
Let the hart send IPI to itself. It's an overhead
but doesn't break anything. However, if we don't
allow it, it breaks if S-mode keep sending IPIs.
Signed-off-by: Atish Patra <atish.patra@wdc.com>
IPIs are updated in scratch space by source hart.
However, different harts or same hart may want to
send different IPIs before previous IPI was read
by the target hart. Currently, previous IPI type
is overwritten in that case.
Use atomic bit set/clear operations to update IPIs.
Signed-off-by: Atish Patra <atish.patra@wdc.com>
The secondary hart waits for an IPI signal from the boot hart to
executing boot code (hot boot). As a result, software generated
interrupts have to be enabled for secondary harts before waiting for
the boot hart boot completion IPI signal.
Enabling software generated interrupts (IPI) can be done independently
of the firmware code and moved to libsbi code so that the different
firmware do not have to implement this.
Signed-off-by: Atish Patra <atish.patra@wdc.com>
PLIC DT entry fixup can be done by comparing external
interrupt number instead of context id. No need to invoke
fixup for each plic context.
Signed-off-by: Atish Patra <atish.patra@wdc.com>
Perform following DT updates.
1. Mask hart if mmu is not supported.
2. Add stdout-path under chosen node.
Signed-off-by: Atish Patra <atish.patra@wdc.com>
There are couple of string function defined in platform
code. We no longer need them as we can directly link minimal
libc.
Every platform required to inclde this as PLIC driver required
libc functions.
Signed-off-by: Atish Patra <atish.patra@wdc.com>
Some of the platform (i.e. SiFive FU540) requires Device
Tree modification before it is passed to higher stages.
Add libfdt support now to help this process. Libfdt should
only be included per platform basis.
Signed-off-by: Atish Patra <atish.patra@wdc.com>
As of now, uboot doesn't have support for SMP.
Moreover, unleashed board has a E51 hart which
doesn't not support S mode.
We should only boot only 1 non-zero hart.
Signed-off-by: Atish Patra <atish.patra@wdc.com>
We should not jump to next stage if next mode (S-mode or U-mode)
is not supported by HART.
Signed-off-by: Atish Patra <atish.patra@wdc.com>
Signed-off-by: Anup Patel <anup.patel@wdc.com>
