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Author SHA1 Message Date
Yu Chien Peter LinandAnup Patel 6f3258e671 platform: andes/ae350: Add fw_platform_init for platform initialization 
This patch adds fw_platform_init() to initialize ae350 platform.name
and platform.hart_count by parsing device tree.

Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
 2022-10-23 10:30:21 +05:30
Yu Chien Peter LinandAnup Patel 127a3f2ab4 platform: andes/ae350: Use fdt irqchip driver 
Andes PLIC is compatible with plic driver. The PLIC base address and
number of source can be obtained by parsing the device tree.

Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
 2022-10-23 10:29:58 +05:30
Yu Chien Peter LinandAnup Patel 8234fc1bdf lib: utils/reset: Add Andes fdt reset driver support 
Add ATCWDT200 as reset device of AE350 platform, this driver requires
SMU to program the reset vector registers before triggering WDT software
restart signal.

dts example:

  smu@f0100000 {
    compatible = "andestech,atcsmu";
    reg = <0x00000000 0xf0100000 0x00000000 0x00001000>;
  };

  wdt: wdt@f0500000 {
    compatible = "andestech,atcwdt200";
    reg = <0x00000000 0xf0500000 0x00000000 0x00001000>;
    interrupts = <3 4>;
    interrupt-parent = <&plic0>;
    clock-frequency = <15000000>;
  };

Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
 2022-10-23 10:29:23 +05:30
Yu Chien Peter LinandAnup Patel ef9f02e7fb lib: utils/timer: Add Andes fdt timer support 
Since we can get the PLMT base address and timer frequency from
device tree, move plmt timer device to fdt timer framework.

dts example (Quad-core AX45MP):

  cpus {
      ...
      timebase-frequency = <0x3938700>;
      ...
  }
  soc {
      ...
      plmt0@e6000000 {
          compatible = "andestech,plmt0";
          reg = <0x00 0xe6000000 0x00 0x100000>;
          interrupts-extended = <&cpu0_intc 0x07
                                 &cpu1_intc 0x07
                                 &cpu2_intc 0x07
                                 &cpu3_intc 0x07>;
      };
      ...
  }

Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
 2022-10-23 10:26:39 +05:30
Yu Chien Peter LinandAnup Patel 88f58a3694 platform: andes/ae350: Use fdt serial driver 
Andes UART is compatible with uart8250 driver. We can use
fdt_serial_init() as platform console init hook.

dts example:

  serial0: serial@f0300000 {
    compatible = "andestech,uart16550", "ns16550a";
    reg = <0x00000000 0xf0300000 0x00000000 0x00001000>;
    interrupts = <9 4>;
    interrupt-parent = <&plic0>;
    clock-frequency = <19660800>;
    current-speed = <38400>;
    reg-shift = <2>;
    reg-offset = <32>;
    reg-io-width = <4>;
    no-loopback-test = <1>;
  };

Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
 2022-10-23 10:26:06 +05:30
Yu Chien Peter LinandAnup Patel 9899b59beb platform: andes/ae350: Use kconfig to set platform version and default name 
This patch makes andes platform name and version can be set in
menuconfig interface.

Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
 2022-10-23 10:25:13 +05:30
Yu Chien Peter LinandAnup Patel bd7ef41398 platform: andes/ae350: Remove enabling cache from an350_final_init 
The boot-time cache operations have been handled by U-boot SPL, so we
can drop duplicate code.

Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
 2022-10-23 10:23:13 +05:30
Yu Chien Peter LinandAnup Patel dcdaf30274 lib: sbi: Add sbi_domain_root_add_memrange() API 
This patch generalizes the logic to add a memory range with desired
alignment and flags of consecutive regions to the root domain.

Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
 2022-10-23 10:21:21 +05:30
Yu Chien Peter LinandAnup Patel 60b78fee92 include: sbi: Fix grammar in comment 
Fix minor grammar issue in function description.

Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
 2022-10-23 10:20:04 +05:30
Yu Chien Peter LinandAnup Patel 11d14ae7f2 lib: sbi: Fix typo in comment 
%s/is is/is

Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
 2022-10-23 10:19:28 +05:30
Yu Chien Peter LinandAnup Patel 98aa12738d include: sbi: Fix typo in comment 
%s/Priviledge/Privilege

Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
 2022-10-23 10:17:22 +05:30