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Commit Graph

Author	SHA1	Message	Date
Zong LiandAnup Patel	5c5cbb53a4	lib: utils/serial: support 'reg-offset' property reg-offset property is used for offset to apply to the mapbase from the start of the registers in 8250 UART. In Linux kernel, it has been handled in 8250 UART driver. dt-bindings: <linux>/Documentation/devicetree/bindings/serial/8250.yaml Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Anup Patel <anup@brainfault.org>	2022-04-17 13:57:48 +05:30
Zong LiandAnup Patel	1ed9eb255d	Write MSIP by using memory-mapped control register The machine-level MSIP bits are written by accesses to memory-mapped control registers. Only use CSR instruction for SSIP and USIP. There is no effect that using CSR instruction to write MSIP when testing on unleashed board and QEMU. Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Anup Patel <anup.patel@wdc.com>	2019-09-28 18:23:13 +05:30

Author

SHA1

Message

Date

Zong LiandAnup Patel

5c5cbb53a4

lib: utils/serial: support 'reg-offset' property

reg-offset property is used for offset to apply to the mapbase
from the start of the registers in 8250 UART. In Linux kernel,
it has been handled in 8250 UART driver.

dt-bindings:
<linux>/Documentation/devicetree/bindings/serial/8250.yaml

Signed-off-by: Zong Li <zong.li@sifive.com>
Reviewed-by: Anup Patel <anup@brainfault.org>

2022-04-17 13:57:48 +05:30

Zong LiandAnup Patel

1ed9eb255d

Write MSIP by using memory-mapped control register

The machine-level MSIP bits are written by accesses to memory-mapped
control registers. Only use CSR instruction for SSIP and USIP.

There is no effect that using CSR instruction to write MSIP when testing
on unleashed board and QEMU.

Signed-off-by: Zong Li <zong.li@sifive.com>
Reviewed-by: Anup Patel <anup.patel@wdc.com>

2019-09-28 18:23:13 +05:30