4 Commits
Author SHA1 Message Date
Zong LiandAnup Patel bf10d3bf89 firmware: Fix comment after relocation completion
After relocation is done, the code is running from the load address,
not the link address. Fix the comment to correctly reflect this.

Signed-off-by: Zong Li <zong.li@sifive.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
Link: https://lore.kernel.org/r/20260626022121.1885209-1-zong.li@sifive.com
Signed-off-by: Anup Patel <anup@brainfault.org>
2026-06-28 14:08:14 +05:30
Zong LiandAnup Patel 570b9ae89a include: sbi_bitops: add ULL version for BIT and GENMASK
Add BIT_ULL and GENMASK_ULL for dealing with 64-bits data on
32-bits CPU, then we don't need to separate the operation to
low part and high part. For instance, the MMIO register is
64 bits wide.

Signed-off-by: Zong Li <zong.li@sifive.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
2024-09-23 18:33:02 +05:30
Zong LiandAnup Patel 5c5cbb53a4 lib: utils/serial: support 'reg-offset' property
reg-offset property is used for offset to apply to the mapbase
from the start of the registers in 8250 UART. In Linux kernel,
it has been handled in 8250 UART driver.

dt-bindings:
<linux>/Documentation/devicetree/bindings/serial/8250.yaml

Signed-off-by: Zong Li <zong.li@sifive.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
2022-04-17 13:57:48 +05:30
Zong LiandAnup Patel 1ed9eb255d Write MSIP by using memory-mapped control register
The machine-level MSIP bits are written by accesses to memory-mapped
control registers. Only use CSR instruction for SSIP and USIP.

There is no effect that using CSR instruction to write MSIP when testing
on unleashed board and QEMU.

Signed-off-by: Zong Li <zong.li@sifive.com>
Reviewed-by: Anup Patel <anup.patel@wdc.com>
2019-09-28 18:23:13 +05:30