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lib: sbi: Allow platforms to override local TLB operations

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Some T-Head based processors, for example the Sophgo SG2044, have a
JTLB errata that requires special handling of certain TLB maintenance
instructions (sfence.vma).

Introduce a sbi_tlb_local_operations structure so platforms can provide
custom local TLB flush implementations. Use it to implement the JTLB
workaround on affected SoCs (currently Sophgo SG2044).

Signed-off-by: Xiang W <wangxiang@iscas.ac.cn>
Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
Reviewed-by: Anup Patel <anup@brainfault.org>
Link: https://lore.kernel.org/r/20260617112925.1144190-2-wangxiang@iscas.ac.cn
Signed-off-by: Anup Patel <anup@brainfault.org>
This commit is contained in:
Xiang W
2026-08-20 20:30:48 +05:30
committed by Anup Patel
parent 65be0e37c4
commit f465413402
4 changed files with 101 additions and 8 deletions
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platform/generic/include/thead/c9xx_errata.h
+1
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@@ -8,6 +8,7 @@
*/
#define THEAD_QUIRK_ERRATA_TLB_FLUSH BIT(0)
#define THEAD_QUIRK_ERRATA_THEAD_PMU BIT(1)
#define THEAD_QUIRK_ERRATA_JTLB BIT(2)
void thead_register_tlb_flush_trap_handler(void);