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Xiang W
f465413402
Some T-Head based processors, for example the Sophgo SG2044, have a JTLB errata that requires special handling of certain TLB maintenance instructions (sfence.vma). Introduce a sbi_tlb_local_operations structure so platforms can provide custom local TLB flush implementations. Use it to implement the JTLB workaround on affected SoCs (currently Sophgo SG2044). Signed-off-by: Xiang W <wangxiang@iscas.ac.cn> Signed-off-by: Han Gao <gaohan@iscas.ac.cn> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20260617112925.1144190-2-wangxiang@iscas.ac.cn Signed-off-by: Anup Patel <anup@brainfault.org>
16 lines
430 B
C
16 lines
430 B
C
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#ifndef __RISCV_THEAD_C9XX_ERRATA_H____
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#define __RISCV_THEAD_C9XX_ERRATA_H____
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/**
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* T-HEAD board with this quirk need to execute sfence.vma to flush
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* stale entrie avoid incorrect memory access.
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*/
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#define THEAD_QUIRK_ERRATA_TLB_FLUSH BIT(0)
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#define THEAD_QUIRK_ERRATA_THEAD_PMU BIT(1)
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#define THEAD_QUIRK_ERRATA_JTLB BIT(2)
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void thead_register_tlb_flush_trap_handler(void);
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#endif // __RISCV_THEAD_C9XX_ERRATA_H____
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