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lib: utils/timer: Add Andes fdt timer support

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Since we can get the PLMT base address and timer frequency from
device tree, move plmt timer device to fdt timer framework.

dts example (Quad-core AX45MP):

  cpus {
      ...
      timebase-frequency = <0x3938700>;
      ...
  }
  soc {
      ...
      plmt0@e6000000 {
          compatible = "andestech,plmt0";
          reg = <0x00 0xe6000000 0x00 0x100000>;
          interrupts-extended = <&cpu0_intc 0x07
                                 &cpu1_intc 0x07
                                 &cpu2_intc 0x07
                                 &cpu3_intc 0x07>;
      };
      ...
  }

Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
This commit is contained in:
Yu Chien Peter Lin
2022-10-14 08:32:46 +08:00
committed by Anup Patel
parent 88f58a3694
commit ef9f02e7fb
13 changed files with 259 additions and 144 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
platform/andes/ae350/Kconfig
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@@ -6,6 +6,8 @@ config PLATFORM_ANDES_AE350
select IRQCHIP_PLIC
select FDT_SERIAL
select FDT_SERIAL_UART8250
select FDT_TIMER
select FDT_TIMER_PLMT
default y
if PLATFORM_ANDES_AE350

2
platform/andes/ae350/objects.mk
View File

@@ -15,7 +15,7 @@ platform-asflags-y =
platform-ldflags-y =
# Objects to build
platform-objs-y += cache.o platform.o plicsw.o plmt.o
platform-objs-y += cache.o platform.o plicsw.o
# Blobs to build
FW_TEXT_START=0x00000000

19
platform/andes/ae350/platform.c
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@@ -19,9 +19,9 @@
#include <sbi_utils/fdt/fdt_fixup.h>
#include <sbi_utils/irqchip/plic.h>
#include <sbi_utils/serial/fdt_serial.h>
#include <sbi_utils/timer/fdt_timer.h>
#include "platform.h"
#include "plicsw.h"
#include "plmt.h"
#include "cache.h"
static struct plic_data plic = {
@@ -81,21 +81,6 @@ static int ae350_ipi_init(bool cold_boot)
return plicsw_warm_ipi_init();
}
/* Initialize platform timer for current HART. */
static int ae350_timer_init(bool cold_boot)
{
int ret;
if (cold_boot) {
ret = plmt_cold_timer_init(AE350_PLMT_ADDR,
AE350_HART_COUNT);
if (ret)
return ret;
}
return plmt_warm_timer_init();
}
/* Vendor-Specific SBI handler */
static int ae350_vendor_ext_provider(long extid, long funcid,
const struct sbi_trap_regs *regs, unsigned long *out_value,
@@ -150,7 +135,7 @@ const struct sbi_platform_operations platform_ops = {
.ipi_init = ae350_ipi_init,
.timer_init = ae350_timer_init,
.timer_init = fdt_timer_init,
.vendor_ext_provider = ae350_vendor_ext_provider
};

2
platform/andes/ae350/platform.h
View File

@@ -18,8 +18,6 @@
#define AE350_PLICSW_ADDR 0xe6400000
#define AE350_PLMT_ADDR 0xe6000000
#define AE350_L2C_ADDR 0xe0500000
/*Memory and Miscellaneous Registers*/

107
platform/andes/ae350/plmt.c
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@@ -1,107 +0,0 @@
/*
* SPDX-License-Identifier: BSD-2-Clause
*
* Copyright (c) 2019 Andes Technology Corporation
*
* Authors:
* Zong Li <zong@andestech.com>
* Nylon Chen <nylon7@andestech.com>
*/
#include <sbi/riscv_asm.h>
#include <sbi/riscv_io.h>
#include <sbi/sbi_timer.h>
static u32 plmt_time_hart_count;
static volatile void *plmt_time_base;
static volatile u64 *plmt_time_val;
static volatile u64 *plmt_time_cmp;
static u64 plmt_timer_value(void)
{
#if __riscv_xlen == 64
return readq_relaxed(plmt_time_val);
#else
u32 lo, hi;
do {
hi = readl_relaxed((void *)plmt_time_val + 0x04);
lo = readl_relaxed(plmt_time_val);
} while (hi != readl_relaxed((void *)plmt_time_val + 0x04));
return ((u64)hi << 32) | (u64)lo;
#endif
}
static void plmt_timer_event_stop(void)
{
u32 target_hart = current_hartid();
if (plmt_time_hart_count <= target_hart)
return;
/* Clear PLMT Time Compare */
#if __riscv_xlen == 64
writeq_relaxed(-1ULL, &plmt_time_cmp[target_hart]);
#else
writel_relaxed(-1UL, &plmt_time_cmp[target_hart]);
writel_relaxed(-1UL, (void *)(&plmt_time_cmp[target_hart]) + 0x04);
#endif
}
static void plmt_timer_event_start(u64 next_event)
{
u32 target_hart = current_hartid();
if (plmt_time_hart_count <= target_hart)
return;
/* Program PLMT Time Compare */
#if __riscv_xlen == 64
writeq_relaxed(next_event, &plmt_time_cmp[target_hart]);
#else
u32 mask = -1UL;
writel_relaxed(next_event & mask, &plmt_time_cmp[target_hart]);
writel_relaxed(next_event >> 32,
(void *)(&plmt_time_cmp[target_hart]) + 0x04);
#endif
}
static struct sbi_timer_device plmt_timer = {
.name = "ae350_plmt",
.timer_value = plmt_timer_value,
.timer_event_start = plmt_timer_event_start,
.timer_event_stop = plmt_timer_event_stop
};
int plmt_warm_timer_init(void)
{
u32 target_hart = current_hartid();
if (plmt_time_hart_count <= target_hart || !plmt_time_base)
return -1;
/* Clear PLMT Time Compare */
#if __riscv_xlen == 64
writeq_relaxed(-1ULL, &plmt_time_cmp[target_hart]);
#else
writel_relaxed(-1UL, &plmt_time_cmp[target_hart]);
writel_relaxed(-1UL, (void *)(&plmt_time_cmp[target_hart]) + 0x04);
#endif
return 0;
}
int plmt_cold_timer_init(unsigned long base, u32 hart_count)
{
plmt_time_hart_count = hart_count;
plmt_time_base = (void *)base;
plmt_time_val = (u64 *)(plmt_time_base);
plmt_time_cmp = (u64 *)(plmt_time_base + 0x8);
sbi_timer_set_device(&plmt_timer);
return 0;
}

17
platform/andes/ae350/plmt.h
View File

@@ -1,17 +0,0 @@
/*
* SPDX-License-Identifier: BSD-2-Clause
*
* Copyright (c) 2019 Andes Technology Corporation
*
* Authors:
* Zong Li <zong@andestech.com>
*/
#ifndef _AE350_PLMT_H_
#define _AE350_PLMT_H_
int plmt_warm_timer_init(void);
int plmt_cold_timer_init(unsigned long base, u32 hart_count);
#endif /* _AE350_PLMT_H_ */