Mirrors/opensbi
7
0
Fork 1
mirror of https://github.com/riscv-software-src/opensbi.git synced 2025-08-25 15:51:41 +01:00
Code Issues Packages Projects Releases Wiki Activity

firmware: Remove redundant write to mideleg and medeleg

Browse Source 
The mideleg and medeleg are already programmed in delegate_traps()
so no need to set it here.

Any CSR setup in our reference firmware becomes a requirement
for bootloader linking to libsbi.a so we should have minimum
possible CSR setup in our reference firmware.

Signed-off-by: Anup Patel <anup.patel@wdc.com>
This commit is contained in:
Anup Patel
2018-12-21 15:05:59 +05:30
committed by Anup Patel
parent 4e15d79419
commit ef5f4e149c
1 changed files with 0 additions and 2 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
firmware/fw_common.S
View File

@@ -119,8 +119,6 @@ _wait_for_boot_hart:
_start_warm: _start_warm:
/* Disable and clear all interrupts */ /* Disable and clear all interrupts */
csrw mideleg, zero
csrw medeleg, zero
csrw mie, zero csrw mie, zero
csrw mip, zero csrw mip, zero