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platform: generic: renesas: rzfive: Add support to configure the PMA

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I/O Coherence Port (IOCP) provides an AXI interface for connecting
external non-caching masters, such as DMA controllers. The accesses
from IOCP are coherent with D-Caches and L2 Cache.

IOCP is a specification option and is disabled on the Renesas RZ/Five
SoC due to this reason IP blocks using DMA will fail.

The Andes AX45MP core has a Programmable Physical Memory Attributes (PMA)
block that allows dynamic adjustment of memory attributes in the runtime.
It contains a configurable amount of PMA entries implemented as CSR
registers to control the attributes of memory locations in interest.
Below are the memory attributes supported:
* Device, Non-bufferable
* Device, bufferable
* Memory, Non-cacheable, Non-bufferable
* Memory, Non-cacheable, Bufferable
* Memory, Write-back, No-allocate
* Memory, Write-back, Read-allocate
* Memory, Write-back, Write-allocate
* Memory, Write-back, Read and Write-allocate

More info about PMA (section 10.3):
Link: http://www.andestech.com/wp-content/uploads/AX45MP-1C-Rev.-5.0.0-Datasheet.pdf

As a workaround for SoCs with IOCP disabled CMO needs to be handled by
software. Firstly OpenSBI configures the memory region as
"Memory, Non-cacheable, Bufferable" and passes this region as a global
shared dma pool as a DT node. With DMA_GLOBAL_POOL enabled all DMA
allocations happen from this region and synchronization callbacks are
implemented to synchronize when doing DMA transactions.

Example PMA region passed as a DT node from OpenSBI:
    reserved-memory {
        #address-cells = <2>;
        #size-cells = <2>;
        ranges;

        pma_resv0@58000000 {
            compatible = "shared-dma-pool";
            reg = <0x0 0x58000000 0x0 0x08000000>;
            no-map;
            linux,dma-default;
        };
    };

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Yu Chien Peter Lin <peterlin@andestech.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
This commit is contained in:
Lad Prabhakar
2023-02-13 21:51:09 +00:00
committed by Anup Patel
parent 31b82e0d50
commit c10095132a
5 changed files with 407 additions and 0 deletions
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48
platform/generic/include/andes/andes45_pma.h Normal file
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/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2023 Renesas Electronics Corp.
*/
#ifndef _ANDES45_PMA_H_
#define _ANDES45_PMA_H_
#include <sbi/sbi_types.h>
#define ANDES45_MAX_PMA_REGIONS 16
/* Naturally aligned power of 2 region */
#define ANDES45_PMACFG_ETYP_NAPOT 3
/* Memory, Non-cacheable, Bufferable */
#define ANDES45_PMACFG_MTYP_MEM_NON_CACHE_BUF (3 << 2)
/**
* struct andes45_pma_region - Describes PMA regions
*
* @pa: Address to be configured in the PMA
* @size: Size of the region
* @flags: Flags to be set for the PMA region
* @dt_populate: Boolean flag indicating if the DT entry should be
* populated for the given PMA region
* @shared_dma: Boolean flag if set "shared-dma-pool" property will
* be set in the DT node
* @no_map: Boolean flag if set "no-map" property will be set in the
* DT node
* @dma_default: Boolean flag if set "linux,dma-default" property will
* be set in the DT node. Note Linux expects single node
* with this property set.
*/
struct andes45_pma_region {
unsigned long pa;
unsigned long size;
u8 flags:7;
bool dt_populate;
bool shared_dma;
bool no_map;
bool dma_default;
};
int andes45_pma_setup_regions(const struct andes45_pma_region *pma_regions,
unsigned int pma_regions_count);
#endif /* _ANDES45_PMA_H_ */