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c10095132a
I/O Coherence Port (IOCP) provides an AXI interface for connecting external non-caching masters, such as DMA controllers. The accesses from IOCP are coherent with D-Caches and L2 Cache. IOCP is a specification option and is disabled on the Renesas RZ/Five SoC due to this reason IP blocks using DMA will fail. The Andes AX45MP core has a Programmable Physical Memory Attributes (PMA) block that allows dynamic adjustment of memory attributes in the runtime. It contains a configurable amount of PMA entries implemented as CSR registers to control the attributes of memory locations in interest. Below are the memory attributes supported: * Device, Non-bufferable * Device, bufferable * Memory, Non-cacheable, Non-bufferable * Memory, Non-cacheable, Bufferable * Memory, Write-back, No-allocate * Memory, Write-back, Read-allocate * Memory, Write-back, Write-allocate * Memory, Write-back, Read and Write-allocate More info about PMA (section 10.3): Link: http://www.andestech.com/wp-content/uploads/AX45MP-1C-Rev.-5.0.0-Datasheet.pdf As a workaround for SoCs with IOCP disabled CMO needs to be handled by software. Firstly OpenSBI configures the memory region as "Memory, Non-cacheable, Bufferable" and passes this region as a global shared dma pool as a DT node. With DMA_GLOBAL_POOL enabled all DMA allocations happen from this region and synchronization callbacks are implemented to synchronize when doing DMA transactions. Example PMA region passed as a DT node from OpenSBI: reserved-memory { #address-cells = <2>; #size-cells = <2>; ranges; pma_resv0@58000000 { compatible = "shared-dma-pool"; reg = <0x0 0x58000000 0x0 0x08000000>; no-map; linux,dma-default; }; }; Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Anup Patel <anup@brainfault.org>
49 lines
1.3 KiB
C
49 lines
1.3 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2023 Renesas Electronics Corp.
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*/
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#ifndef _ANDES45_PMA_H_
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#define _ANDES45_PMA_H_
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#include <sbi/sbi_types.h>
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#define ANDES45_MAX_PMA_REGIONS 16
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/* Naturally aligned power of 2 region */
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#define ANDES45_PMACFG_ETYP_NAPOT 3
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/* Memory, Non-cacheable, Bufferable */
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#define ANDES45_PMACFG_MTYP_MEM_NON_CACHE_BUF (3 << 2)
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/**
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* struct andes45_pma_region - Describes PMA regions
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*
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* @pa: Address to be configured in the PMA
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* @size: Size of the region
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* @flags: Flags to be set for the PMA region
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* @dt_populate: Boolean flag indicating if the DT entry should be
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* populated for the given PMA region
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* @shared_dma: Boolean flag if set "shared-dma-pool" property will
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* be set in the DT node
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* @no_map: Boolean flag if set "no-map" property will be set in the
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* DT node
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* @dma_default: Boolean flag if set "linux,dma-default" property will
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* be set in the DT node. Note Linux expects single node
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* with this property set.
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*/
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struct andes45_pma_region {
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unsigned long pa;
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unsigned long size;
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u8 flags:7;
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bool dt_populate;
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bool shared_dma;
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bool no_map;
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bool dma_default;
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};
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int andes45_pma_setup_regions(const struct andes45_pma_region *pma_regions,
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unsigned int pma_regions_count);
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#endif /* _ANDES45_PMA_H_ */
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