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https://github.com/riscv-software-src/opensbi.git
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include: Rename ECALL defines to match latest RISC-V spec
We rename CAUSE_HYPERVISOR_ECALL to CAUSE_SUPERVISOR_ECALL and CAUSE_SUPERVISOR_ECALL to CAUSE_VIRTUAL_SUPERVISOR_ECALL so that it matches latest RISC-V privilege spec. Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Atish Patra <atish.patra@wdc.com>
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@@ -539,8 +539,8 @@
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#define CAUSE_MISALIGNED_STORE 0x6
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#define CAUSE_STORE_ACCESS 0x7
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#define CAUSE_USER_ECALL 0x8
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#define CAUSE_HYPERVISOR_ECALL 0x9
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#define CAUSE_SUPERVISOR_ECALL 0xa
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#define CAUSE_SUPERVISOR_ECALL 0x9
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#define CAUSE_VIRTUAL_SUPERVISOR_ECALL 0xa
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#define CAUSE_MACHINE_ECALL 0xb
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#define CAUSE_FETCH_PAGE_FAULT 0xc
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#define CAUSE_LOAD_PAGE_FAULT 0xd
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@@ -108,7 +108,7 @@ static int delegate_traps(struct sbi_scratch *scratch, u32 hartid)
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* from VS-mode), Guest page faults and Virtual interrupts.
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*/
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if (misa_extension('H')) {
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exceptions |= (1U << CAUSE_SUPERVISOR_ECALL);
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exceptions |= (1U << CAUSE_VIRTUAL_SUPERVISOR_ECALL);
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exceptions |= (1U << CAUSE_FETCH_GUEST_PAGE_FAULT);
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exceptions |= (1U << CAUSE_LOAD_GUEST_PAGE_FAULT);
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exceptions |= (1U << CAUSE_VIRTUAL_INST_FAULT);
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@@ -251,7 +251,7 @@ void sbi_trap_handler(struct sbi_trap_regs *regs)
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rc = sbi_misaligned_store_handler(mtval, mtval2, mtinst, regs);
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msg = "misaligned store handler failed";
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break;
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case CAUSE_HYPERVISOR_ECALL:
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case CAUSE_SUPERVISOR_ECALL:
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rc = sbi_ecall_handler(regs);
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msg = "ecall handler failed";
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break;
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