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platform: generic: mips p8700: CPU clusters memranges

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Reserve memory regions for CPU clusters according to P8700
cluster memory layout.

There's a set of components in the CPU cluster according to [1]

[1] https://mips.com/wp-content/uploads/2025/11/P8700-F_Programmers_Reference_Manual-TM.pdf

Signed-off-by: Vladimir Kondratiev <vladimir.kondratiev@mobileye.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
Link: https://lore.kernel.org/r/20260223-for-upstream-eyeq7h-v3-15-621d004d1a21@mobileye.com
Signed-off-by: Anup Patel <anup@brainfault.org>
This commit is contained in:
Vladimir Kondratiev
2026-02-23 16:54:54 +02:00
committed by Anup Patel
parent df7bbe7c2e
commit bdec423074
4 changed files with 59 additions and 44 deletions
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26
platform/generic/mips/boston.c
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@@ -43,30 +43,12 @@ static int boston_early_init(bool cold_boot)
if (rc)
return rc;
if (cold_boot) {
unsigned long cm_base = p8700_cm_info->gcr_base[0];
if (!cold_boot)
return 0;
/* For the CPC mtime region, the minimum size is 0x10000. */
rc = sbi_domain_root_add_memrange(cm_base, SIZE_FOR_CPC_MTIME,
P8700_ALIGN,
(SBI_DOMAIN_MEMREGION_MMIO |
SBI_DOMAIN_MEMREGION_M_READABLE |
SBI_DOMAIN_MEMREGION_M_WRITABLE));
if (rc)
return rc;
rc = mips_p8700_add_memranges();
/* For the APLIC and ACLINT m-mode region */
rc = sbi_domain_root_add_memrange(cm_base + AIA_OFFSET, SIZE_FOR_AIA_M_MODE,
P8700_ALIGN,
(SBI_DOMAIN_MEMREGION_MMIO |
SBI_DOMAIN_MEMREGION_M_READABLE |
SBI_DOMAIN_MEMREGION_M_WRITABLE));
if (rc)
return rc;
}
return 0;
return rc;
}
static int boston_nascent_init(void)