From bdec42307472f86f523db6414eb8ab4cae415561 Mon Sep 17 00:00:00 2001 From: Vladimir Kondratiev Date: Mon, 23 Feb 2026 16:54:54 +0200 Subject: [PATCH] platform: generic: mips p8700: CPU clusters memranges Reserve memory regions for CPU clusters according to P8700 cluster memory layout. There's a set of components in the CPU cluster according to [1] [1] https://mips.com/wp-content/uploads/2025/11/P8700-F_Programmers_Reference_Manual-TM.pdf Signed-off-by: Vladimir Kondratiev Reviewed-by: Anup Patel Link: https://lore.kernel.org/r/20260223-for-upstream-eyeq7h-v3-15-621d004d1a21@mobileye.com Signed-off-by: Anup Patel --- platform/generic/include/mips/p8700.h | 1 + platform/generic/mips/boston.c | 26 +++----------- platform/generic/mips/eyeq7h.c | 25 ++----------- platform/generic/mips/p8700.c | 51 +++++++++++++++++++++++++++ 4 files changed, 59 insertions(+), 44 deletions(-) diff --git a/platform/generic/include/mips/p8700.h b/platform/generic/include/mips/p8700.h index ad7353f8..4cda183e 100644 --- a/platform/generic/include/mips/p8700.h +++ b/platform/generic/include/mips/p8700.h @@ -192,6 +192,7 @@ struct p8700_cache_info { void mips_p8700_cache_info(struct p8700_cache_info *l1d, struct p8700_cache_info *l1i, struct p8700_cache_info *l2); +int mips_p8700_add_memranges(void); struct fdt_match; int mips_p8700_platform_init(const void *fdt, int nodeoff, const struct fdt_match *match); diff --git a/platform/generic/mips/boston.c b/platform/generic/mips/boston.c index 86e14c1e..ece60a7e 100644 --- a/platform/generic/mips/boston.c +++ b/platform/generic/mips/boston.c @@ -43,30 +43,12 @@ static int boston_early_init(bool cold_boot) if (rc) return rc; - if (cold_boot) { - unsigned long cm_base = p8700_cm_info->gcr_base[0]; + if (!cold_boot) + return 0; - /* For the CPC mtime region, the minimum size is 0x10000. */ - rc = sbi_domain_root_add_memrange(cm_base, SIZE_FOR_CPC_MTIME, - P8700_ALIGN, - (SBI_DOMAIN_MEMREGION_MMIO | - SBI_DOMAIN_MEMREGION_M_READABLE | - SBI_DOMAIN_MEMREGION_M_WRITABLE)); - if (rc) - return rc; + rc = mips_p8700_add_memranges(); - /* For the APLIC and ACLINT m-mode region */ - rc = sbi_domain_root_add_memrange(cm_base + AIA_OFFSET, SIZE_FOR_AIA_M_MODE, - P8700_ALIGN, - (SBI_DOMAIN_MEMREGION_MMIO | - SBI_DOMAIN_MEMREGION_M_READABLE | - SBI_DOMAIN_MEMREGION_M_WRITABLE)); - if (rc) - return rc; - - } - - return 0; + return rc; } static int boston_nascent_init(void) diff --git a/platform/generic/mips/eyeq7h.c b/platform/generic/mips/eyeq7h.c index 816ac6f5..c6e688e2 100644 --- a/platform/generic/mips/eyeq7h.c +++ b/platform/generic/mips/eyeq7h.c @@ -277,28 +277,9 @@ static int eyeq7h_early_init(bool cold_boot) * 0x08_00000000 0x10_00000000 M:---- S:-RWX DDR64 * 0x10_00000000 0x20_00000000 M:---- S:IRW- PCI64 BARs */ - - for (int i = 0; i < p8700_cm_info->num_cm; i++) { - unsigned long cm_base = p8700_cm_info->gcr_base[i]; - - /* CM and MTIMER */ - rc = sbi_domain_root_add_memrange(cm_base, SIZE_FOR_CPC_MTIME, - SIZE_FOR_CPC_MTIME, - (SBI_DOMAIN_MEMREGION_MMIO | - SBI_DOMAIN_MEMREGION_M_READABLE | - SBI_DOMAIN_MEMREGION_M_WRITABLE)); - if (rc) - return rc; - - /* For the APLIC and ACLINT m-mode region */ - rc = sbi_domain_root_add_memrange(cm_base + AIA_OFFSET, SIZE_FOR_AIA_M_MODE, - SIZE_FOR_AIA_M_MODE, - (SBI_DOMAIN_MEMREGION_MMIO | - SBI_DOMAIN_MEMREGION_M_READABLE | - SBI_DOMAIN_MEMREGION_M_WRITABLE)); - if (rc) - return rc; - } + rc = mips_p8700_add_memranges(); + if (rc) + return rc; /* the rest of MMIO - shared with S-mode */ rc = sbi_domain_root_add_memrange(MMIO_BASE, MMIO_SIZE, MMIO_SIZE, SBI_DOMAIN_MEMREGION_MMIO | diff --git a/platform/generic/mips/p8700.c b/platform/generic/mips/p8700.c index 4e693bc0..c2f41ee7 100644 --- a/platform/generic/mips/p8700.c +++ b/platform/generic/mips/p8700.c @@ -168,6 +168,57 @@ void mips_p8700_cache_info(struct p8700_cache_info *l1d, struct p8700_cache_info } } +/** + * See CPU cluster memory map in the table below + * To save PMP regions, group areas with M mode access, marked (1) and (2) + * + * GCR_BASE offset | | | Block Name | Description + * 0x00000 - 0x01FFF | M | ^ | GCR.Global | Per-cluster CM registers. + * 0x02000 - 0x05FFF | M | | | GCR.Core | Per-core CM registers. + * 0x06000 - 0x07FFF | - |(1)| Reserved. + * 0x08000 - 0x09FFF | M | | | CPC.Global | Per-cluster CPC registers. + * 0x0A000 - 0x0EFFF | M | | | CPC.Core | Per-core/Per-device CPC registers. + * 0x0F000 - 0x0FFFF | - | v | Reserved. + * 0x10000 - 0x1FFFF | S | | uGCR | Reserved for user defined CM registers. + * 0x20000 - 0x3EFFF | - | | Reserved. + * 0x3F000 - 0x3F0FF | ? | | FDC.Global | FDC.Global registers. + * 0x3F100 - 0x3FFFF | ? | | TRF.Global | TRF.Global registers + * 0x40000 - 0x4BFFF | M | ^ | APLIC.M | APLIC Machine registers. + * 0x4C000 - 0x4CFFF | M |(2)| APLIC.custom | APLIC custom registers. + * 0x4D000 - 0x4FFFF | - | | | Reserved. + * 0x50000 - 0x5FFFF | M | v | ACLINT.M | ACLINT Machine registers. + * 0x60000 - 0x6BFFF | S | | APLIC.S | APLIC Supervisor registers. + * 0x6C000 - 0x6FFFF | S | | ACLINT.S | ACLINT Supervisor registers. + * 0x70000 - 0x7EFFF | - | | Reserved. + * 0x7F000 - 0x7FFFF | S | | GCR.U | User Mode GCRs. + */ +int mips_p8700_add_memranges(void) +{ + int rc = SBI_OK; + for (int i = 0; i < p8700_cm_info->num_cm; i++) { + unsigned long cm_base = p8700_cm_info->gcr_base[i]; + + /* CM and MTIMER */ + rc = sbi_domain_root_add_memrange(cm_base, SIZE_FOR_CPC_MTIME, + SIZE_FOR_CPC_MTIME, + (SBI_DOMAIN_MEMREGION_MMIO | + SBI_DOMAIN_MEMREGION_M_READABLE | + SBI_DOMAIN_MEMREGION_M_WRITABLE)); + if (rc) + return rc; + + /* For the APLIC and ACLINT m-mode region */ + rc = sbi_domain_root_add_memrange(cm_base + AIA_OFFSET, SIZE_FOR_AIA_M_MODE, + SIZE_FOR_AIA_M_MODE, + (SBI_DOMAIN_MEMREGION_MMIO | + SBI_DOMAIN_MEMREGION_M_READABLE | + SBI_DOMAIN_MEMREGION_M_WRITABLE)); + if (rc) + return rc; + } + return rc; +} + int mips_p8700_platform_init(const void *fdt, int nodeoff, const struct fdt_match *match) { const struct p8700_cm_info *data = match->data;