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https://github.com/riscv-software-src/opensbi.git
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lib: sbi_irqchip: Support irqchip device targetting subset of harts
It is possible to have platform where an irqchip device targets a subset of harts and there are multiple irqchip devices to cover all harts. To support this scenario: 1) Add target_harts hartmask to struct sbi_irqchip_device which represents the set of harts targetted by the irqchip device 2) Call warm_init() and process_hwirqs() callbacks of an irqchip device on a hart only if irqchip device targets that particular hart Signed-off-by: Anup Patel <anup.patel@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260213055342.3124872-6-anup.patel@oss.qualcomm.com Signed-off-by: Anup Patel <anup@brainfault.org>
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@@ -10,6 +10,7 @@
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#ifndef __SBI_IRQCHIP_H__
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#define __SBI_IRQCHIP_H__
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#include <sbi/sbi_hartmask.h>
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#include <sbi/sbi_list.h>
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#include <sbi/sbi_types.h>
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@@ -20,11 +21,14 @@ struct sbi_irqchip_device {
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/** Node in the list of irqchip devices */
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struct sbi_dlist node;
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/** Set of harts targetted by this irqchip */
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struct sbi_hartmask target_harts;
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/** Initialize per-hart state for the current hart */
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int (*warm_init)(struct sbi_irqchip_device *chip);
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/** Process hardware interrupts from this irqchip */
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int (*process_hwirqs)(void);
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int (*process_hwirqs)(struct sbi_irqchip_device *chip);
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};
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/**
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@@ -38,7 +42,7 @@ struct sbi_irqchip_device {
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int sbi_irqchip_process(void);
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/** Register an irqchip device to receive callbacks */
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void sbi_irqchip_add_device(struct sbi_irqchip_device *chip);
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int sbi_irqchip_add_device(struct sbi_irqchip_device *chip);
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/** Initialize interrupt controllers */
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int sbi_irqchip_init(struct sbi_scratch *scratch, bool cold_boot);
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@@ -10,36 +10,65 @@
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#include <sbi/sbi_irqchip.h>
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#include <sbi/sbi_list.h>
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#include <sbi/sbi_platform.h>
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#include <sbi/sbi_scratch.h>
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struct sbi_irqchip_hart_data {
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struct sbi_irqchip_device *chip;
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};
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static unsigned long irqchip_hart_data_off;
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static SBI_LIST_HEAD(irqchip_list);
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static int default_irqfn(void)
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{
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return SBI_ENODEV;
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}
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static int (*ext_irqfn)(void) = default_irqfn;
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int sbi_irqchip_process(void)
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{
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return ext_irqfn();
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struct sbi_irqchip_hart_data *hd;
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hd = sbi_scratch_thishart_offset_ptr(irqchip_hart_data_off);
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if (!hd || !hd->chip || !hd->chip->process_hwirqs)
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return SBI_ENODEV;
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return hd->chip->process_hwirqs(hd->chip);
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}
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void sbi_irqchip_add_device(struct sbi_irqchip_device *chip)
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int sbi_irqchip_add_device(struct sbi_irqchip_device *chip)
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{
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sbi_list_add_tail(&chip->node, &irqchip_list);
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struct sbi_irqchip_hart_data *hd;
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struct sbi_scratch *scratch;
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u32 h;
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if (chip->process_hwirqs)
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ext_irqfn = chip->process_hwirqs;
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if (!chip || !sbi_hartmask_weight(&chip->target_harts))
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return SBI_EINVAL;
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if (chip->process_hwirqs) {
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sbi_hartmask_for_each_hartindex(h, &chip->target_harts) {
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scratch = sbi_hartindex_to_scratch(h);
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if (!scratch)
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continue;
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hd = sbi_scratch_offset_ptr(scratch, irqchip_hart_data_off);
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if (hd->chip && hd->chip != chip)
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return SBI_EINVAL;
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hd->chip = chip;
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}
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}
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sbi_list_add_tail(&chip->node, &irqchip_list);
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return 0;
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}
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int sbi_irqchip_init(struct sbi_scratch *scratch, bool cold_boot)
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{
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int rc;
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const struct sbi_platform *plat = sbi_platform_ptr(scratch);
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struct sbi_irqchip_hart_data *hd;
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struct sbi_irqchip_device *chip;
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int rc;
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if (cold_boot) {
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irqchip_hart_data_off =
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sbi_scratch_alloc_offset(sizeof(struct sbi_irqchip_hart_data));
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if (!irqchip_hart_data_off)
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return SBI_ENOMEM;
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rc = sbi_platform_irqchip_init(plat);
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if (rc)
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return rc;
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@@ -48,12 +77,15 @@ int sbi_irqchip_init(struct sbi_scratch *scratch, bool cold_boot)
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sbi_list_for_each_entry(chip, &irqchip_list, node) {
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if (!chip->warm_init)
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continue;
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if (!sbi_hartmask_test_hartindex(current_hartindex(), &chip->target_harts))
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continue;
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rc = chip->warm_init(chip);
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if (rc)
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return rc;
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}
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if (ext_irqfn != default_irqfn)
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hd = sbi_scratch_thishart_offset_ptr(irqchip_hart_data_off);
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if (hd && hd->chip && hd->chip->process_hwirqs)
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csr_set(CSR_MIE, MIP_MEIP);
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return 0;
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@@ -61,6 +93,9 @@ int sbi_irqchip_init(struct sbi_scratch *scratch, bool cold_boot)
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void sbi_irqchip_exit(struct sbi_scratch *scratch)
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{
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if (ext_irqfn != default_irqfn)
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struct sbi_irqchip_hart_data *hd;
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hd = sbi_scratch_thishart_offset_ptr(irqchip_hart_data_off);
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if (hd && hd->chip && hd->chip->process_hwirqs)
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csr_clear(CSR_MIE, MIP_MEIP);
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}
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@@ -297,8 +297,18 @@ int aplic_cold_irqchip_init(struct aplic_data *aplic)
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return rc;
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}
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if (aplic->num_idc) {
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for (i = 0; i < aplic->num_idc; i++)
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sbi_hartmask_set_hartindex(aplic->idc_map[i],
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&aplic->irqchip.target_harts);
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} else {
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sbi_hartmask_set_all(&aplic->irqchip.target_harts);
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}
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/* Register irqchip device */
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sbi_irqchip_add_device(&aplic->irqchip);
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rc = sbi_irqchip_add_device(&aplic->irqchip);
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if (rc)
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return rc;
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/* Attach to the aplic list */
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sbi_list_add_tail(&aplic->node, &aplic_list);
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@@ -147,7 +147,7 @@ int imsic_get_target_file(u32 hartindex)
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return imsic_get_hart_file(scratch);
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}
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static int imsic_process_hwirqs(void)
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static int imsic_process_hwirqs(struct sbi_irqchip_device *chip)
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{
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ulong mirq;
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@@ -391,7 +391,10 @@ int imsic_cold_irqchip_init(struct imsic_data *imsic)
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}
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/* Register irqchip device */
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sbi_irqchip_add_device(&imsic_device);
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sbi_hartmask_set_all(&imsic_device.target_harts);
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rc = sbi_irqchip_add_device(&imsic_device);
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if (rc)
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return rc;
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/* Register IPI device */
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sbi_ipi_add_device(&imsic_ipi_device);
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@@ -276,11 +276,10 @@ int plic_cold_irqchip_init(struct plic_data *plic)
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continue;
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plic_set_hart_data_ptr(sbi_hartindex_to_scratch(i), plic);
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sbi_hartmask_set_hartindex(i, &plic->irqchip.target_harts);
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}
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/* Register irqchip device */
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plic->irqchip.warm_init = plic_warm_irqchip_init;
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sbi_irqchip_add_device(&plic->irqchip);
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return 0;
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return sbi_irqchip_add_device(&plic->irqchip);
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}
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