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https://github.com/riscv-software-src/opensbi.git
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b55bb4cdcb
It is possible to have platform where an irqchip device targets a subset of harts and there are multiple irqchip devices to cover all harts. To support this scenario: 1) Add target_harts hartmask to struct sbi_irqchip_device which represents the set of harts targetted by the irqchip device 2) Call warm_init() and process_hwirqs() callbacks of an irqchip device on a hart only if irqchip device targets that particular hart Signed-off-by: Anup Patel <anup.patel@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260213055342.3124872-6-anup.patel@oss.qualcomm.com Signed-off-by: Anup Patel <anup@brainfault.org>
102 lines
2.3 KiB
C
102 lines
2.3 KiB
C
/*
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* SPDX-License-Identifier: BSD-2-Clause
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*
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* Copyright (c) 2022 Ventana Micro Systems Inc.
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*
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* Authors:
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* Anup Patel <apatel@ventanamicro.com>
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*/
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#include <sbi/sbi_irqchip.h>
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#include <sbi/sbi_list.h>
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#include <sbi/sbi_platform.h>
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#include <sbi/sbi_scratch.h>
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struct sbi_irqchip_hart_data {
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struct sbi_irqchip_device *chip;
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};
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static unsigned long irqchip_hart_data_off;
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static SBI_LIST_HEAD(irqchip_list);
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int sbi_irqchip_process(void)
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{
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struct sbi_irqchip_hart_data *hd;
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hd = sbi_scratch_thishart_offset_ptr(irqchip_hart_data_off);
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if (!hd || !hd->chip || !hd->chip->process_hwirqs)
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return SBI_ENODEV;
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return hd->chip->process_hwirqs(hd->chip);
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}
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int sbi_irqchip_add_device(struct sbi_irqchip_device *chip)
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{
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struct sbi_irqchip_hart_data *hd;
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struct sbi_scratch *scratch;
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u32 h;
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if (!chip || !sbi_hartmask_weight(&chip->target_harts))
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return SBI_EINVAL;
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if (chip->process_hwirqs) {
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sbi_hartmask_for_each_hartindex(h, &chip->target_harts) {
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scratch = sbi_hartindex_to_scratch(h);
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if (!scratch)
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continue;
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hd = sbi_scratch_offset_ptr(scratch, irqchip_hart_data_off);
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if (hd->chip && hd->chip != chip)
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return SBI_EINVAL;
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hd->chip = chip;
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}
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}
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sbi_list_add_tail(&chip->node, &irqchip_list);
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return 0;
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}
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int sbi_irqchip_init(struct sbi_scratch *scratch, bool cold_boot)
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{
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const struct sbi_platform *plat = sbi_platform_ptr(scratch);
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struct sbi_irqchip_hart_data *hd;
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struct sbi_irqchip_device *chip;
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int rc;
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if (cold_boot) {
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irqchip_hart_data_off =
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sbi_scratch_alloc_offset(sizeof(struct sbi_irqchip_hart_data));
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if (!irqchip_hart_data_off)
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return SBI_ENOMEM;
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rc = sbi_platform_irqchip_init(plat);
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if (rc)
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return rc;
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}
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sbi_list_for_each_entry(chip, &irqchip_list, node) {
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if (!chip->warm_init)
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continue;
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if (!sbi_hartmask_test_hartindex(current_hartindex(), &chip->target_harts))
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continue;
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rc = chip->warm_init(chip);
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if (rc)
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return rc;
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}
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hd = sbi_scratch_thishart_offset_ptr(irqchip_hart_data_off);
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if (hd && hd->chip && hd->chip->process_hwirqs)
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csr_set(CSR_MIE, MIP_MEIP);
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return 0;
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}
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void sbi_irqchip_exit(struct sbi_scratch *scratch)
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{
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struct sbi_irqchip_hart_data *hd;
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hd = sbi_scratch_thishart_offset_ptr(irqchip_hart_data_off);
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if (hd && hd->chip && hd->chip->process_hwirqs)
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csr_clear(CSR_MIE, MIP_MEIP);
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}
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