Mirrors/opensbi
4
0
Fork 1
mirror of https://github.com/riscv-software-src/opensbi.git synced 2026-02-28 02:01:50 +00:00
Code Issues Packages Projects Releases Wiki Activity

lib: utils/suspend: add Andes ATCSMU suspend driver

Browse Source 
Implement a system-wide suspend driver for the Andes AE350 platform.
This driver supports Andes-specific deep sleep (suspend to RAM) and
light sleep (suspend to standby) functionalities via the ATCSMU.

The major differences between deep sleep and light sleep are:

- Power Domain and Resume Path: Deep sleep powers down the core domain.
  Consequently, harts waking from deep sleep resume from the reset
  vector. Light sleep utilizes clock gating to the core domain; harts
  maintain state and resume execution at the instruction immediately
  following the WFI instruction.

- Primary Hart Wakeup: In both modes, the primary hart is woken by
  UART or RTC alarm interrupts. In deep sleep, the primary hart is
  additionally responsible for re-enabling the Last Level Cache (LLC)
  and restoring Andes-specific CSRs.

- Secondary Hart Wakeup: In light sleep, secondary harts are woken
  by an IPI sent from the primary hart. In deep sleep, they are
  woken by an ATCSMU hardware wake-up command. Furthermore,
  secondary harts must restore Andes-specific CSRs when returning
  from deep sleep.

Signed-off-by: Ben Zong-You Xie <ben717@andestech.com>
Signed-off-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Link: https://lore.kernel.org/r/20251229071914.1451587-6-ben717@andestech.com
Signed-off-by: Anup Patel <anup@brainfault.org>
This commit is contained in:
Ben Zong-You Xie
2025-12-29 15:19:14 +08:00
committed by Anup Patel
parent 82b0961821
commit b27ecec76b
7 changed files with 178 additions and 10 deletions
Download Patch File Download Diff File Expand all files Collapse all files

10
platform/generic/andes/ae350.c
View File

@@ -8,9 +8,12 @@
#include <andes/andes_pmu.h>
#include <andes/andes_sbi.h>
#include <platform_override.h>
#include <sbi/sbi_ecall_interface.h>
#include <sbi/riscv_asm.h>
#include <sbi/sbi_init.h>
#include <sbi/sbi_scratch.h>
#include <sbi_utils/fdt/fdt_helper.h>
#include <sbi_utils/hsm/fdt_hsm_andes_atcsmu.h>
static unsigned long andes_hart_data_offset;
extern void _start_warm(void);
@@ -59,14 +62,17 @@ void ae350_enable_coherency_warmboot(void)
static int ae350_early_init(bool cold_boot)
{
u32 hartid = current_hartid();
u32 sleep_type = atcsmu_get_sleep_type(hartid);
if (cold_boot) {
andes_hart_data_offset = sbi_scratch_alloc_offset(sizeof(struct andes_hart_data));
if (!andes_hart_data_offset)
return SBI_ENOMEM;
}
/* Don't restore Andes CSRs during boot */
if (sbi_init_count(current_hartindex()))
/* Don't restore Andes CSRs during boot or wake up from light sleep */
if (sbi_init_count(current_hartindex()) && sleep_type == SBI_SUSP_SLEEP_TYPE_SUSPEND)
ae350_non_ret_restore(sbi_scratch_thishart_ptr());
return generic_early_init(cold_boot);

1
platform/generic/configs/defconfig
View File

@@ -62,6 +62,7 @@ CONFIG_FDT_SERIAL_UART8250=y
CONFIG_FDT_SERIAL_XILINX_UARTLITE=y
CONFIG_SERIAL_SEMIHOSTING=y
CONFIG_FDT_SUSPEND=y
CONFIG_FDT_SUSPEND_ANDES_ATCSMU=y
CONFIG_FDT_SUSPEND_RPMI=y
CONFIG_FDT_SUSPEND_SIFIVE_SMC0=y
CONFIG_FDT_TIMER=y