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b27ecec76b
Implement a system-wide suspend driver for the Andes AE350 platform. This driver supports Andes-specific deep sleep (suspend to RAM) and light sleep (suspend to standby) functionalities via the ATCSMU. The major differences between deep sleep and light sleep are: - Power Domain and Resume Path: Deep sleep powers down the core domain. Consequently, harts waking from deep sleep resume from the reset vector. Light sleep utilizes clock gating to the core domain; harts maintain state and resume execution at the instruction immediately following the WFI instruction. - Primary Hart Wakeup: In both modes, the primary hart is woken by UART or RTC alarm interrupts. In deep sleep, the primary hart is additionally responsible for re-enabling the Last Level Cache (LLC) and restoring Andes-specific CSRs. - Secondary Hart Wakeup: In light sleep, secondary harts are woken by an IPI sent from the primary hart. In deep sleep, they are woken by an ATCSMU hardware wake-up command. Furthermore, secondary harts must restore Andes-specific CSRs when returning from deep sleep. Signed-off-by: Ben Zong-You Xie <ben717@andestech.com> Signed-off-by: Leo Yu-Chi Liang <ycliang@andestech.com> Link: https://lore.kernel.org/r/20251229071914.1451587-6-ben717@andestech.com Signed-off-by: Anup Patel <anup@brainfault.org>
78 lines
2.0 KiB
Plaintext
78 lines
2.0 KiB
Plaintext
CONFIG_PLATFORM_ALLWINNER_D1=y
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CONFIG_PLATFORM_ANDES_AE350=y
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CONFIG_PLATFORM_ANDES_QILAI=y
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CONFIG_PLATFORM_ESWIN_EIC770X=y
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CONFIG_PLATFORM_OPENHWGROUP_ARIANE=y
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CONFIG_PLATFORM_OPENHWGROUP_OPENPITON=y
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CONFIG_PLATFORM_RENESAS_RZFIVE=y
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CONFIG_PLATFORM_SIFIVE_FU540=y
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CONFIG_PLATFORM_SIFIVE_FU740=y
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CONFIG_PLATFORM_SOPHGO_SG2042=y
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CONFIG_PLATFORM_STARFIVE_JH7110=y
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CONFIG_PLATFORM_THEAD=y
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CONFIG_PLATFORM_MIPS_P8700=y
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CONFIG_PLATFORM_SPACEMIT_K1=y
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CONFIG_FDT_CACHE=y
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CONFIG_FDT_CACHE_ANDES_LLCACHE=y
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CONFIG_FDT_CACHE_SIFIVE_CCACHE=y
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CONFIG_FDT_CACHE_SIFIVE_EC=y
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CONFIG_FDT_CACHE_SIFIVE_PL2=y
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CONFIG_FDT_CPPC=y
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CONFIG_FDT_CPPC_RPMI=y
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CONFIG_FDT_GPIO=y
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CONFIG_FDT_GPIO_DESIGNWARE=y
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CONFIG_FDT_GPIO_SIFIVE=y
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CONFIG_FDT_GPIO_STARFIVE=y
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CONFIG_FDT_HSM=y
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CONFIG_FDT_HSM_ANDES_ATCSMU=y
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CONFIG_FDT_HSM_RPMI=y
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CONFIG_FDT_HSM_SIFIVE_TMC0=y
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CONFIG_FDT_I2C=y
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CONFIG_FDT_I2C_SIFIVE=y
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CONFIG_FDT_I2C_DW=y
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CONFIG_FDT_IPI=y
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CONFIG_FDT_IPI_MSWI=y
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CONFIG_FDT_IPI_PLICSW=y
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CONFIG_FDT_IRQCHIP=y
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CONFIG_FDT_IRQCHIP_APLIC=y
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CONFIG_FDT_IRQCHIP_IMSIC=y
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CONFIG_FDT_IRQCHIP_PLIC=y
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CONFIG_FDT_MAILBOX=y
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CONFIG_RPMI_MAILBOX=y
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CONFIG_FDT_MAILBOX_RPMI_SHMEM=y
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CONFIG_FDT_REGMAP=y
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CONFIG_FDT_REGMAP_SYSCON=y
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CONFIG_FDT_RESET=y
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CONFIG_FDT_RESET_ATCWDT200=y
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CONFIG_FDT_RESET_GPIO=y
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CONFIG_FDT_RESET_HTIF=y
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CONFIG_FDT_RESET_RPMI=y
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CONFIG_FDT_RESET_SG2042_HWMON_MCU=y
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CONFIG_FDT_RESET_SUNXI_WDT=y
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CONFIG_FDT_RESET_SYSCON=y
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CONFIG_FDT_SERIAL=y
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CONFIG_FDT_SERIAL_CADENCE=y
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CONFIG_FDT_SERIAL_GAISLER=y
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CONFIG_FDT_SERIAL_HTIF=y
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CONFIG_FDT_SERIAL_RENESAS_SCIF=y
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CONFIG_FDT_SERIAL_SHAKTI=y
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CONFIG_FDT_SERIAL_SIFIVE=y
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CONFIG_FDT_SERIAL_LITEX=y
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CONFIG_FDT_SERIAL_UART8250=y
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CONFIG_FDT_SERIAL_XILINX_UARTLITE=y
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CONFIG_SERIAL_SEMIHOSTING=y
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CONFIG_FDT_SUSPEND=y
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CONFIG_FDT_SUSPEND_ANDES_ATCSMU=y
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CONFIG_FDT_SUSPEND_RPMI=y
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CONFIG_FDT_SUSPEND_SIFIVE_SMC0=y
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CONFIG_FDT_TIMER=y
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CONFIG_FDT_TIMER_MTIMER=y
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CONFIG_FDT_TIMER_PLMT=y
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CONFIG_FDT_MPXY=y
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CONFIG_FDT_MPXY_RPMI_MBOX=y
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CONFIG_FDT_MPXY_RPMI_CLOCK=y
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CONFIG_FDT_MPXY_RPMI_VOLTAGE=y
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CONFIG_FDT_MPXY_RPMI_DEVICE_POWER=y
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CONFIG_FDT_MPXY_RPMI_PERFORMANCE=y
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CONFIG_FDT_MPXY_RPMI_SYSMSI=y
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