mirror of
https://github.com/riscv-software-src/opensbi.git
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lib: utils/irqchip: Add FDT based driver for IMSIC
We add simple FDT irqchip driver for IMSIC so that generic platform (and other FDT based platforms) can utilize common IMIC library. Signed-off-by: Anup Patel <anup.patel@wdc.com> Signed-off-by: Anup Patel <apatel@ventanamicro.com> Reviewed-by: Atish Patra <atishp@rivosinc.com>
This commit is contained in:
@@ -68,6 +68,12 @@ int fdt_parse_uart8250_node(void *fdt, int nodeoffset,
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int fdt_parse_uart8250(void *fdt, struct platform_uart_data *uart,
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const char *compatible);
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struct imsic_data;
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bool fdt_check_imsic_mlevel(void *fdt);
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int fdt_parse_imsic_node(void *fdt, int nodeoff, struct imsic_data *imsic);
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struct plic_data;
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int fdt_parse_plic_node(void *fdt, int nodeoffset, struct plic_data *plic);
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@@ -13,6 +13,7 @@
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#include <sbi/sbi_platform.h>
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#include <sbi/sbi_scratch.h>
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#include <sbi_utils/fdt/fdt_helper.h>
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#include <sbi_utils/irqchip/imsic.h>
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#include <sbi_utils/irqchip/plic.h>
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#define DEFAULT_UART_FREQ 0
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@@ -465,6 +466,108 @@ int fdt_parse_uart8250(void *fdt, struct platform_uart_data *uart,
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return fdt_parse_uart8250_node(fdt, nodeoffset, uart);
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}
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bool fdt_check_imsic_mlevel(void *fdt)
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{
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const fdt32_t *val;
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int i, len, noff = 0;
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if (!fdt)
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return false;
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while ((noff = fdt_node_offset_by_compatible(fdt, noff,
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"riscv,imsics")) >= 0) {
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val = fdt_getprop(fdt, noff, "interrupts-extended", &len);
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if (val && len > sizeof(fdt32_t)) {
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len = len / sizeof(fdt32_t);
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for (i = 0; i < len; i += 2) {
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if (fdt32_to_cpu(val[i + 1]) == IRQ_M_EXT)
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return true;
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}
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}
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}
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return false;
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}
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int fdt_parse_imsic_node(void *fdt, int nodeoff, struct imsic_data *imsic)
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{
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const fdt32_t *val;
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struct imsic_regs *regs;
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uint64_t reg_addr, reg_size;
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int i, rc, len, nr_parent_irqs;
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if (nodeoff < 0 || !imsic || !fdt)
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return SBI_ENODEV;
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imsic->targets_mmode = false;
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val = fdt_getprop(fdt, nodeoff, "interrupts-extended", &len);
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if (val && len > sizeof(fdt32_t)) {
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len = len / sizeof(fdt32_t);
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nr_parent_irqs = len / 2;
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for (i = 0; i < len; i += 2) {
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if (fdt32_to_cpu(val[i + 1]) == IRQ_M_EXT) {
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imsic->targets_mmode = true;
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break;
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}
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}
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} else
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return SBI_EINVAL;
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val = fdt_getprop(fdt, nodeoff, "riscv,guest-index-bits", &len);
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if (val && len > 0)
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imsic->guest_index_bits = fdt32_to_cpu(*val);
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else
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imsic->guest_index_bits = 0;
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val = fdt_getprop(fdt, nodeoff, "riscv,hart-index-bits", &len);
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if (val && len > 0) {
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imsic->hart_index_bits = fdt32_to_cpu(*val);
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} else {
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imsic->hart_index_bits = sbi_fls(nr_parent_irqs);
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if ((1UL << imsic->hart_index_bits) < nr_parent_irqs)
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imsic->hart_index_bits++;
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}
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val = fdt_getprop(fdt, nodeoff, "riscv,group-index-bits", &len);
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if (val && len > 0)
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imsic->group_index_bits = fdt32_to_cpu(*val);
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else
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imsic->group_index_bits = 0;
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val = fdt_getprop(fdt, nodeoff, "riscv,group-index-shift", &len);
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if (val && len > 0)
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imsic->group_index_shift = fdt32_to_cpu(*val);
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else
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imsic->group_index_shift = 2 * IMSIC_MMIO_PAGE_SHIFT;
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val = fdt_getprop(fdt, nodeoff, "riscv,num-ids", &len);
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if (val && len > 0)
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imsic->num_ids = fdt32_to_cpu(*val);
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else
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return SBI_EINVAL;
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for (i = 0; i < IMSIC_MAX_REGS; i++) {
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regs = &imsic->regs[i];
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regs->addr = 0;
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regs->size = 0;
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}
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for (i = 0; i < (IMSIC_MAX_REGS - 1); i++) {
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regs = &imsic->regs[i];
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rc = fdt_get_node_addr_size(fdt, nodeoff, i,
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®_addr, ®_size);
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if (rc < 0 || !reg_addr || !reg_size)
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break;
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regs->addr = reg_addr;
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regs->size = reg_size;
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};
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if (!imsic->regs[0].size)
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return SBI_EINVAL;
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return 0;
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}
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int fdt_parse_plic_node(void *fdt, int nodeoffset, struct plic_data *plic)
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{
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int len, rc;
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@@ -12,9 +12,11 @@
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#include <sbi_utils/fdt/fdt_helper.h>
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#include <sbi_utils/irqchip/fdt_irqchip.h>
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extern struct fdt_irqchip fdt_irqchip_imsic;
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extern struct fdt_irqchip fdt_irqchip_plic;
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static struct fdt_irqchip *irqchip_drivers[] = {
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&fdt_irqchip_imsic,
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&fdt_irqchip_plic
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};
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106
lib/utils/irqchip/fdt_irqchip_imsic.c
Normal file
106
lib/utils/irqchip/fdt_irqchip_imsic.c
Normal file
@@ -0,0 +1,106 @@
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/*
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* SPDX-License-Identifier: BSD-2-Clause
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*
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* Copyright (c) 2021 Western Digital Corporation or its affiliates.
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* Copyright (c) 2022 Ventana Micro Systems Inc.
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*
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* Authors:
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* Anup Patel <anup.patel@wdc.com>
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*/
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#include <libfdt.h>
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#include <sbi/riscv_asm.h>
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#include <sbi/sbi_error.h>
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#include <sbi/sbi_hartmask.h>
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#include <sbi_utils/fdt/fdt_helper.h>
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#include <sbi_utils/irqchip/fdt_irqchip.h>
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#include <sbi_utils/irqchip/imsic.h>
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#define IMSIC_MAX_NR 16
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static unsigned long imsic_count = 0;
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static struct imsic_data imsic[IMSIC_MAX_NR];
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static int irqchip_imsic_update_hartid_table(void *fdt, int nodeoff,
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struct imsic_data *id)
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{
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const fdt32_t *val;
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u32 phandle, hwirq, hartid;
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int i, err, count, cpu_offset, cpu_intc_offset;
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val = fdt_getprop(fdt, nodeoff, "interrupts-extended", &count);
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if (!val || count < sizeof(fdt32_t))
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return SBI_EINVAL;
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count = count / sizeof(fdt32_t);
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for (i = 0; i < count; i += 2) {
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phandle = fdt32_to_cpu(val[i]);
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hwirq = fdt32_to_cpu(val[i + 1]);
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cpu_intc_offset = fdt_node_offset_by_phandle(fdt, phandle);
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if (cpu_intc_offset < 0)
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continue;
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cpu_offset = fdt_parent_offset(fdt, cpu_intc_offset);
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if (cpu_intc_offset < 0)
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continue;
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err = fdt_parse_hart_id(fdt, cpu_offset, &hartid);
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if (err)
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return SBI_EINVAL;
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if (SBI_HARTMASK_MAX_BITS <= hartid)
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return SBI_EINVAL;
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switch (hwirq) {
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case IRQ_M_EXT:
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err = imsic_map_hartid_to_data(hartid, id, i / 2);
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if (err)
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return err;
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break;
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default:
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break;
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}
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}
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return 0;
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}
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static int irqchip_imsic_cold_init(void *fdt, int nodeoff,
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const struct fdt_match *match)
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{
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int rc;
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struct imsic_data *id;
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if (IMSIC_MAX_NR <= imsic_count)
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return SBI_ENOSPC;
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id = &imsic[imsic_count];
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rc = fdt_parse_imsic_node(fdt, nodeoff, id);
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if (rc)
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return rc;
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if (!id->targets_mmode)
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return 0;
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rc = irqchip_imsic_update_hartid_table(fdt, nodeoff, id);
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if (rc)
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return rc;
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rc = imsic_cold_irqchip_init(id);
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if (rc)
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return rc;
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imsic_count++;
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return 0;
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}
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static const struct fdt_match irqchip_imsic_match[] = {
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{ .compatible = "riscv,imsics" },
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{ },
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};
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struct fdt_irqchip fdt_irqchip_imsic = {
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.match_table = irqchip_imsic_match,
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.cold_init = irqchip_imsic_cold_init,
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.warm_init = imsic_warm_irqchip_init,
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};
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@@ -8,6 +8,7 @@
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#
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libsbiutils-objs-y += irqchip/fdt_irqchip.o
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libsbiutils-objs-y += irqchip/fdt_irqchip_imsic.o
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libsbiutils-objs-y += irqchip/fdt_irqchip_plic.o
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libsbiutils-objs-y += irqchip/imsic.o
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libsbiutils-objs-y += irqchip/plic.o
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@@ -18,6 +18,7 @@
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#include <sbi_utils/fdt/fdt_helper.h>
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#include <sbi_utils/fdt/fdt_pmu.h>
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#include <sbi_utils/irqchip/fdt_irqchip.h>
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#include <sbi_utils/irqchip/imsic.h>
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#include <sbi_utils/serial/fdt_serial.h>
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#include <sbi_utils/timer/fdt_timer.h>
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#include <sbi_utils/ipi/fdt_ipi.h>
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@@ -56,6 +57,7 @@ static void fw_platform_lookup_special(void *fdt, int root_offset)
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}
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extern struct sbi_platform platform;
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static bool platform_has_mlevel_imsic = false;
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static u32 generic_hart_index2id[SBI_HARTMASK_MAX_BITS] = { 0 };
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/*
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@@ -110,6 +112,8 @@ unsigned long fw_platform_init(unsigned long arg0, unsigned long arg1,
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platform.hart_count = hart_count;
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platform_has_mlevel_imsic = fdt_check_imsic_mlevel(fdt);
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/* Return original FDT pointer */
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return arg1;
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@@ -118,6 +122,13 @@ fail:
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wfi();
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}
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static int generic_nascent_init(void)
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{
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if (platform_has_mlevel_imsic)
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imsic_local_irqchip_init();
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return 0;
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}
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static int generic_early_init(bool cold_boot)
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{
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if (!generic_plat || !generic_plat->early_init)
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@@ -210,6 +221,7 @@ static uint64_t generic_pmu_xlate_to_mhpmevent(uint32_t event_idx,
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}
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const struct sbi_platform_operations platform_ops = {
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.nascent_init = generic_nascent_init,
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.early_init = generic_early_init,
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.final_init = generic_final_init,
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.early_exit = generic_early_exit,
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